[
  {
    "cluster_id": "vVoLSldryY0J",
    "title": "Using Memristor Arrays as Physical Unclonable Functions",
    "authors": [
      "A Anagnostopoulos",
      "S Katzenbeisser"
    ],
    "first_author_last": "Anagnostopoulos",
    "year": null,
    "venue": "tolga.arul.de",
    "link": "https://tolga.arul.de/files/Frank2022_ESORICS.pdf",
    "doi": null,
    "cited_by": 0,
    "snippet": "… The memristor cells used in our work are so-called self-directed channel memristors [11]. … consists of an amorphous chalcogenide using tungsten as a dopant (W + Ge2Se3). This layer …",
    "pdf_url": "https://tolga.arul.de/files/Frank2022_ESORICS.pdf",
    "is_knowm": false,
    "is_sdc": true,
    "is_mss": true,
    "devices": [],
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": null,
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "16303362233189106715",
    "title": "TESTING THE SDC MEMRISTORS IN THREE PHASE SYSTEMS",
    "authors": [
      "K BEDNARZ",
      "B omiej GARDA"
    ],
    "first_author_last": "BEDNARZ",
    "year": 2025,
    "venue": "PRZEGLĄD ELEKTROTECHNICZNY",
    "link": "https://ptze.pl/wp-content/uploads/2024/06/materialy-konferencyjne-PTZE_Szklarska-Poreba-2024.pdf#page=29",
    "doi": "10.15199/48.2025.02.13",
    "cited_by": 0,
    "snippet": "… The tested device were chalcogenide ion-conducting resistive device commonly known as SDC memristors. To reduce the current all memristors have been connected in series with the …",
    "pdf_url": "https://ptze.pl/wp-content/uploads/2024/06/materialy-konferencyjne-PTZE_Szklarska-Poreba-2024.pdf#page=29",
    "is_knowm": false,
    "is_sdc": true,
    "is_mss": false,
    "devices": [],
    "abstract": "Wydawnictwo SIGMA-NOT wydaje czasopisma fachowe informujące swoich czytelników o najnowszych osiągnięciach naukowych i nowoczesnych rozwiązaniach technicznych w Polsce i na świecie, popularyzuje problemy techniczne oraz poszerza wiedzę i kulturę techniczną.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4407920737",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "15735647798260159202",
    "title": "Examination of the Reliability of a Robustness Test for the Self-Directed Channel Carbon-Based Memristors by Reading Their DC Resistance",
    "authors": [
      "CD Ercan",
      "E Karakulak",
      "R Mutlu"
    ],
    "first_author_last": "Ercan",
    "year": 2023,
    "venue": "Düzce Üniversitesi Bilim ve Teknoloji Dergisi",
    "link": "https://dergipark.org.tr/en/pub/dubited/article/1084460",
    "doi": "10.29130/dubited.1084460",
    "cited_by": 0,
    "snippet": "… on the SDC Carbon-based memristors to verify whether such a memristor is broken or not. … In this section, the SDC Carbon-based memristors produced by Knowm company [12] are …",
    "pdf_url": "https://dergipark.org.tr/en/download/article-file/2296550",
    "is_knowm": true,
    "is_sdc": true,
    "is_mss": false,
    "devices": [
      "C",
      "Sn",
      "W"
    ],
    "abstract": "An ideal memristor that has been theoretically predicted almost a half-century ago is a nonlinear power dissipating circuit element. Nowadays, memristive systems such as thin films which are not ideal memristors are also called memristors. Such systems have current-dependent behavior and nonlinear charge-dependent electrical resistance. Self-directed channel Carbon-, Tungsten-, Chrome-, and Tin-based memristors have become commercially available nowadays and they are used for research purposes. All circuit components must be tested before their usage. It is expected that memristors will become commonly used in electronic circuits in the future. However, the literature has just a few memristor tests reported. To the best of our knowledge, there is not a suggested robustness test for the self-directed channel Carbon-based memristors in the literature. In this study, A recently suggested memristor robustness test which could be made using just a multimeter is modified using a series resistor. The test is tried on the Self-Directed Channel Carbon-Based memristors. Unfortunately, the test is found unreliable and invalid for the self-Directed Channel Carbon-Based memristors.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://dergipark.org.tr/en/download/article-file/2296550",
    "openalex_id": "https://openalex.org/W4387832355",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "URCuwM6hawYJ",
    "title": "The memristor switching behavior from the energy point of view",
    "authors": [
      "B Garda"
    ],
    "first_author_last": "Garda",
    "year": 2018,
    "venue": "zet.agh.edu.pl",
    "link": "http://www.zet.agh.edu.pl/ncn2016memristors/presentations/GardaMemristorSwitchingMEMRISYS2018Poster.pdf",
    "doi": "10.1109/iolts.2018.8474167",
    "cited_by": 2,
    "snippet": "… Measurement tests of the self-directed channel (SDC) … of the layered chalcogenide materials Ge2Se3/SnSe/Ag [1]. … memristor under study is a self-directed-channel memristor [1] …",
    "pdf_url": "http://www.zet.agh.edu.pl/ncn2016memristors/presentations/GardaMemristorSwitchingMEMRISYS2018Poster.pdf",
    "is_knowm": false,
    "is_sdc": true,
    "is_mss": true,
    "devices": [],
    "abstract": "The technology of Resistive Switching (RS) devices (memristors) is continuously maturing on its way towards viable commercial establishment. So far, the change of resistance has been identified as a function of the applied pulse characteristics, such as amplitude and duration. However, parameter variability holds back any universal approach based on these two magnitudes, making also difficult even the qualitative comparison between different RS material compounds. On the contrary, there is a relevant magnitude which is much less affected by device variability; the energy. In this direction, we doubt anyone so far has ever wondered “what is the quantitative effect of the injected energy on the device state?” Interestingly, a first step was made recently towards the definition of performance parameters for this emerging device technology, using as fundamental parameter the energy. In this work, we further elaborate on such ideas, proving experimentally that the “resistance change per energy unit” $( dR/ dE )$ can be considered a significant magnitude in analog operation of bipolar memristors, being a key performance parameter worth of timely disclosure.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://hdl.handle.net/2117/130084",
    "openalex_id": "https://openalex.org/W2896336424",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "llm_verdict": "not-knowm",
    "llm_confidence": "medium",
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "KMi4ONHxjOAJ",
    "title": "Abstract submission template for MEMRISYS 2017 The memristor switching behavior from the energetic point of view",
    "authors": [
      "B Garda"
    ],
    "first_author_last": "Garda",
    "year": null,
    "venue": "zet.agh.edu.pl",
    "link": "http://www.zet.agh.edu.pl/ncn2016memristors/presentations/GardaMemristorSwitchingMEMRISYS2018.pdf",
    "doi": null,
    "cited_by": 0,
    "snippet": "… There were carried out some measurement tests over the self-directed channel (SDC) … an ion-conducting memristor comprised of the layered chalcogenide materials Ge2Se3/SnSe/Ag (…",
    "pdf_url": "http://www.zet.agh.edu.pl/ncn2016memristors/presentations/GardaMemristorSwitchingMEMRISYS2018.pdf",
    "is_knowm": false,
    "is_sdc": true,
    "is_mss": true,
    "devices": [],
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": null,
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "3434315774257480362",
    "title": "Resistive Switching Behavior seen from the Energy",
    "authors": [
      "J Gomez",
      "A Abusleme",
      "A Rubio",
      "I Vourkas"
    ],
    "first_author_last": "Gomez",
    "year": 2018,
    "venue": "academia.edu",
    "link": "https://www.academia.edu/download/95500808/Rubio_2008474167.pdf",
    "doi": "10.1109/iolts.2018.8474167",
    "cited_by": 2,
    "snippet": "… The BS-AF-W memristors developed by Knowm Inc are in a 16-pin DIP package. The PCB includes a MIC 7122YMM opamp for its wide Vsup range support, and a feedback resistor R,. …",
    "pdf_url": "https://www.academia.edu/download/95500808/Rubio_2008474167.pdf",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": true,
    "devices": [],
    "abstract": "The technology of Resistive Switching (RS) devices (memristors) is continuously maturing on its way towards viable commercial establishment. So far, the change of resistance has been identified as a function of the applied pulse characteristics, such as amplitude and duration. However, parameter variability holds back any universal approach based on these two magnitudes, making also difficult even the qualitative comparison between different RS material compounds. On the contrary, there is a relevant magnitude which is much less affected by device variability; the energy. In this direction, we doubt anyone so far has ever wondered “what is the quantitative effect of the injected energy on the device state?” Interestingly, a first step was made recently towards the definition of performance parameters for this emerging device technology, using as fundamental parameter the energy. In this work, we further elaborate on such ideas, proving experimentally that the “resistance change per energy unit” $( dR/ dE )$ can be considered a significant magnitude in analog operation of bipolar memristors, being a key performance parameter worth of timely disclosure.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://hdl.handle.net/2117/130084",
    "openalex_id": "https://openalex.org/W2896336424",
    "relevance": "excluded",
    "review_screen": "unclear",
    "review_reason": "weak use cues: experimental, experiment",
    "llm_verdict": "not-knowm",
    "llm_confidence": "medium",
    "pdf_knowm": null,
    "knowm_role": null
  },
  {
    "cluster_id": "HH3UiGDuMNAJ",
    "title": "Memristors in Neural Networks",
    "authors": [
      "RL Murrer III"
    ],
    "first_author_last": "III",
    "year": null,
    "venue": "commandpattern.org",
    "link": "https://commandpattern.org/wp-content/uploads/2023/08/rmurrer_vlsi_memristor_paper_formatted.pdf",
    "doi": null,
    "cited_by": 0,
    "snippet": "… devices that include memristors currently. In 2015 a company KNOWM was formed and … Currently you can purchase a 16x1 array of memristors of various material types from KNOWM …",
    "pdf_url": "https://commandpattern.org/wp-content/uploads/2023/08/rmurrer_vlsi_memristor_paper_formatted.pdf",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": null,
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "ZKiqDV36FmcJ",
    "title": "Diseño y simulación de redes neuronales basadas en memristores Design and simulation of memristor-based neural networks.",
    "authors": [
      "PA Lázaro",
      "IJ Gallo",
      "GB Juan",
      "FJ Molinos"
    ],
    "first_author_last": "Lázaro",
    "year": null,
    "venue": "docta.ucm.es",
    "link": "https://docta.ucm.es/rest/api/core/bitstreams/ae6a2b86-5f54-4bd6-a56d-be81a328d3c5/content",
    "doi": null,
    "cited_by": 0,
    "snippet": "… memristors functioning properly, we can now begin to conduct our own experiments using KNOWM’s memristors through the Memristor Discovery … on the Discovery board itself, where …",
    "pdf_url": "https://docta.ucm.es/rest/api/core/bitstreams/ae6a2b86-5f54-4bd6-a56d-be81a328d3c5/content",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": true,
    "devices": [],
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": null,
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "OrFVHjSwzfEJ",
    "title": "A New Simple Chaotic Circuit Based on Memristor",
    "authors": [
      "C Wang"
    ],
    "first_author_last": "Wang",
    "year": 2016,
    "venue": "International Journal of Bifurcation and Chaos",
    "link": "http://csee.hnu.edu.cn/Content/UploadFiles/2005236/Files/cd617dbf-1f0d-48b3-9a59-e6d1c9d506d2.pdf",
    "doi": "10.1142/s0218127416501455",
    "cited_by": 80,
    "snippet": "… memristor, the knowm memristor is formed by metal W, Ag and Chalcogenide. However, the cost of fabricating knowm memristor is … and design the memristor models and emulators. In …",
    "pdf_url": "http://csee.hnu.edu.cn/Content/UploadFiles/2005236/Files/cd617dbf-1f0d-48b3-9a59-e6d1c9d506d2.pdf",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "In this paper, a new memristor is proposed, and then an emulator built from off-the-shelf solid state components imitating the behavior of the proposed memristor is presented. Multisim simulation and breadboard experiment are done on the emulator, exhibiting a pinched hysteresis loop in the voltage–current plane when the emulator is driven by a periodic excitation voltage. In addition, a new simple chaotic circuit is designed by using the proposed memristor and other circuit elements. It is exciting that this circuit with only a linear negative resistor, a capacitor, an inductor and a memristor can generate a chaotic attractor. The dynamical behaviors of the proposed chaotic system are analyzed by Lyapunov exponents, phase portraits and bifurcation diagrams. Finally, an electronic circuit is designed to implement the chaotic system. For the sake of simple circuit topology, the proposed chaotic circuit can be easily manufactured at low cost.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W2516138848",
    "relevance": "cites",
    "review_screen": "likely-cite-only",
    "review_reason": "cite/other-device cues: emulator, proposed memristor, new memristor, simulation",
    "pdf_knowm": "cites",
    "knowm_role": "cites"
  },
  {
    "cluster_id": "3UkUReCg7q0J",
    "title": "Ternary Combinational Logic Gates Design Based on Tri-Valued Memristors",
    "authors": [
      "XY Wang",
      "X Li",
      "P Li",
      "Z Chen"
    ],
    "first_author_last": "Wang",
    "year": 2023,
    "venue": "SSRN Electronic Journal",
    "link": "https://papers.ssrn.com/sol3/papers.cfm?abstract_id=4489169",
    "doi": "10.2139/ssrn.4489169",
    "cited_by": 1,
    "snippet": "… In 2015, Knowm Inc Company designed and produced a voltage … binary memristor called Knowm memristor. In this paper, by modifying the expression of G(v) of the Knowm memristor …",
    "pdf_url": "https://papers.ssrn.com/sol3/Delivery.cfm?abstractid=4489169",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": "http://dx.doi.org/10.2139/ssrn.4489169",
    "openalex_id": "https://openalex.org/W4381886655",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-model",
    "knowm_role": "uses-model"
  },
  {
    "cluster_id": "11741744475281555779",
    "title": "Emulating short-term synaptic dynamics with memristive devices",
    "authors": [
      "R Berdan",
      "E Vasilaki",
      "A Khiat",
      "G Indiveri",
      "A Serb"
    ],
    "first_author_last": "Berdan",
    "year": 2016,
    "venue": "Scientific Reports",
    "link": "https://www.nature.com/articles/srep18639",
    "doi": "10.1038/srep18639",
    "cited_by": 139,
    "snippet": "… 2 memristors can exhibit non-associative plasticity phenomena observed in biological synapses, supported by their metastable … Exploiting metastable switching dynamics for processing …",
    "pdf_url": "https://www.nature.com/articles/srep18639.pdf",
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": true,
    "devices": [],
    "abstract": "Neuromorphic architectures offer great promise for achieving computation capacities beyond conventional Von Neumann machines. The essential elements for achieving this vision are highly scalable synaptic mimics that do not undermine biological fidelity. Here we demonstrate that single solid-state TiO2 memristors can exhibit non-associative plasticity phenomena observed in biological synapses, supported by their metastable memory state transition properties. We show that, contrary to conventional uses of solid-state memory, the existence of rate-limiting volatility is a key feature for capturing short-term synaptic dynamics. We also show how the temporal dynamics of our prototypes can be exploited to implement spatio-temporal computation, demonstrating the memristors full potential for building biophysically realistic neural processing systems.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://www.nature.com/articles/srep18639.pdf",
    "openalex_id": "https://openalex.org/W2100385534",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-model",
    "knowm_role": "uses-model"
  },
  {
    "cluster_id": "14987719445923361105",
    "title": "More than Moore. Experience on material implication computing with an electromechanical memristor emulator",
    "authors": [
      "S Zuin Castillo"
    ],
    "first_author_last": "Castillo",
    "year": 2016,
    "venue": "",
    "link": "https://upcommons.upc.edu/entities/publication/584c0db0-e7d0-477c-8c2e-670a0c0ae162",
    "doi": "10.1109/ssci.2016.7850154",
    "cited_by": 1,
    "snippet": "… Knowm Memristors are devices which its principal performance is done because an electric field. This electric field induced ions through a metal multilayer material stack [Figure 6]. …",
    "pdf_url": "https://upcommons.upc.edu/bitstreams/845b022a-421f-47f0-9d10-d5a105983dfb/download",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "Memristors are being considered as a promising emerging device able to introduce new paradigms in both data storage and computing. In this paper the authors introduce the concept of a quasi-ideal experimental device that emulates the fundamental behavior of a memristor based on an electromechanical organization. By using this emulator, results about the experimental implementation of an unconventional material implication-based data-path equivalent to the i-4004 are presented and experimentally demonstrated. The use of the proposed quasi-ideal device allows the evaluation of this new computing paradigm, based on the resistance domain, without incorporating the disturbance of process and cycle to cycle variabilities observed in real nowadays devices that cause a limit in yield and behavior.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://hdl.handle.net/2117/101683",
    "openalex_id": "https://openalex.org/W2588872044",
    "relevance": "cites",
    "review_screen": "likely-cite-only",
    "review_reason": "cite/other-device cues: emulator",
    "pdf_knowm": "cites",
    "knowm_role": "cites"
  },
  {
    "cluster_id": "17786698160696761736",
    "title": "An experience with chalcogenide memristors, and implications on memory and computer applications",
    "authors": [
      "M Escudero-López",
      "E Amat",
      "A Rubio"
    ],
    "first_author_last": "Escudero-López",
    "year": 2016,
    "venue": "Conference on …",
    "link": "https://ieeexplore.ieee.org/abstract/document/7845387/",
    "doi": "10.1109/dcis.2016.7845387",
    "cited_by": 2,
    "snippet": "… DEVICE CHARACTERISTICS Memristors used in this study are manufactured by Knowm company [5]. The principal operation of these devices is based on the generation and …",
    "pdf_url": "https://repository.tudelft.nl/file/File_fd5dd0f1-fa55-44b9-8ddb-920f28986223",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "Memristors are considered a promising emerging device that may improve some specific applications, like memories, or make feasible new ones, mainly alternative computing architectures. However, it is not a mature technology and their characteristics can vary significantly depending on their structures. Also, variability and reliability might suppose an important issue in some applications. In this paper, a chalcogenide memristor is studied and their main parameters are extracted. Then, it's discused how their properties can affect two applications: a memory circuit and a digital computing alternative, the logic implication technique.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W2586744819",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "llm_verdict": "uncertain",
    "llm_confidence": "medium",
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "8159377785153980208",
    "title": "Evaluating ternary adders using a hybrid memristor/CMOS approach",
    "authors": [
      "D Fey"
    ],
    "first_author_last": "Fey",
    "year": 2016,
    "venue": "arXiv preprint arXiv:1701.00065",
    "link": "https://arxiv.org/abs/1701.00065",
    "doi": null,
    "cited_by": 4,
    "snippet": "… curve for a memristor starts to show a slope. Furthermore, we consider a statistical model for one of the first commercially available memristors, namely the memristors from Knowm [10]. …",
    "pdf_url": "https://arxiv.org/pdf/1701.00065",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "This paper investigates the potentials of using a hybrid memristor CMOS technology, called MeMOS, for the realisation of ternary adders. Ternary adders exploit the qualitative advantage of multi-value storage capability of memristors compared to conventional CMOS flip-flops storing only binary values in one cell. Furthermore they carry out an addition in $O(1)$ and are therefore considered. The MeMOS approach is compared to a CMOS solution for the ternary adders using multi value memristors as registers concerning the achievable latency and the energy consumption. It is shown that using the TEAM, VTEAM model and a model considering commercially available memristors from Known the approach of using CMOS ternary adders using memristors as multi-value register memory is to prefer. MeMOS circuits have advantages for a static operation mode, i.e. if they are operated after a reset.",
    "abstract_source": "semanticscholar",
    "oa_pdf_url": null,
    "openalex_id": null,
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-model",
    "knowm_role": "uses-model"
  },
  {
    "cluster_id": "ItIqpSh5unQJ",
    "title": "Memristor variants and models from Knowm",
    "authors": [
      "E Korczynski"
    ],
    "first_author_last": "Korczynski",
    "year": 2016,
    "venue": "SOLID STATE TECHNOLOGY",
    "link": "",
    "doi": null,
    "cited_by": 0,
    "snippet": "",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": null,
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "named-in-abstract"
  },
  {
    "cluster_id": "18241928675217209828",
    "title": "Did the memristor breakthroug (finally) occur?",
    "authors": [
      "T Lecklider"
    ],
    "first_author_last": "Lecklider",
    "year": 2016,
    "venue": "EE: Evaluation Engineering",
    "link": "https://search.ebscohost.com/login.aspx?direct=true&profile=ehost&scope=site&authtype=crawler&jrnl=01490370&asa=N&AN=118536456&h=WuG2w2%2F%2FocgopZYIOaYNkfP4InRYBNgrBqNOwc%2BlBCOxnZpIHJsHKfIFmS%2BpIlRog7DXS6PJgK8unBGRB45Y4g%3D%3D&crl=c",
    "doi": null,
    "cited_by": 0,
    "snippet": "… and make com mercially available memristors with bidirectional incremental … Knowm's memristors are capable of bidirectional incremental learning.... With this ad vancement, Knowm …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": null,
    "relevance": "core",
    "review_screen": null,
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    "pdf_knowm": null,
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    "human_verdict": "uses-knowm-device",
    "human_reason": "YES (user)"
  },
  {
    "cluster_id": "10551629993982335667",
    "title": "The generalized metastable switch memristor model",
    "authors": [
      "TW Molter",
      "MA Nugent"
    ],
    "first_author_last": "Molter",
    "year": 2016,
    "venue": "CNNA ; 15th International …",
    "link": "https://ieeexplore.ieee.org/abstract/document/7827960/",
    "doi": null,
    "cited_by": 74,
    "snippet": "… As the number of channels increases, the memristor will become more incremental as it … as a metastable switch (MSS) and the conductance of a collection of metastable switches …",
    "pdf_url": "https://arxiv.org/pdf/1608.04659",
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": true,
    "devices": [],
    "abstract": "Memristor device modeling is currently a heavily researched topic and is becoming ever more important as memristor devices make their way into CMOS circuit designs, necessitating accurate and efficient memristor circuit simulations. In this paper, the Generalized Metastable Switch (MSS) memristor model is presented. The Generalized MSS model consists of a voltage-dependent stochastic component and a voltage-dependent exponential diode current component and is designed to be easy to implement, computationally efficient, and amenable to modeling a wide range of different memristor devices.",
    "abstract_source": "ieee-xplore",
    "oa_pdf_url": null,
    "openalex_id": null,
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-model",
    "knowm_role": "uses-model"
  },
  {
    "cluster_id": "9721567928242759914",
    "title": "Machine Learning with Memristors via Thermodynamic RAM",
    "authors": [
      "TW Molter",
      "MA Nugent"
    ],
    "first_author_last": "Molter",
    "year": 2016,
    "venue": "CNNA ; 15th International …",
    "link": "https://ieeexplore.ieee.org/abstract/document/7827977/",
    "doi": null,
    "cited_by": 2,
    "snippet": "… Machine Learning Capabilities with Thermodynamic RAM and the Knowm API (http://knowm.org/machine-learningcapabilities-with-thermodynamic-ram-and-the-knowm-api/), and a …",
    "pdf_url": "https://arxiv.org/pdf/1608.04105",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": true,
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    "abstract": "Thermodynamic RAM (kT-RAM) is a neuromemristive co-processor design based on the theory of AHaH Computing and implemented via CMOS and memristors. The co-processor is a 2-D array of differential memristor pairs (synapses) that can be selectively coupled together (neurons) via the digital bit addressing of the underlying CMOS RAM circuitry. The chip is designed to plug into existing digital computers and be interacted with via a simple instruction set. Anti-Hebbian and Hebbian (AHaH) computing forms the theoretical framework from which a nature-inspired type of computing architecture is built where, unlike von Neumann architectures, memory and processor are physically combined for synaptic operations. Through exploitation of AHaH attractor states, memristor-based circuits converge to attractor basins that represents machine learning solutions such as unsupervised feature learning, supervised classification and anomaly detection. Because kT-RAM eliminates the need to shuttle bits back and forth between memory and processor and can operate at very low voltage levels, it can significantly surpass CPU, GPU, and FPGA performance for synaptic integration and learning operations. Here, we present a memristor technology developed for use in kT-RAM, in particular bi-directional incremental adaptation of conductance via short low-voltage (<1.0 V, <1.0 muS) pulses.",
    "abstract_source": "ieee-xplore",
    "oa_pdf_url": null,
    "openalex_id": null,
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-model",
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  },
  {
    "cluster_id": "nz39bJ8hDAYJ",
    "title": "Design and Simulation of a Quaternary Memory Cell based on a Physical Memristor",
    "authors": [
      "A Nannarelli",
      "J Taylor"
    ],
    "first_author_last": "Nannarelli",
    "year": 2016,
    "venue": "IEEE Nordic Circuits and Systems …",
    "link": "https://orbit.dtu.dk/en/publications/design-and-simulation-of-a-quaternary-memory-cell-based-on-a-phys/",
    "doi": "10.1109/norchip.2016.7792884",
    "cited_by": 2,
    "snippet": "… of these physical memristors by designing a memristorbased … memristor is currently being manufactured by Knowm Inc. [3]. In the following we describe the testing of BS-AF-W memristor …",
    "pdf_url": "https://orbit.dtu.dk/files/127421938/Memory_memristor_Nannarelli.pdf",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": true,
    "devices": [],
    "abstract": "Memristors were theorized more than fifty years ago, but only recently physical devices with memristor's behavior have been fabricated and shipped. In this work, we experiment on one of these physical memristors by designing a memristor-based memory cell, implementing the cell, and testing it. Our experiments demonstrate that the memristor technology is not yet mature for practical applications, but, nevertheless, when production will provide reliable and dependable devices, memristor-based memory systems may replace CMOS memories with some advantages.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://orbit.dtu.dk/en/publications/8ecd8303-7588-4147-a4ed-eb24db4e8bbe",
    "openalex_id": "https://openalex.org/W2563435441",
    "relevance": "excluded",
    "review_screen": "likely-use",
    "review_reason": "use cues: physical memristor, experiment",
    "llm_verdict": "uncertain",
    "llm_confidence": "medium",
    "human_verdict": "not-knowm",
    "human_reason": "NO (user)",
    "pdf_knowm": null,
    "knowm_role": null
  },
  {
    "cluster_id": "11363431029930167708",
    "title": "A memristor based ultrasonic transducer: The memosducer",
    "authors": [
      "S Dos Santos",
      "S Furui"
    ],
    "first_author_last": "Santos",
    "year": 2016,
    "venue": "IEEE International Ultrasonics …",
    "link": "https://ieeexplore.ieee.org/abstract/document/7728885/",
    "doi": "10.1109/ultsym.2016.7728885",
    "cited_by": 16,
    "snippet": "… 16 BSAF-W tiers 1,2 and 3 commercialized memristors (Knowm … The simplicity of the proposed coupling between memristors … of 16 BS-AF-W tiers 1,2 and 3 commercialized memristors (…",
    "pdf_url": "https://www.researchgate.net/profile/Serge-Dos-Santos/publication/309773031_A_memristor_based_ultrasonic_transducer_The_memosducer/links/5a095c500f7e9b68229cf63b/A-memristor-based-ultrasonic-transducer-The-memosducer.pdf",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": true,
    "devices": [],
    "abstract": "We suggest an experimental realization for a new concept of chaotic transducer based on memristors and specifically devoted to the optimization of ultrasonic excitation involved in nonlinear time reversal based ultrasonic imaging. The design utilizes hysteretic properties of a Knowm Inc memristor, considered as the new key electronic component used in mimicking elementary cells plasticity and biological neuronal systems as humain brain. Due to the memristor ability to include nonlinear and memory based properties in the time domain, complex time delays activated by a suitable distribution of array of memristors is equivalent to the acoustic response of multiple scattering and multiple reflections in waves guides as inside chaotic cavities. Instead being an hindrance, it actually improves the focusing properties of the Time Reversal (TR) based Nonlinear Elastic Wave Spectroscopy (NEWS) methods aim at measuring local nonlinear signature of complex damaged systems. Consequently, the memristor based TR-NEWS device induces a new focusing family of ultrasonic transducers modified by the presence of memory properties. Like the memcapacitor and the meminductor, the memosducer constitutes the memory based improved new generation of ultrasonic transducing devices devoted to nonlinear acoustic imaging.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W2547849175",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "named-in-abstract"
  },
  {
    "cluster_id": "14652309378461698938",
    "title": "Design and simulation of a quaternary memory cell based on a physical memristor",
    "authors": [
      "J Taylor",
      "A Nannarelli"
    ],
    "first_author_last": "Taylor",
    "year": 2016,
    "venue": "IEEE Nordic Circuits and Systems …",
    "link": "https://ieeexplore.ieee.org/abstract/document/7792884/",
    "doi": "10.1109/norchip.2016.7792884",
    "cited_by": 2,
    "snippet": "… of these physical memristors by designing a memristorbased … memristor is currently being manufactured by Knowm Inc. [3]. In the following we describe the testing of BS-AF-W memristor …",
    "pdf_url": "https://scholar.archive.org/work/wz7udrrxejgi7fupwwpmfunyjm/access/wayback/https://core.ac.uk/download/pdf/84001579.pdf",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": true,
    "devices": [],
    "abstract": "Memristors were theorized more than fifty years ago, but only recently physical devices with memristor's behavior have been fabricated and shipped. In this work, we experiment on one of these physical memristors by designing a memristor-based memory cell, implementing the cell, and testing it. Our experiments demonstrate that the memristor technology is not yet mature for practical applications, but, nevertheless, when production will provide reliable and dependable devices, memristor-based memory systems may replace CMOS memories with some advantages.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://orbit.dtu.dk/en/publications/8ecd8303-7588-4147-a4ed-eb24db4e8bbe",
    "openalex_id": "https://openalex.org/W2563435441",
    "relevance": "excluded",
    "review_screen": "likely-use",
    "review_reason": "use cues: physical memristor, experiment",
    "llm_verdict": "uncertain",
    "llm_confidence": "medium",
    "human_verdict": "not-knowm",
    "human_reason": "NO (user)",
    "pdf_knowm": null,
    "knowm_role": null
  },
  {
    "cluster_id": "428182733021014726",
    "title": "1-D memristor networks as ternary storage cells",
    "authors": [
      "I Vourkas",
      "A Abusleme",
      "GC Sirakoulis"
    ],
    "first_author_last": "Vourkas",
    "year": 2016,
    "venue": "CNNA ; 15th …",
    "link": "https://ieeexplore.ieee.org/abstract/document/7827978/",
    "doi": null,
    "cited_by": 5,
    "snippet": "… memristors, as means to create voltagecontrolled ternary memristive switches (TMS). We demonstrate that the number of memristors … experimental validation using the KNOWM.ORG …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "Due to its inherent analog nature, the memristor can store information in a continuous form, being thus well-suited for compact multi-bit memory cell technology. In this context, threshold-type switching devices show great retention and switching speed, but still poor controllability. To this end, in this work we use one-dimensional (1-D) networks of anti-serially connected threshold-type memristors, as means to create voltage-controlled ternary memristive switches (TMS). We demonstrate that the number of memristors and their polarity define the memristance corresponding to the different stored information. We present a simulation-based study of their performance using a threshold-type switching model of bipolar voltage-controlled memristors, and comment on the applied programming-pulse characteristics and the most important device-level properties.",
    "abstract_source": "ieee-xplore",
    "oa_pdf_url": null,
    "openalex_id": null,
    "relevance": "excluded",
    "review_screen": "unclear",
    "review_reason": "no strong cues",
    "pdf_knowm": null,
    "knowm_role": null,
    "human_verdict": "not-knowm",
    "human_reason": "NO (user)"
  },
  {
    "cluster_id": "2986474348425905464",
    "title": "A new simple chaotic circuit based on memristor",
    "authors": [
      "R Wu",
      "C Wang"
    ],
    "first_author_last": "Wu",
    "year": 2016,
    "venue": "International Journal of Bifurcation and Chaos",
    "link": "https://www.worldscientific.com/doi/abs/10.1142/S0218127416501455",
    "doi": "10.1142/S0218127416501455",
    "cited_by": 80,
    "snippet": "… memristor, the knowm memristor is formed by metal W, Ag and Chalcogenide. However, the cost of fabricating knowm memristor … sary to research and design the memristor models and …",
    "pdf_url": "http://csee.hnu.edu.cn/Content/UploadFiles/2005236/Files/980f7c3f-d1f9-4741-9cde-e7b52c4f93dd.pdf",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "In this paper, a new memristor is proposed, and then an emulator built from off-the-shelf solid state components imitating the behavior of the proposed memristor is presented. Multisim simulation and breadboard experiment are done on the emulator, exhibiting a pinched hysteresis loop in the voltage–current plane when the emulator is driven by a periodic excitation voltage. In addition, a new simple chaotic circuit is designed by using the proposed memristor and other circuit elements. It is exciting that this circuit with only a linear negative resistor, a capacitor, an inductor and a memristor can generate a chaotic attractor. The dynamical behaviors of the proposed chaotic system are analyzed by Lyapunov exponents, phase portraits and bifurcation diagrams. Finally, an electronic circuit is designed to implement the chaotic system. For the sake of simple circuit topology, the proposed chaotic circuit can be easily manufactured at low cost.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W2516138848",
    "relevance": "cites",
    "review_screen": "likely-cite-only",
    "review_reason": "cite/other-device cues: emulator, proposed memristor, new memristor, simulation",
    "pdf_knowm": "cites",
    "knowm_role": "cites"
  },
  {
    "cluster_id": "13484348715100945711",
    "title": "Experience on material implication computing with an electromechanical memristor emulator",
    "authors": [
      "S Zuin",
      "M Escudero-Lopez",
      "F Moll"
    ],
    "first_author_last": "Zuin",
    "year": 2016,
    "venue": "IEEE …",
    "link": "https://ieeexplore.ieee.org/abstract/document/7850154/",
    "doi": "10.1109/ssci.2016.7850154",
    "cited_by": 1,
    "snippet": "… In the case shown we are considering a chalcogenide memristor manufactured by the KNOWM company [11], [12]. The different colored curves correspond just to repetitive cycles of set …",
    "pdf_url": "https://upcommons.upc.edu/bitstreams/7ae05d4f-fe3d-4ef0-b1bc-4c0cf2599239/download",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "Memristors are being considered as a promising emerging device able to introduce new paradigms in both data storage and computing. In this paper the authors introduce the concept of a quasi-ideal experimental device that emulates the fundamental behavior of a memristor based on an electromechanical organization. By using this emulator, results about the experimental implementation of an unconventional material implication-based data-path equivalent to the i-4004 are presented and experimentally demonstrated. The use of the proposed quasi-ideal device allows the evaluation of this new computing paradigm, based on the resistance domain, without incorporating the disturbance of process and cycle to cycle variabilities observed in real nowadays devices that cause a limit in yield and behavior.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://hdl.handle.net/2117/101683",
    "openalex_id": "https://openalex.org/W2588872044",
    "relevance": "cites",
    "review_screen": "likely-cite-only",
    "review_reason": "cite/other-device cues: emulator",
    "pdf_knowm": "cites",
    "knowm_role": "cites"
  },
  {
    "cluster_id": "4408144684565927605",
    "title": "… approach to Memristive Devices and its applications on Stateful Logic: Design and experimental evaluation of the IMPLY logic gate with Knowm memristors",
    "authors": [
      "AE Galofre Ballbe"
    ],
    "first_author_last": "Ballbe",
    "year": 2017,
    "venue": "",
    "link": "https://upcommons.upc.edu/entities/publication/a513d43c-06ab-417d-9277-8e3a539d135d",
    "doi": null,
    "cited_by": 0,
    "snippet": "… The memristors provided by Knowm operate … memristors provided by Knowm. These differ from each other by the metal introduced in the metal chalcogenide layer, Tungsten, Chromium …",
    "pdf_url": "https://upcommons.upc.edu/bitstreams/8e18fb78-2530-4819-8160-aca225310e29/download",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": null,
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "M4eX04v1taMJ",
    "title": "… to Memristive Devices and its applications on Stateful Logic: Design and experimental evaluation of the IMPLY logic gate with Knowm memristors",
    "authors": [
      "G Ballbe",
      "A Elisabeth"
    ],
    "first_author_last": "Ballbe",
    "year": 2017,
    "venue": "",
    "link": "",
    "doi": null,
    "cited_by": 0,
    "snippet": "",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": null,
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "18397999106514960894",
    "title": "Self-directed channel memristor for high temperature operation",
    "authors": [
      "KA Campbell"
    ],
    "first_author_last": "Campbell",
    "year": 2016,
    "venue": "Microelectronics Journal",
    "link": "https://www.sciencedirect.com/science/article/pii/S0026269216303779",
    "doi": "10.1016/j.mejo.2016.11.006",
    "cited_by": 143,
    "snippet": "… The type of memristor described in this work is an ion-… into channels within the device active layer to change the device resistance. This memristor, referred to as a self-directed channel (…",
    "pdf_url": "https://www.sciencedirect.com/science/article/am/pii/S0026269216303779",
    "is_knowm": false,
    "is_sdc": true,
    "is_mss": false,
    "devices": [],
    "abstract": "Ion-conducting memristors comprised of the layered chalcogenide materials Ge2Se3/SnSe/Ag are described. The memristor, termed a self-directed channel (SDC) device, can be classified as a generic memristor and can tolerate continuous high temperature operation (at least 150 °C). Unlike other chalcogenide-based ion conducting device types, the SDC device does not require complicated fabrication steps, such as photodoping or thermal annealing, making these devices faster and more reliable to fabricate. Device pulsed response shows fast state switching in the 10−9 s range. Device cycling at both room temperature and 140 °C show write endurance of at least 1 billion.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://doi.org/10.1016/j.mejo.2016.11.006",
    "openalex_id": "https://openalex.org/W2510112518",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "a9_t2MJxcpAJ",
    "title": "Using LT-Spice Circuit Modeling to Investigate the Effects of Changing the Metal-Selenide Layer in the Self-Directed Channel Memristor",
    "authors": [
      "D Lloyd"
    ],
    "first_author_last": "Lloyd",
    "year": 2017,
    "venue": "",
    "link": "https://scholarworks.boisestate.edu/icur/2017/Poster_Session/105/",
    "doi": null,
    "cited_by": 0,
    "snippet": "… for several self-directed channel (SDC) memristor device types … device response using the Yakopcic memristor model. Each device … model of the SDC memristor device and an improved …",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": true,
    "is_mss": false,
    "devices": [],
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": null,
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "named-in-abstract"
  },
  {
    "cluster_id": "11425374184176087416",
    "title": "Design of a multi-level memory cell with new emerging non-volatile memristive technology",
    "authors": [
      "EA i Llucià"
    ],
    "first_author_last": "Llucià",
    "year": 2017,
    "venue": "",
    "link": "https://upcommons.upc.edu/bitstreams/8fa61372-0a4e-4619-b797-5218a6a911db/download",
    "doi": null,
    "cited_by": 0,
    "snippet": "… Knowm Memristors The Knowm Memristor devices (www.knowm.org), which are used in this … The Knowm memristors we are going to use come in a 16 PIN ceramic DIP (Dual Inline …",
    "pdf_url": "https://upcommons.upc.edu/bitstreams/8fa61372-0a4e-4619-b797-5218a6a911db/download",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": null,
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "11216050355231365316",
    "title": "Memristor state transition in reconfigurable microwave filter",
    "authors": [
      "I Marković",
      "M Potrebić",
      "D Tošić"
    ],
    "first_author_last": "Marković",
    "year": 2017,
    "venue": "IEEE 30th International …",
    "link": "https://ieeexplore.ieee.org/abstract/document/8190071/",
    "doi": "10.1109/miel.2017.8190071",
    "cited_by": 7,
    "snippet": "… memristors do not require any bias, and there are no moving parts involved. In this paper, we propose that memristors could … On the other side, KnowM [3] fabricated memristors for lower …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "Memristors are promising candidates to enhance performances in RF/microwave circuits, because memristors do not require any bias, and there are no moving parts involved. In this paper, we propose that memristors could be used as switches for designing a reconfigurable microwave filter. Results obtained using Pi's model for RF/microwave simulations are presented. For the memristor state transition, we use Biolek's model. The model is resistive and it is used for the proof-of-concept transient analysis of idealized microwave circuits.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W2773055405",
    "relevance": "excluded",
    "review_screen": "unclear",
    "review_reason": "no strong cues",
    "llm_verdict": "not-knowm",
    "llm_confidence": "high",
    "pdf_knowm": null,
    "knowm_role": null
  },
  {
    "cluster_id": "7926550170020658627",
    "title": "From memristors to compositional machine learning: Exploring neuromemristive algorithmic abstractions with the knowm api",
    "authors": [
      "A Nugent",
      "T Molter"
    ],
    "first_author_last": "Nugent",
    "year": 2017,
    "venue": "Proceedings of the Neuromorphic Computing …",
    "link": "https://dl.acm.org/doi/abs/10.1145/3183584.3183615",
    "doi": "10.1145/3183584.3183615",
    "cited_by": 0,
    "snippet": "… All devices which demonstrate such a response are termed memristors. For our purposes of exploring machine learning function, we require memristor models that can be tuned to the …",
    "pdf_url": "https://dl.acm.org/doi/pdf/10.1145/3183584.3183615",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "Due to the recent congruence of big data and compute acceleration, the field of machine learning (ML) has made significant advancements, driven primarily by deep neural networks trained with the stochastic gradient descent algorithm (DNN). Error rates on challenging learning benchmarks have fallen precipitously. The algorithmic success of DNNs combined with the significant architectural mismatch between modern processors and neural architectures has resulted in a race to build DNN processors. The mismatch is demonstrated by analyzing the dynamic power consumption due to capacitive loss associated with synaptic access:",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://dl.acm.org/doi/pdf/10.1145/3183584.3183615",
    "openalex_id": "https://openalex.org/W2802783863",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "15302273829752673404",
    "title": "Acousto-mechanical instrumentation of multiscale hysteretic memristive properties of the skin with nonlinear time reversal imaging",
    "authors": [
      "S Dos Santos",
      "M Lints",
      "A Masood"
    ],
    "first_author_last": "Santos",
    "year": 2017,
    "venue": "Cosmetic …",
    "link": "https://ieeexplore.ieee.org/abstract/document/8521466/",
    "doi": "10.1109/comet.2017.8521466",
    "cited_by": 1,
    "snippet": "… The intrinsic hysteretic behavior of the memristor is included in the ultrasonic excitation … array of 16 BS-AF-W tiers 1,2 and 3 commercialized memristors (Knowm Inc, Santa Fe, USA). …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": true,
    "devices": [],
    "abstract": "The aim of this paper is to present an acousto-mechanical based experiment for skin ageing characterization using the Nonlinear Time Reversal signal processing tool known to extract, in a complex medium, sources of multiscale non-linearity potentially responsible of skin ageing process. New biomarkers of the porcine skin ageing are identified thanks to an optimized mixture of Preisach-Mayergoyz distributions extracted experimentally. Then each hysteretic elementary unit is supposed to be identified with a electronic memristor with suitable memory resistance controlled electronically.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W2900002824",
    "relevance": "excluded",
    "review_screen": "likely-use",
    "review_reason": "use cues: experimental, experiment, characteriz",
    "llm_verdict": "not-knowm",
    "llm_confidence": "high",
    "pdf_knowm": null,
    "knowm_role": null
  },
  {
    "cluster_id": "15614506813153820644",
    "title": "Memristor‐enhanced humanoid robot control system–Part I: Theory behind the novel memcomputing paradigm",
    "authors": [
      "A Ascoli",
      "D Baumann",
      "R Tetzlaff"
    ],
    "first_author_last": "Ascoli",
    "year": 2017,
    "venue": "International Journal of Circuit Theory and Applications",
    "link": "https://onlinelibrary.wiley.com/doi/abs/10.1002/cta.2431",
    "doi": "10.1002/cta.2431",
    "cited_by": 23,
    "snippet": "… memristor. In the companion part II paper40, adopting a couple of distinct memristor models, one from the class of ideal memristors … dynamics of a real nanodevice from Knowm, Inc.43, …",
    "pdf_url": "https://onlinelibrary.wiley.com/doi/am-pdf/10.1002/cta.2431",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "Summary Myon is a humanoid robot where each joint is controlled independently by a supervised bio‐inspired artificial neural network inducing the correction of a number of distinct actions depending on the excitation. One of the control strategies, which the network, located within a certain joint, may implement, allows a controlled motion of the limb connected to the joint from a stable state up to a prescribed height and the maintenance of the new position afterwards. The original approach adopted for this control operation is stable and robust but results in slow and energy‐inefficient limb movements. This work proposes a novel, low‐power, time‐efficient and adaptive memristor‐centred control strategy for the aforementioned robot action. The idea is based upon the exploitation of the combined ability of memristors to store and process data in the same physical location. The part I paper sets the theoretic foundations for the memcomputing paradigm to robot motion control, while the part II manuscript shall demonstrate its benefits over the original approach in terms of energy, and speed, and the inheritance from the standard strategy of a good level of adaptability to changes in the limb load on the basis of the analysis of circuit‐theoretic models adopting an ideal and a real memristor, respectively. Copyright © 2017 John Wiley &amp; Sons, Ltd.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W2773805230",
    "relevance": "excluded",
    "review_screen": "unclear",
    "review_reason": "weak use cues: real memristor",
    "llm_verdict": "not-knowm",
    "llm_confidence": "medium",
    "pdf_knowm": null,
    "knowm_role": null
  },
  {
    "cluster_id": "469607913680149669",
    "title": "Memristor‐enhanced humanoid robot control system–Part II: Circuit theoretic model and performance analysis",
    "authors": [
      "D Baumann",
      "A Ascoli",
      "R Tetzlaff"
    ],
    "first_author_last": "Baumann",
    "year": 2017,
    "venue": "International Journal of Circuit Theory and Applications",
    "link": "https://onlinelibrary.wiley.com/doi/abs/10.1002/cta.2430",
    "doi": "10.1002/cta.2430",
    "cited_by": 23,
    "snippet": "… The reason behind our choice to apply a non-null pulse across the Knowm memristor at the beginning of each drive phase only provided the modulus of the inverting integrator output …",
    "pdf_url": "http://www.neurorobotik.de/downloads/publications/Baumann_et_al-2018-International_Journal_of_Circuit_Theory_and_Applications.pdf",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "Summary Neuromorphic circuits shall be considered in electronics to perform complex computing tasks in a time‐efficient and energy‐efficient fashion and to adapt their problem‐solving methodologies to changes in initial conditions and parameters. One of the key biological paradigms at the basis of their operation, allowing them to exhibit higher performance levels as compared with state‐of‐the‐art electronic systems, is the mem‐computing functionality, i.e. the capability to process and store data in the same physical location, which represents the core principle to overcome the time inefficiency of von Neumann machine architectures. With the advent of memristors, the interest in the exploitation of this principle to develop dynamic circuits for the implementation of innovative signal processing strategies has grown considerably. Here, we leverage the mem‐computing capability inherent in these devices to propose an innovative control system for motion control in a humanoid robot. In the part I paper, we introduced the paradigm theoretic foundations. In this part II manuscript, we propose circuit‐theoretic models for the new control system based upon an ideal and upon a physical memristor model and demonstrate through numerical simulations how it outperforms the old approach in terms of time‐efficiency and energy‐efficiency, maintaining a good degree of adaptability to changes in environmental conditions.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://onlinelibrary.wiley.com/doi/pdfdirect/10.1002/cta.2430",
    "openalex_id": "https://openalex.org/W2795157148",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "llm_verdict": "not-knowm",
    "llm_confidence": "medium",
    "pdf_knowm": "uses-model",
    "knowm_role": "uses-model"
  },
  {
    "cluster_id": "2580294836093675021",
    "title": "An Optically Gated Transistor Composed of Amorphous M + Ge2Se3 (M = Cu or Sn) for Accessing and Continuously Programming a Memristor",
    "authors": [
      "KA Campbell",
      "RA Bassine",
      "MF Kabir"
    ],
    "first_author_last": "Campbell",
    "year": 2018,
    "venue": "ACS Applied Electronic Materials",
    "link": "https://pubs.acs.org/doi/abs/10.1021/acsaelm.8b00034",
    "doi": "10.1021/acsaelm.8b00034",
    "cited_by": 12,
    "snippet": "… The memristor used in this work operates under a similar mechanism as the self-directed channel memristor, (34) except that it contains a sandwiched layer of cosputtered W–Ge 2 Se 3 …",
    "pdf_url": "https://pubs.acs.org/doi/pdf/10.1021/acsaelm.8b00034",
    "is_knowm": false,
    "is_sdc": true,
    "is_mss": true,
    "devices": [],
    "abstract": "We demonstrate that a device composed of sputtered amorphous chalcogenide Ge2Se3/M + Ge2Se3 (M = Sn or Cu) alternating layers functions as an optically gated transistor (OGT) and can be used as an access transistor for a memristor memory element. This transistor has only two electrically connected terminals (source and drain), with the gate being optically controlled, thus allowing the transistor to operate only in the presence of light (385-1200 nm). The switching speed of OGTs is < 15 μs. The OGT is demonstrated in series with the Ge2Se3 + W memristor, where we show that by alternating the light intensity on the OGT gate, the memristor can be programmed to a continuous range of nonvolatile memory states using the saturation current of the OGT as a programming compliance current. By having a continuous range of nonvolatile states, one memory cell can potentially achieve 2n levels. This high density, combined with optical programmability, enables hybrid electronic/photonic memory.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://doi.org/10.1021/acsaelm.8b00034",
    "openalex_id": "https://openalex.org/W2906215269",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "ANbDSQbP7HAJ",
    "title": "OXYGEN AND SILVER-OXYGEN DEFECTS IN Ge2Se3 ELECTROCHEMICAL METALLIZATION BRIDGE MEMRISTORS",
    "authors": [
      "JT Chen"
    ],
    "first_author_last": "Chen",
    "year": 2018,
    "venue": "",
    "link": "https://digitalrepository.unm.edu/ece_etds/449/",
    "doi": null,
    "cited_by": 0,
    "snippet": "… 6EMB memristors are also known as ionic memristors [11], … voltages of self-directed channel (SDC) memristor are 0 to 1 … SDC memristor is an EMB memristor and uses Ge2Se3, the …",
    "pdf_url": "https://digitalrepository.unm.edu/cgi/viewcontent.cgi?article=1447&context=ece_etds",
    "is_knowm": false,
    "is_sdc": true,
    "is_mss": true,
    "devices": [],
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": null,
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "named-in-abstract"
  },
  {
    "cluster_id": "7423194879121406328",
    "title": "On the variability-aware design of memristor-based logic circuits",
    "authors": [
      "M Escudero",
      "I Vourkas",
      "A Rubio"
    ],
    "first_author_last": "Escudero",
    "year": 2018,
    "venue": "IEEE 18th …",
    "link": "https://ieeexplore.ieee.org/abstract/document/8626367/",
    "doi": "10.1109/nano.2018.8626367",
    "cited_by": 5,
    "snippet": "… released by Knowm Inc. [14] who provided affordable access to real memristors. Therefore, … b) its importance in the design and evaluation of memristorbased circuits and systems. More …",
    "pdf_url": "https://upcommons.upc.edu/bitstreams/85c05579-f18c-4d57-8b0a-79babcad705c/download",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "Ever since the advent of the first TiO <sub xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sub> -based memristor and the respective linear model published by Hewlett-Packard Labs, several behavioral models of memristors have been published. Such models capture the fundamental characteristics of resistive switching behavior through simple equations and rules, so they received a lot of attention and contributed significantly to the fast progress of research in this new and emerging device technology field. However, while this technology is maturing, accurate physics-based models are being developed, which go deeper into the device dynamics and capture more details than what just would be the fundamentals: i.e. parasitics of the device structure, variability of threshold voltages and resistance states, temperature dependency, dynamic current fluctuations, etc. In this work we build upon such a physics-based model of a bipolar metal-oxide resistive RAM device, showing how to take into account device variability and its significance in evaluation of processing circuits. With the Cadence Virtuoso suite, we focus on a family of memristive logic gate implementations showing that read & write errors can emerge due to both variability and state-drift impact, features rarely seen so far in results shown in other relevant published works.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://hdl.handle.net/2117/130150",
    "openalex_id": "https://openalex.org/W2912011089",
    "relevance": "excluded",
    "review_screen": "unclear",
    "review_reason": "no strong cues",
    "llm_verdict": "not-knowm",
    "llm_confidence": "high",
    "pdf_knowm": "none",
    "knowm_role": null
  },
  {
    "cluster_id": "15218252624224155894",
    "title": "Modeling sinusoidally driven self-directed channel memristors",
    "authors": [
      "B Garda",
      "Z Galias"
    ],
    "first_author_last": "Garda",
    "year": 2018,
    "venue": "… on Signals and Electronic Systems (ICSES)",
    "link": "https://ieeexplore.ieee.org/abstract/document/8507323/",
    "doi": "10.1109/icses.2018.8507323",
    "cited_by": 6,
    "snippet": "In this work, the problem of memristors modeling is investigated. The elements under study are self-directed-channel memristors with a tungsten dopant fabricated by the Knowm Inc. …",
    "pdf_url": "https://www.researchgate.net/profile/Bartlomiej-Garda-2/publication/328520280_Modeling_Sinusoidally_Driven_Self-Directed_Channel_Memristors/links/5bdc5f59a6fdcc3a8db89d75/Modeling-Sinusoidally-Driven-Self-Directed-Channel-Memristors.pdf",
    "is_knowm": true,
    "is_sdc": true,
    "is_mss": false,
    "devices": [
      "W"
    ],
    "abstract": "In this work, the problem of memristors modeling is investigated. The elements under study are self-directed-channel memristors with a tungsten dopant fabricated by the Knowm Inc. Memristors are exited using a sinusoidal waveform. Three existing memristor models are considered: the Strukov model, the Biolek model, and the VTEAM model. Additionally, an asymmetric Strukov model is considered. Parameters of the models are fitted to experimental data using the interior-point optimization algorithm. Based on the results obtained comparison of models is carried out.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W2898317394",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "1465915736942641473",
    "title": "Modeling of Memristors Under Sinusoidal Excitations with Various Frequencies",
    "authors": [
      "B Garda",
      "Z Galias"
    ],
    "first_author_last": "Garda",
    "year": 2018,
    "venue": "25th IEEE International Conference on …",
    "link": "https://ieeexplore.ieee.org/abstract/document/8617926/",
    "doi": "10.1109/icecs.2018.8617926",
    "cited_by": 6,
    "snippet": "… Abstract—The problem of memristors modeling is investigated. The elements under study are self-directed-channel memristors with a tungsten dopant fabricated by the Knowm Inc. …",
    "pdf_url": "http://www.zet.agh.edu.pl/ncn2016memristors/presentations/icecs2018bgf.pdf",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [
      "W"
    ],
    "abstract": "The problem of memristors modeling is investigated. The elements under study are self-directed-channel memristors with a tungsten dopant fabricated by the Knowm Inc. Memristors are exited using a sinusoidal waveform. Three memristor models are considered: the asymmetric Strukov model, the Strukov model with the Biolek window, and the VTEAM model. Parameters of the models are fitted to experimental data using the interior-point optimization algorithm. The possibility of modeling memristor's behavior in a wide frequency range using the models considered is studied.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W2913333668",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "14086452346772605196",
    "title": "Resistive switching behavior seen from the energy point of view",
    "authors": [
      "J Gomez",
      "A Abusleme",
      "I Vourkas"
    ],
    "first_author_last": "Gomez",
    "year": 2018,
    "venue": "IEEE 24th …",
    "link": "https://ieeexplore.ieee.org/abstract/document/8474167/",
    "doi": "10.1109/iolts.2018.8474167",
    "cited_by": 2,
    "snippet": "… The BS-AF-W memristors developed by Knowm Inc are in a 16-pin DIP package. The PCB includes a MIC 7122YMM opamp for its wide Vsup range support, and a feedback resistor R,. …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": true,
    "devices": [],
    "abstract": "The technology of Resistive Switching (RS) devices (memristors) is continuously maturing on its way towards viable commercial establishment. So far, the change of resistance has been identified as a function of the applied pulse characteristics, such as amplitude and duration. However, parameter variability holds back any universal approach based on these two magnitudes, making also difficult even the qualitative comparison between different RS material compounds. On the contrary, there is a relevant magnitude which is much less affected by device variability; the energy. In this direction, we doubt anyone so far has ever wondered “what is the quantitative effect of the injected energy on the device state?” Interestingly, a first step was made recently towards the definition of performance parameters for this emerging device technology, using as fundamental parameter the energy. In this work, we further elaborate on such ideas, proving experimentally that the “resistance change per energy unit” $( dR/ dE )$ can be considered a significant magnitude in analog operation of bipolar memristors, being a key performance parameter worth of timely disclosure.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://hdl.handle.net/2117/130084",
    "openalex_id": "https://openalex.org/W2896336424",
    "relevance": "excluded",
    "review_screen": "unclear",
    "review_reason": "weak use cues: experimental, experiment",
    "llm_verdict": "not-knowm",
    "llm_confidence": "medium",
    "pdf_knowm": null,
    "knowm_role": null
  },
  {
    "cluster_id": "975554548377154180",
    "title": "Experimental measurements on resistive switching devices: Gaining hands-on experience",
    "authors": [
      "J Gomez",
      "A Abusleme",
      "I Vourkas"
    ],
    "first_author_last": "Gomez",
    "year": 2018,
    "venue": "7th International …",
    "link": "https://ieeexplore.ieee.org/abstract/document/8376607/",
    "doi": "10.1109/mocast.2018.8376607",
    "cited_by": 5,
    "snippet": "… The BS-AF-W memristors developed by Knowm Inc are in a 16-pin DIP package. In such bipolar devices, the material stack is based on mobile metal ion conduction through a layer of …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": true,
    "devices": [],
    "abstract": "The maximum exploitation of the favorable properties and the analog nature of memristor technology in innovative applications can be guaranteed only by the deeper understanding of their behavior. Fully functional memristors are commercially available. However, lab experiments with memristors are a challenging step. In this direction, this paper presents some important considerations to carry out reliable measurements. Most importantly, the proposed experimental setup is composed of off-the-shelf components and an affordable data acquisition system, showing the way on how to bypass the need for expensive research equipment and expand memristor experimentation beyond research labs and into classrooms.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W2808048868",
    "relevance": "excluded",
    "review_screen": "likely-use",
    "review_reason": "use cues: off-the-shelf, commercially available, measurement, experimental",
    "llm_verdict": "uncertain",
    "llm_confidence": "low",
    "human_verdict": "not-knowm",
    "human_reason": "NO (user)",
    "pdf_knowm": null,
    "knowm_role": null
  },
  {
    "cluster_id": "13951345475943014789",
    "title": "Impact of integrated circuit packaging on synaptic dynamics of memristive devices",
    "authors": [
      "A Irmanova",
      "GA Ellis",
      "AP James"
    ],
    "first_author_last": "Irmanova",
    "year": 2018,
    "venue": "Nazarbayev University Repository (Nazarbayev University)",
    "link": "https://ieeexplore.ieee.org/abstract/document/8680861/",
    "doi": "10.1109/edaps.2018.8680861",
    "cited_by": 1,
    "snippet": "… of memristors in Quad Flat Pack. A comparison is drawn between the memristors with and … For the simulation of packaged memristors the Knowm model [9] was used. In this model the …",
    "pdf_url": "https://arxiv.org/pdf/1809.10434",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "The memristor can be used as non volatile memory (NVM) and for emulating neuron behavior. It has the ability to switch between low resistance R on and high resistance values R off, and exhibit the synaptic dynamic behaviour such as potentiation and depression. This paper presents a study on potentiation and depression of memristors in Quad Flat Pack. A comparison is drawn between the memristors with and without the impact of parasitics of packaging, using measured data and equivalent circuit models. The parameters in memristor and packaging models for the SPICE simulations were determined using measured data to reflect the memristor parasitics in Quad Flat Packs.",
    "abstract_source": "openalex",
    "oa_pdf_url": "http://nur.nu.edu.kz/handle/123456789/4259",
    "openalex_id": "https://openalex.org/W2963605396",
    "relevance": "cites",
    "review_screen": "likely-cite-only",
    "review_reason": "cite/other-device cues: spice, simulation",
    "pdf_knowm": "cites",
    "knowm_role": "cites"
  },
  {
    "cluster_id": "3639553593446673025",
    "title": "Investigation of the memristor nonlinear properties",
    "authors": [
      "S Khrapko",
      "V Rusyn",
      "L Politansky"
    ],
    "first_author_last": "Khrapko",
    "year": 2018,
    "venue": "Informatyka Automatyka Pomiary w Gospodarce i Ochronie Środowiska",
    "link": "https://bibliotekanauki.pl/articles/408547.pdf",
    "doi": "10.5604/01.3001.0010.8544",
    "cited_by": 3,
    "snippet": "… of the memristor In this study, we use the memristor company KNOWM of series BS-AF-W 16DIP… The topological structure of the used memristor is described in detail in [13]. The …",
    "pdf_url": "https://bibliotekanauki.pl/articles/408547.pdf",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": true,
    "devices": [
      "W"
    ],
    "abstract": "The study of nonlinear systems is an important research topic for scientists and researchers. Memristor, for a long time, it remained just as a theoretical element and rarely appeared in the literature because of having no simple and practical realization. In this paper, we reviewed the theoretical substantiation of the memristor and conducted a practical study of its nonlinear properties using the memristor company KNOWM of series BS-AF-W 16DIP. We also investigated the characteristics of the memristor via the LabView environment.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://doi.org/10.5604/01.3001.0010.8544",
    "openalex_id": "https://openalex.org/W2793731106",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "13054611359129182445",
    "title": "BADANIE NIELINIOWYCH WŁAŚCIWOŚCI MEMRYSTORA",
    "authors": [
      "S Khrapko",
      "V Rusyn",
      "L Politansky"
    ],
    "first_author_last": "Khrapko",
    "year": 2018,
    "venue": "Informatyka, Automatyka, Pomiary w …",
    "link": "https://ph.pollub.pl/index.php/iapgos/article/view/1032",
    "doi": null,
    "cited_by": 0,
    "snippet": "… of the memristor In this study, we use the memristor company KNOWM of series BS-AF-W 16DIP… The topological structure of the used memristor is described in detail in [13]. The …",
    "pdf_url": "https://ph.pollub.pl/index.php/iapgos/article/download/1032/802",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": true,
    "devices": [],
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": null,
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "DNSUIt8vqioJ",
    "title": "Memristors: Where fantasy meets fact (Conference Presentation)",
    "authors": [
      "A Nugent"
    ],
    "first_author_last": "Nugent",
    "year": 2018,
    "venue": "Disruptive Technologies in Information Sciences",
    "link": "https://www.spiedigitallibrary.org/conference-proceedings-of-spie/10652/106520L/Memristors-Where-fantasy-meets-fact-Conference-Presentation/10.1117/12.2306993.short",
    "doi": "10.1117/12.2306993.short",
    "cited_by": 0,
    "snippet": "… technology we will discuss some of the more disruptive memristor applications with a focus on … of the Knowm Inc memristor technology stack and a live demonstration of memristors. …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "Theorized since the 1970’s and brought to public awareness through HP’s tumultuous marketing efforts starting in 2008, the memristor has promised radical disruptions in computing technology. Like almost all new and disruptive technologies, promises failed to materialize as the gap between theory and reality stubbornly refused to come together. Rather than fading into obscurity, interest in the memristor has continued its exponential rise. While it is only natural for one to use a new tool in the same manner as an old familiar one, we argue that the future success of the memristor lies in understanding what makes it unique and in firmly understanding where theoretical idealizations deviate from hard reality. After a brief history of memristor technology we will discuss some of the more disruptive memristor applications with a focus on synaptic processors. We will conclude with a review of the Knowm Inc memristor technology stack and a live demonstration of memristors.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W2804051948",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "named-in-abstract"
  },
  {
    "cluster_id": "3606512940856416475",
    "title": "Thermodynamic-RAM technology stack",
    "authors": [
      "MA Nugent",
      "TW Molter"
    ],
    "first_author_last": "Nugent",
    "year": 2017,
    "venue": "International Journal of Parallel Emergent and Distributed Systems",
    "link": "https://www.tandfonline.com/doi/abs/10.1080/17445760.2017.1314472",
    "doi": "10.1080/17445760.2017.1314472",
    "cited_by": 24,
    "snippet": "… computation, kT-RAM will provide a … kT-RAM becomes a much easier task. The levels of the Thermodynamic-RAM technology stack include the memristor, synapse, AHaH node, kT-RAM…",
    "pdf_url": "https://arxiv.org/pdf/1406.5633",
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": true,
    "devices": [],
    "abstract": "We introduce a technology stack or specification describing the multiple levels of abstraction and specialisation needed to implement a neuromorphic processor (NPU) based on the previously-described concept of AHaH Computing and integrate it into today’s digital computing systems. The general purpose NPU implementation described here is called Thermodynamic-RAM (kT-RAM) and is just one of many possible architectures, each with varying advantages and trade offs. Bringing us closer to brain-like neural computation, kT-RAM will provide a general-purpose adaptive hardware resource to existing computing platforms enabling fast and low-power machine learning capabilities that are currently hampered by the separation of memory and processing, a.k.a the von Neumann bottleneck. Because understanding such a processor based on non-traditional principles can be difficult, by presenting the various levels of the stack from the bottom up, layer by layer, explaining kT-RAM becomes a much easier task. The levels of the Thermodynamic-RAM technology stack include the memristor, synapse, AHaH node, kT-RAM, instruction set, sparse spike encoding, kT-RAM emulator, and SENSE server.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://arxiv.org/pdf/1406.5633",
    "openalex_id": "https://openalex.org/W280546096",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "13658299471382240821",
    "title": "Memristor: Modeling and research of information properties",
    "authors": [
      "V Rusyn",
      "S Khrapko"
    ],
    "first_author_last": "Rusyn",
    "year": 2019,
    "venue": "Springer proceedings in complexity",
    "link": "https://link.springer.com/chapter/10.1007/978-3-030-15297-0_21",
    "doi": "10.1007/978-3-030-15297-0_21",
    "cited_by": 10,
    "snippet": "… of memristor based on Chua’s scheme. The circuit of connection of the memristor to obtain I–… In our study, we used the KNOWM memristor BS-AF-W 16DIP series based on the tungsten …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": true,
    "devices": [],
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W2947535369",
    "relevance": "excluded",
    "review_screen": "no-abstract",
    "review_reason": "no abstract — manual check",
    "pdf_knowm": null,
    "knowm_role": null,
    "human_verdict": "not-knowm",
    "human_reason": "NO (user)"
  },
  {
    "cluster_id": "5024387494430798743",
    "title": "Self-calibration of multiscale hysteresis with memristors in nonlinear time reversal based processes",
    "authors": [
      "S Dos Santos",
      "A Masood",
      "S Furui"
    ],
    "first_author_last": "Santos",
    "year": 2018,
    "venue": "16th Biennial …",
    "link": "https://ieeexplore.ieee.org/abstract/document/8600977/",
    "doi": "10.1109/bec.2018.8600977",
    "cited_by": 10,
    "snippet": "… of 16 BS-AF-W tiers 1,2 and 3 commercialized memristors (Knowm Inc, Santa Fe, USA, https://knowm.org/memristors/ )… The simplicity of the proposed coupling between memristors and …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": true,
    "devices": [],
    "abstract": "A calibration process of a nonlinear time reversal based ultrasonic device which is associated to the development of a phenomenological characterization of material local elastic properties is proposed. The experimental device is improved and specially scaled in order to access to a wide range of parameters: mechanical properties, ultrasonic parameters (celerity and attenuation) and local geometric data. The experimental set-up is completed by using modern ultrasonic memosducer components aim at describing memristive properties of damaged media.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W2909762373",
    "relevance": "excluded",
    "review_screen": "likely-use",
    "review_reason": "use cues: experimental, experiment, characteriz",
    "llm_verdict": "not-knowm",
    "llm_confidence": "medium",
    "pdf_knowm": null,
    "knowm_role": null
  },
  {
    "cluster_id": "12582900725756473695",
    "title": "Perspective: A review on memristive hardware for neuromorphic computation",
    "authors": [
      "C Sung",
      "H Hwang",
      "IK Yoo"
    ],
    "first_author_last": "Sung",
    "year": 2018,
    "venue": "Journal of Applied Physics",
    "link": "https://pubs.aip.org/aip/jap/article/124/15/151903/347883",
    "doi": "10.1063/1.5037835",
    "cited_by": 216,
    "snippet": "… of memristor-based neuromorphic computation was analyzed on the basis of papers and patents to identify the competitiveness of the memristor … knowm ® has also released a classifier …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "Neuromorphic computation is one of the axes of parallel distributed processing, and memristor-based synaptic weight is considered as a key component of this type of computation. However, the material properties of memristors, including material related physics, are not yet matured. In parallel with memristors, CMOS based Graphics Processing Unit, Field Programmable Gate Array, and Application Specific Integrated Circuit are also being developed as dedicated artificial intelligence (AI) chips for fast computation. Therefore, it is necessary to analyze the competitiveness of the memristor-based neuromorphic device in order to position the memristor in the appropriate position of the future AI ecosystem. In this article, the status of memristor-based neuromorphic computation was analyzed on the basis of papers and patents to identify the competitiveness of the memristor properties by reviewing industrial trends and academic pursuits. In addition, material issues and challenges are discussed for implementing the memristor-based neural processor.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://aip.scitation.org/doi/pdf/10.1063/1.5037835",
    "openalex_id": "https://openalex.org/W2895545069",
    "relevance": "cites",
    "review_screen": "unclear",
    "review_reason": "no strong cues",
    "llm_verdict": "cites-only",
    "llm_confidence": "high",
    "pdf_knowm": "uses-model",
    "knowm_role": "cites",
    "human_verdict": "cites-only",
    "human_reason": "CITE (user): reviewed PDF — cites Knowm's AHaH classifier product (ref 82, knowm.org/ahah-computing); no device or MSS-model use"
  },
  {
    "cluster_id": "5149562119241802639",
    "title": "Special issue on 'Advances in Memristive Networks'",
    "authors": [
      "I Vourkas",
      "GC Sirakoulis"
    ],
    "first_author_last": "Vourkas",
    "year": 2018,
    "venue": "International Journal of Parallel Emergent and Distributed Systems",
    "link": "https://www.tandfonline.com/doi/full/10.1080/17445760.2018.1450874",
    "doi": "10.1080/17445760.2018.1450874",
    "cited_by": 0,
    "snippet": "… However, nowadays the term memristor may refer to any resistive switching device that … recently by Knowm Inc. [Citation5], who provided affordable access to memristors, bringing this …",
    "pdf_url": "https://www.tandfonline.com/doi/pdf/10.1080/17445760.2018.1450874",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "The existence of the fourth fundamental circuit element, the ‘memristor’, was postulated by Chua in 1971 [1]. Chua mathematically explored the properties of this new nonlinear circuit element and f...",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://www.tandfonline.com/doi/pdf/10.1080/17445760.2018.1450874?download=true",
    "openalex_id": "https://openalex.org/W2811404205",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "llm_verdict": "cites-only",
    "llm_confidence": "high",
    "pdf_knowm": "uses-model",
    "knowm_role": "uses-model"
  },
  {
    "cluster_id": "17234137771124957834",
    "title": "Bioinspired Computing with Synaptic Elements",
    "authors": [
      "G Wendin"
    ],
    "first_author_last": "Wendin",
    "year": 2018,
    "venue": "Natural computing series",
    "link": "https://link.springer.com/chapter/10.1007/978-3-319-65826-1_5",
    "doi": "10.1007/978-3-319-65826-1_5",
    "cited_by": 1,
    "snippet": "… , with emphasis on synaptic networks based on various kinds of memristors. … kT-RAM) (Molter and Nugent, 2016) is a neuromemristive co-processor design based on the theory of AHaH …",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": true,
    "devices": [],
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W2884725192",
    "relevance": "excluded",
    "review_screen": "no-abstract",
    "review_reason": "no abstract — manual check",
    "pdf_knowm": null,
    "knowm_role": null,
    "human_verdict": "not-knowm",
    "human_reason": "NO (user)"
  },
  {
    "cluster_id": "10585731469854948274",
    "title": "Deep-DFR: A memristive deep delayed feedback reservoir computing system with hybrid neural network topology",
    "authors": [
      "K Bai",
      "Q An",
      "Y Yi"
    ],
    "first_author_last": "Bai",
    "year": 2019,
    "venue": "Proceedings of the 56th annual design automation …",
    "link": "https://dl.acm.org/doi/abs/10.1145/3316781.3317796",
    "doi": "10.1145/3316781.3317796",
    "cited_by": 13,
    "snippet": "… The output weight matrix was deployed by the discrete memristor device (BS-AF-W) [17] from the Knowm Inc., replicating the synaptic behavior in the neurological system. …",
    "pdf_url": "https://dl.acm.org/doi/pdf/10.1145/3316781.3317796",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": true,
    "devices": [],
    "abstract": "Deep neural networks (DNNs), the brain-like machine learning architecture, have gained immense success in data-extensive applications. In this work, a hybrid structured deep delayed feedback reservoir (Deep-DFR) computing model is proposed and fabricated. Our Deep-DFR employs memristive synapses working in a hierarchical information processing fashion with DFR modules as the readout layer, leading our proposed deep learning structure to be both depth-in-space and depth-in-time. Our fabricated prototype along with experimental results demonstrate its high energy efficiency with low hardware implementation cost. With applications on the image classification, MNIST and SVHN, our Deep-DFR yields a 1.26~7.69X reduction on the testing error compared to state-of-the-art DNN designs.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W2946347869",
    "relevance": "excluded",
    "review_screen": "unclear",
    "review_reason": "weak use cues: experimental, experiment",
    "llm_verdict": "not-knowm",
    "llm_confidence": "medium",
    "pdf_knowm": null,
    "knowm_role": null
  },
  {
    "cluster_id": "10782609128073508990",
    "title": "A training-efficient hybrid-structured deep neural network with reconfigurable memristive synapses",
    "authors": [
      "K Bai",
      "Q An",
      "L Liu",
      "Y Yi"
    ],
    "first_author_last": "Bai",
    "year": 2019,
    "venue": "IEEE Transactions on Very Large Scale Integration (VLSI) Systems",
    "link": "https://ieeexplore.ieee.org/abstract/document/8866734/",
    "doi": "10.1109/tvlsi.2019.2942267",
    "cited_by": 38,
    "snippet": "… This particular conductance state is allocated within the range of measured conductance states through the discrete memristor device (BS-AF-W) [39] from the Knowm Inc. [40], which is …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": true,
    "devices": [],
    "abstract": "The continued success in the development of neuromorphic computing has immensely pushed today's artificial intelligence forward. Deep neural networks (DNNs), a brainlike machine learning architecture, rely on the intensive vector-matrix computation with extraordinary performance in data-extensive applications. Recently, the nonvolatile memory (NVM) crossbar array uniquely has unvailed its intrinsic vector-matrix computation with parallel computing capability in neural network designs. In this article, we design and fabricate a hybrid-structured DNN (hybrid-DNN), combining both depth-in-space (spatial) and depth-in-time (temporal) deep learning characteristics. Our hybrid-DNN employs memristive synapses working in a hierarchical information processing fashion and delay-based spiking neural network (SNN) modules as the readout layer. Our fabricated prototype in 130-nm CMOS technology along with experimental results demonstrates its high computing parallelism and energy efficiency with low hardware implementation cost, making the designed system a candidate for low-power embedded applications. From chaotic time-series forecasting benchmarks, our hybrid-DNN exhibits 1.16×-13.77× reduction on the prediction error compared to the state-of-the-art DNN designs. Moreover, our hybrid-DNN records 99.03% and 99.63% testing accuracy on the handwritten digit classification and the spoken digit recognition tasks, respectively.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W2979610412",
    "relevance": "excluded",
    "review_screen": "unclear",
    "review_reason": "weak use cues: experimental, experiment",
    "llm_verdict": "not-knowm",
    "llm_confidence": "high",
    "pdf_knowm": null,
    "knowm_role": null
  },
  {
    "cluster_id": "8992218204011938206",
    "title": "The self-directed channel memristor: operational dependence on the metal-chalcogenide layer",
    "authors": [
      "KA Campbell"
    ],
    "first_author_last": "Campbell",
    "year": 2019,
    "venue": "Handbook of Memristor Networks",
    "link": "https://link.springer.com/chapter/10.1007/978-3-319-76375-0_29",
    "doi": "10.1007/978-3-319-76375-0_29",
    "cited_by": 11,
    "snippet": "… The basic self-directed channel memristor is comprised of five layers of Ge 2 Se 3 , SnSe, and an oxidizable metal, Ag. Each layer plays a role in the operation of the memristor, …",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": true,
    "is_mss": false,
    "devices": [],
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W2983464142",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "named-in-abstract"
  },
  {
    "cluster_id": "11621156976198608696",
    "title": "Desenho lógico com Memristors",
    "authors": [
      "JV Correia"
    ],
    "first_author_last": "Correia",
    "year": 2019,
    "venue": "",
    "link": "https://search.proquest.com/openview/6b23630ed5a0c0400cb3741b3cd1e634/1?pq-origsite=gscholar&cbl=2026366&diss=y",
    "doi": null,
    "cited_by": 0,
    "snippet": "… The test setup is depicted in Fig.2.24, where the memristor used was the BS-AF-W from Knowm. The measurements were made using a PicoScope 2208B, with the AWG channel as the …",
    "pdf_url": "https://repositorio.ulisboa.pt/bitstream/10451/41640/1/ulfpie053583_tm.pdf",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": true,
    "devices": [],
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": null,
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "uses-knowm-model",
    "human_verdict": "uses-knowm-model",
    "human_reason": "YES (user): uses the Knowm memristor model (I–V curves)"
  },
  {
    "cluster_id": "9885249981547819430",
    "title": "Comparison of the electrical response of Cu and Ag ion-conducting SDC memristors over the temperature range 6 K to 300 K",
    "authors": [
      "K Drake",
      "T Lu",
      "MKH Majumdar",
      "KA Campbell"
    ],
    "first_author_last": "Drake",
    "year": 2019,
    "venue": "Micromachines",
    "link": "https://www.mdpi.com/2072-666X/10/10/663",
    "doi": "10.3390/mi10100663",
    "cited_by": 15,
    "snippet": "… Electrical performance of self-directed channel (SDC) ion-conducting memristors which use … SDC memristors operate at temperatures as low as 6 K, whereas Ag-based SDC memristors …",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": true,
    "is_mss": false,
    "devices": [],
    "abstract": "Electrical performance of self-directed channel (SDC) ion-conducting memristors which use Ag and Cu as the mobile ion source are compared over the temperature range of 6 K to 300 K. The Cu-based SDC memristors operate at temperatures as low as 6 K, whereas Ag-based SDC memristors are damaged if operated below 125 K. It is also observed that Cu reversibly diffuses into the active Ge2Se3 layer during normal device shelf-life, thus changing the state of a Cu-based memristor over time. This was not observed for the Ag-based SDC devices. The response of each device type to sinusoidal excitation is provided and shows that the Cu-based devices exhibit hysteresis lobe collapse at lower frequencies than the Ag-based devices. In addition, the pulsed response of the device types is presented.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://www.mdpi.com/2072-666X/10/10/663/pdf?version=1569841236",
    "openalex_id": "https://openalex.org/W2975321185",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "11912088943985247297",
    "title": "Analog weights in ReRAM DNN accelerators",
    "authors": [
      "JK Eshraghian",
      "SM Kang",
      "S Baek"
    ],
    "first_author_last": "Eshraghian",
    "year": 2019,
    "venue": "… Circuits and Systems …",
    "link": "https://ieeexplore.ieee.org/abstract/document/8771550/",
    "doi": "10.1109/aicas.2019.8771550",
    "cited_by": 36,
    "snippet": "… memristor conductance, we show it is possible to map a continuous range of weights that are assignable to memristors… 4(a) as input with GeSeSn-W memristors purchased from Knowm. …",
    "pdf_url": "https://arxiv.org/pdf/1904.12008",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "Artificial neural networks have become ubiquitous in modern life, which has triggered the emergence of a new class of application specific integrated circuits for their acceleration. ReRAM-based accelerators have gained significant traction due to their ability to leverage in-memory computations. In a crossbar structure, they can perform multiply-and-accumulate operations more efficiently than standard CMOS logic. By virtue of being resistive switches, ReRAM switches can only reliably store one of two states. This is a severe limitation on the range of values in a computational kernel. This paper presents a novel scheme in alleviating the single-bit-per-device restriction by exploiting frequency dependence of v-i plane hysteresis, and assigning kernel information not only to the device conductance but also partially distributing it to the frequency of a time-varying input.We show this approach reduces average power consumption for a single crossbar convolution by up to a factor of ×16 for an unsigned 8-bit input image, where each convolutional process consumes a worst-case of 1.1mW, and reduces area by a factor of ×8, without reducing accuracy to the level of binarized neural networks. This presents a massive saving in computing cost when there are many simultaneous in-situ multiply-and-accumulate processes occurring across different crossbars.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://arxiv.org/pdf/1904.12008",
    "openalex_id": "https://openalex.org/W2942061430",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "llm_verdict": "not-knowm",
    "llm_confidence": "high",
    "pdf_knowm": "uses-model",
    "knowm_role": "uses-model"
  },
  {
    "cluster_id": "18089067132048427071",
    "title": "Voltage divider for self-limited analog state programing of memristors",
    "authors": [
      "J Gomez",
      "I Vourkas",
      "A Abusleme"
    ],
    "first_author_last": "Gomez",
    "year": 2019,
    "venue": "… on Circuits and …",
    "link": "https://ieeexplore.ieee.org/abstract/document/8740908/",
    "doi": null,
    "cited_by": 30,
    "snippet": "… The RS devices used were BS-AF-W discrete self-directed-channel bipolar memristors with … M + Ge2Se3 (M = Cu or Sn) for accessing and continuously programming a memristor,” …",
    "pdf_url": "http://confcats-event-sessions.s3.amazonaws.com/iscas20/slides/1587.pdf",
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": true,
    "devices": [],
    "abstract": "Resistive switching devices—memristors—present a tunable, incremental switching behavior. Tuning their state accurately, repeatedly and in a wide range, makes memristors well-suited for multi-level (ML) resistive memory cells and analog computing applications. In this brief, the tuning approach based on a memristor-resistor voltage divider (VD) is validated experimentally using commercial memristors from <italic xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\">Knowm Inc</i>. and a custom circuit. Rapid and controllable multi-state SET tuning is shown with an appreciable range of different resistance values obtained as a function of the amplitude of the applied voltage pulse. The efficiency of the VD is finally compared against an adaptive pulse-based tuning protocol, in terms of circuit overhead, tuning precision, tuning time, and energy consumption, qualifying as a simple hardware solution for fast, reliable, and energy-efficient ML resistance tuning.",
    "abstract_source": "ieee-xplore",
    "oa_pdf_url": null,
    "openalex_id": null,
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "5076904003119880402",
    "title": "Exploring memristor multi-level tuning dependencies on the applied pulse properties via a low cost instrumentation setup",
    "authors": [
      "J Gomez",
      "I Vourkas",
      "A Abusleme"
    ],
    "first_author_last": "Gomez",
    "year": 2019,
    "venue": "IEEE Access",
    "link": "https://ieeexplore.ieee.org/abstract/document/8708254/",
    "doi": "10.1109/access.2019.2915100",
    "cited_by": 34,
    "snippet": "… In all measurements, the memristors used were BS-AF-W discrete self-directed-channel bipolar devices [27], developed and commercialized in 16-pin ceramic DIP packages by Knowm …",
    "pdf_url": "https://ieeexplore.ieee.org/iel7/6287639/8600701/08708254.pdf",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": true,
    "devices": [],
    "abstract": "Deeper understanding of memristive behavior is the only safe way towards maximum exploitation of the favorable properties and the analog nature of this new device technology in innovative applications. This can be achieved through experimental hands-on experience with real devices. However, lab experiments with memristors are a challenging step, especially for the uninitiated. In this direction, this paper presents some important considerations to carry out reliable measurements using an experimental setup composed of <italic xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\">off-the-shelf</i> components and an affordable data acquisition system. We specifically show how a transimpedance amplifier can be used to protect the memristor from damage via current compliance limiting, and allow full control over the voltage drop on its terminals. Using the proposed setup, a set of key experiments were carried out on commercial memristors from <italic xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\">Knowm Inc.</i> , revealing fundamental dependencies of memristor state-tuning properties on the characteristics of the applied pulses and the initial conditions of the devices.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://ieeexplore.ieee.org/ielx7/6287639/8600701/08708254.pdf",
    "openalex_id": "https://openalex.org/W2944289649",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "7154975357328404610",
    "title": "Memristors for programmable circuits controlled by embedded systems",
    "authors": [
      "P Grothe",
      "J Haase"
    ],
    "first_author_last": "Grothe",
    "year": 2019,
    "venue": "Proceedings of the 22nd International Workshop on …",
    "link": "https://dl.acm.org/doi/abs/10.1145/3323439.3323985",
    "doi": "10.1145/3323439.3323985",
    "cited_by": 3,
    "snippet": "… As of spring 2019 physical memristors are only available through Knowm Inc. and have been so for a couple of years. The behavior of the memristor is caused by ion channels forming …",
    "pdf_url": "https://dl.acm.org/doi/pdf/10.1145/3323439.3323985",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "Many embedded systems reside within bigger electrical systems. While the embedded system takes control over many aspects of the surrounding systems, the amount of possible control is set by the given configuration. This causes a divide between the flexibility provided by software and the unchanging nature of the encompassing hardware. The concept of programmable circuits seeks to bridge this gap. The use of memristors enables the changing of resistor values within a circuit without disassembly. The continuous, non-volatile variable resistor provides the possibility to reconfigure hardware circuits through external influences or even by software on the embedded system at run time.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W2945515528",
    "relevance": "cites",
    "review_screen": "unclear",
    "review_reason": "no strong cues",
    "llm_verdict": "uncertain",
    "llm_confidence": "low",
    "pdf_knowm": "cites",
    "knowm_role": "cites"
  },
  {
    "cluster_id": "wiZZIkVlC6UJ",
    "title": "2019 36th National Radio Science Conference (NRSC)",
    "authors": [
      "SF Ibrahim"
    ],
    "first_author_last": "Ibrahim",
    "year": 2019,
    "venue": "",
    "link": "https://www.researchgate.net/profile/Sherief-Nafea/publication/333220732_Memristor_NRSC_2019/links/5ce2b7f1a6fdccc9ddbfd40b/Memristor-NRSC-2019.pdf",
    "doi": "10.1109/nrsc46828.2019",
    "cited_by": 4,
    "snippet": "… The Knowm Self Directed Channel (SDC) Memristor material stack is metal ionconducting device which relies on Ag+ (Silver ions) movement into channels within the active layer to …",
    "pdf_url": "https://www.researchgate.net/profile/Sherief-Nafea/publication/333220732_Memristor_NRSC_2019/links/5ce2b7f1a6fdccc9ddbfd40b/Memristor-NRSC-2019.pdf",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4286804464",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "uses-knowm-device",
    "human_verdict": "uses-knowm-device",
    "human_reason": "YES (user)"
  },
  {
    "cluster_id": "4348406546205440301",
    "title": "Knowm Self Directed Channel Memristors Data Sheet",
    "authors": [
      "Knowm Inc."
    ],
    "first_author_last": "Inc",
    "year": 2019,
    "venue": "",
    "link": "",
    "doi": null,
    "cited_by": 4,
    "snippet": "",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": null,
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "named-in-abstract"
  },
  {
    "cluster_id": "VwLLsws7likJ",
    "title": "Memristors: Properties, Models",
    "authors": [
      "O Krestinskaya",
      "A Irmanova"
    ],
    "first_author_last": "Krestinskaya",
    "year": 2025,
    "venue": "River Publishers eBooks",
    "link": "https://books.google.com/books?hl=en&lr=&id=yWWRDwAAQBAJ&oi=fnd&pg=PA13&dq=generalized+metastable+switch+memristor&ots=Uanfr4Dn5Q&sig=Dpkj0xA1Cu4WaWB4BaitIh9IX9Q",
    "doi": "10.1201/9788770047296-2",
    "cited_by": 0,
    "snippet": "… generalized memristor models and application of generalized window functions, memristor … Model WAM The generalized metastable switch memristor model 86. Molter TW, Nugent MA …",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": true,
    "devices": [],
    "abstract": "This chapter provides a comprehensive overview of the principles, fabrication techniques, types, applications, and the challenges and future prospects associated with the memristors. The introductory section of this chapter provides a foundational understanding of memristor devices. Subsections, which explore various memristor models, including the linear ion shift model, models based on window function, models for parameter fitting, memristor models for particular devices, etc., shed light on the diverse theoretical frameworks that develop these devices. Additionally, the chapter explains memristor fabrication techniques and discusses the scaling down process and recent advances in fabrication technology, highlighting the continuous evolution in the field. The sections also comprises diverse types of memristors, detailing their unique properties and applications. The types include resistive memristors, polymeric memristors, ferroelectric memristors, resonant-tunneling diodes (RTDs), and spintronic memristors, each providing distinct advantages and use cases. This section serves as a valuable resource for readers seeking a wide understanding of the expanding area of memristor technologies. The subsequent sections focus on the practical applications of memristor-based devices. Non-volatile memory applications are explored, emphasizing the potential of memristors in developing data storage. The discussion extends to crossbar arrays and memory density, elucidating how memristor technology contributes to increased storage capacity. Furthermore, the chapter explores the implications of memristors in enhancing the speed and energy efficiency of memory storage systems, addressing crucial aspects of contemporary technological demands. The final section critically examines the challenges faced by memristor technology and outlines potential future directions. The authors discuss the future scope of memristor technology, focusing on its potential impact on various fields and industries. Overall, the chapter offers a thorough exploration of the foundational principles, diverse types, practical applications, and future trajectories of memristor technology.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4414850018",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "human_verdict": "uses-knowm-model",
    "human_reason": "YES: uses the MSS model",
    "pdf_knowm": null,
    "knowm_role": "uses-knowm-model"
  },
  {
    "cluster_id": "15858730838830951036",
    "title": "Design and analysis of new meminductor model based on Knowm memristor",
    "authors": [
      "Z Lei-Jie",
      "W Fa-Qiang"
    ],
    "first_author_last": "Lei-Jie",
    "year": 2019,
    "venue": "Acta Physica Sinica",
    "link": "",
    "doi": "10.7498/aps.68.20190793",
    "cited_by": 6,
    "snippet": "",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "In the past, the memristor model and its application research have mainly focused on constructing and analyzing the memristor model and its equivalent circuit model based on the basic concept of memristor, while the research based on commercial memristive devices in the market has been rare. According to the theoretical relationship between meminductor and memristor, a new model of meminductor is constructed based on Knowm memristor, the first commercial memristor chip in the world, combined with the second-generation current conveyor and transconductance operational amplifier. By adjusting the frequency and the amplitude of the input voltage and the transconductance gain of the transconductance operational amplifier, the continuous adjustment of the meminductance can be effectively achieved in the circuit. The LTspice circuit model and hardware experimental circuit of the proposed meminductor are designed. The validity of the new meminductor model and the correctness of the design method are verified by LTspice simulations and circuit experiments.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://doi.org/10.7498/aps.68.20190793",
    "openalex_id": "https://openalex.org/W3085398072",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "named-in-abstract"
  },
  {
    "cluster_id": "pm75XsTrjVQJ",
    "title": "Investigation of the Conduction Mechanisms in the Ag-and Cu-Based Self-Directed Channel (SDC) Memristor",
    "authors": [
      "T Lu"
    ],
    "first_author_last": "Lu",
    "year": 2019,
    "venue": "",
    "link": "https://scholarworks.boisestate.edu/under_conf_2019/100/",
    "doi": null,
    "cited_by": 0,
    "snippet": "… Memristors are currently actively researched as a potential … proposed that the self-directed channel (SDC) memristor is a type … , non-conductive channel that bridges the active layer. This …",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": true,
    "is_mss": false,
    "devices": [],
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": null,
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "named-in-abstract"
  },
  {
    "cluster_id": "8269004657102462781",
    "title": "On the mechanism of creating pinched hysteresis loops using a commercial memristor device",
    "authors": [
      "S Majzoub",
      "AS Elwakil",
      "C Psychalinos"
    ],
    "first_author_last": "Majzoub",
    "year": 2019,
    "venue": "AEU - International Journal of Electronics and Communications",
    "link": "https://www.sciencedirect.com/science/article/pii/S1434841119316310",
    "doi": "10.1016/j.aeue.2019.152923",
    "cited_by": 26,
    "snippet": "… A commercial BS-AF-W memristor chip (see inset of Fig. 1) from KNOWM was used in the setup recommended by the manufacturer where a 50 k Ω resistance is connected in series with …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": true,
    "devices": [],
    "abstract": "Abstract In this short communication we analyze the impact of signal harmonics on the formation of the pinched hysteresis loop using a commercial memristor device. We show that by using only the fundamental frequency and the second harmonic components, extracted from the measured electrical current signal, a distortion-less pinched hysteresis loop is re-created. This loop is then used to simulate memristor-based AND/OR gates without any loss in digital functionality. This verifies that the generation of a pinched hysteresis loop requires a nonlinear frequency doubling mechanism to create a second harmonic in the current signal from an applied single frequency voltage excitation. Obtaining a pinched loop with three pinch points from the experimentally measured data is also demonstrated.",
    "abstract_source": "semanticscholar",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W2973695263",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-knowm-device",
    "human_verdict": "uses-knowm-device",
    "human_reason": "YES (user)"
  },
  {
    "cluster_id": "10226837468146028665",
    "title": "Jedno rješenje automatizacije programiranja KnowM memristora",
    "authors": [
      "I Marković",
      "M Potrebić",
      "D Tošić"
    ],
    "first_author_last": "Marković",
    "year": 2019,
    "venue": "18th International Symposium …",
    "link": "https://infoteh.etf.ues.rs.ba/zbornik/2019/radovi/ELS/ELS-5.pdf",
    "doi": null,
    "cited_by": 1,
    "snippet": "… hardware required for automatisation of programming of KnowM’s memristors. For that purpose, … voltage levels that should be applied on memristor, and measures memristor responses. …",
    "pdf_url": "https://infoteh.etf.ues.rs.ba/zbornik/2019/radovi/ELS/ELS-5.pdf",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": null,
    "relevance": "cites",
    "review_screen": "no-abstract",
    "review_reason": "no abstract — manual check",
    "pdf_knowm": "cites",
    "knowm_role": "cites"
  },
  {
    "cluster_id": "1sg-A8w85QsJ",
    "title": "Binary-Weighted Synaptic Circuit for Neuromorphic Learning System Using Stochastic Memristor SPICE Model",
    "authors": [
      "M Nigus",
      "R Priyadarshini"
    ],
    "first_author_last": "Nigus",
    "year": 2019,
    "venue": "… Conference on Computing …",
    "link": "https://ieeexplore.ieee.org/abstract/document/8974525/",
    "doi": "10.1109/icccis48478.2019.8974525",
    "cited_by": 0,
    "snippet": "… memristor-based neuromorphic learning system application. In this paper, a stochastic metastable switch memristor … empirical memristor model called the generalized metastable switch …",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": true,
    "devices": [],
    "abstract": "The memristive device is a nanoscale nonlinear passive two-terminal fourth fundamental circuit element in addition to the three previously known passive fundamental circuit elements namely resistor, capacitor, and inductor. However aside from its non-volatile memory nature, this memristor resistance/ memristance controlled in the circuit operation by the amount of charge applied between its terminals. The memristor device SPICE modeling is significant for memristive circuit and neuromorphic system design. Nowadays probabilistic switching behavior observed in many fabricated memristor devices that inspired stochastic learning rule for memristor-based neuromorphic learning system application. In this paper, a stochastic metastable switch memristor model (MSSs) is used for binary-weighted memristor-based artificial synapse circuitry presentation. Using this MSSs memristor SPICE model a binary-weighted memristor-based artificial synapse circuit presented. The presented circuit shows a binary response to the signal given to the memristor implemented in the binary synaptic circuit using a stochastic memristor device model. The authors left the implementation of the proposed binary synaptic circuit in a memristor-based artificial neural network that functions through the clipped perceptron (CP) learning algorithm as future work.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W3003770641",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "8923820935176949004",
    "title": "Experimental investigation of memristance enhancement",
    "authors": [
      "V Ntinas",
      "A Rubio",
      "GC Sirakoulis"
    ],
    "first_author_last": "Ntinas",
    "year": 2019,
    "venue": "IEEE/ACM …",
    "link": "https://ieeexplore.ieee.org/abstract/document/9073637/",
    "doi": "10.1109/nanoarch47378.2019.181299",
    "cited_by": 6,
    "snippet": "… of memristors in memory or logic applications, thus, this work presents the enhancement of this ratio on actual memristor devices, namely Knowm memristors, … phenomenon known as …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "Memristor devices are two-terminal nanoscale circuit elements that exhibit nonvolatile information storing and can be manufactured in ultra-dense arrays with low-power operation. Although, theoretically, memristors are strong candidates for novel memory and computing applications, the fabricated devices show high variability, both device-to-device and cycle-to-cycle, such as varying switching behaviour and maximum (R <sub xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\">MAX</sub> ) and minimum (R <sub xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\">MIN</sub> ) resistance values. Those limitations in the device's R <sub xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\">MAX</sub> /R <sub xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\">MIN</sub> ratio suppress the wide use of memristors in memory or logic applications, thus, this work presents the enhancement of this ratio on actual memristor devices, namely Knowm memristors, due to the introduction of external noise as a beneficial disturbance, following the nonlinear system phenomenon known as Stochastic Resonance.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W3022852236",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "named-in-abstract"
  },
  {
    "cluster_id": "4729704974881115316",
    "title": "Self Directed Channel Memristors",
    "authors": [
      "A Nugent"
    ],
    "first_author_last": "Nugent",
    "year": 2018,
    "venue": "Knowm Inc",
    "link": "",
    "doi": "10.1109/icses.2018.8507323",
    "cited_by": 6,
    "snippet": "",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [
      "W"
    ],
    "abstract": "In this work, the problem of memristors modeling is investigated. The elements under study are self-directed-channel memristors with a tungsten dopant fabricated by the Knowm Inc. Memristors are exited using a sinusoidal waveform. Three existing memristor models are considered: the Strukov model, the Biolek model, and the VTEAM model. Additionally, an asymmetric Strukov model is considered. Parameters of the models are fitted to experimental data using the interior-point optimization algorithm. Based on the results obtained comparison of models is carried out.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W2898317394",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "named-in-abstract"
  },
  {
    "cluster_id": "3802626912783967472",
    "title": "Implementation and characterization of a memristive memory system",
    "authors": [
      "D Radakovits",
      "N TaheriNejad"
    ],
    "first_author_last": "Radakovits",
    "year": 2019,
    "venue": "IEEE Canadian …",
    "link": "https://ieeexplore.ieee.org/abstract/document/8861788/",
    "doi": "10.1109/ccece.2019.8861788",
    "cited_by": 13,
    "snippet": "… for reading the data from memristors as opposed to voltage pulses. Reading the data from the … were undertaken with memristors fabricated by KNOWM [19]. The memristors are tungsten …",
    "pdf_url": "https://eclectx.org/Publications/2019_C29_MemristiveMemory_CCECE.pdf",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "Memristors are one of the promising emerging technologies to address several challenges faced by the computing system of the day. However, a sizeable portion of the works in the literature are not supported by practical implementations or their details are kept as trade secrets. In this work, we propose and implement a writing and reading circuit for a memristive memory system and present our measurement results. A key feature of the proposed system is that it does not need any read-out compensation and virtually no refreshing (due to readout). However, we observed that by the passage of the time (and irrespective of not applying any inputs) some information loss happens, which necessitates refreshing and dictates its frequency. We associate this phenomenon, which has not been reported in the literature before, to what we call “leakage current”. We anticipate this paper to be a starting point for seeing more implementation-based works in the literature, modeling the leakage current phenomenon, and incorporating such design and consideration into the design process of memristive systems.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W2979553033",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "llm_verdict": "uncertain",
    "llm_confidence": "low",
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "5650421672369914898",
    "title": "Hardware implementation of a low power memristor-based voltage controlled oscillator",
    "authors": [
      "MI Selmy",
      "H Mostafa"
    ],
    "first_author_last": "Selmy",
    "year": 2019,
    "venue": "31st International …",
    "link": "https://ieeexplore.ieee.org/abstract/document/9021706/",
    "doi": "10.1109/icm48031.2019.9021706",
    "cited_by": 3,
    "snippet": "… Section III introduces Knowm's memristor: structure, work principles, generalized metastable switch (MSS) model, and programming. Section IV presents the prototype circuits …",
    "pdf_url": "https://www.researchgate.net/profile/Mohamed-Selmy-3/publication/339767013_Hardware_Implementation_of_a_Low_Power_Memristor-Based_Voltage_Controlled_Oscillator/links/61c6ff2bb8305f7c4bfd438a/Hardware-Implementation-of-a-Low-Power-Memristor-Based-Voltage-Controlled-Oscillator.pdf",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": true,
    "devices": [],
    "abstract": "Designing and implementation of a low frequency voltage controlled oscillator to achieve a wide tuning range with a practical small area and low power constraints is a challenge. In this paper, the challenge is overcome by replacing the large values of resistances that occupy large Silicon area in the conventional design by memristors and hence smaller values of capacitances are used. Therefore, this paper proposes and characterizes a hardware implementation of a memristors-based voltage controlled oscillator that used in Electrical Neural Stimulation. The basic proposed circuit generates low frequency signals that range from 1.2 KHz to 3.4 KHz with small area and low power consumption about 0.49 mW. In addition, four-stages D-flip-flops are used as a frequency divider circuit to reduce the frequency range from KHz range to Hz range which is very useful in biomedical and embedded systems applications.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W3010913949",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "llm_verdict": "uncertain",
    "llm_confidence": "low",
    "pdf_knowm": null,
    "knowm_role": "uses-knowm-device",
    "human_verdict": "uses-knowm-device",
    "human_reason": "YES: paper text says 'Knowm Memristor'"
  },
  {
    "cluster_id": "9564299245144080000",
    "title": "From behavioral design of memristive circuits and systems to physical implementations",
    "authors": [
      "N TaheriNejad",
      "D Radakovits"
    ],
    "first_author_last": "TaheriNejad",
    "year": 2019,
    "venue": "IEEE Circuits and Systems Magazine",
    "link": "https://eclectx.org/Publications/2019_J8_CASmag_Paper.pdf",
    "doi": "10.1109/mcas.2019.2945209",
    "cited_by": 27,
    "snippet": "… 5) a memory write and read circuit [95] and measured the maximum retention time of Knowm “BS-AF-W” memristors [96]. Our measurement showed 81 hours of retention time (488 reads…",
    "pdf_url": "https://eclectx.org/Publications/2019_J8_CASmag_Paper.pdf",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": true,
    "devices": [],
    "abstract": "Since Hewlett Packard (HP) announced the passive fabrication of their memristors, various memristive technologies?as a promising emerging technology?have gained ever-increasing attention from the researchers. Although a natural application is using them as memory units, there have been several works in the literature showing their utilization in circuits and systems. While research on various aspects of memristive circuits and systems has been proliferating, the majority of these works are based on simulations at different levels of modeling abstraction. Simulation is a very helpful design tool, and there have been several efforts in modeling memristors; however, we contend that at this point these simulations represent the reality of the behavior of memristors, especially in a circuit or system set-up, only to a very limited extent. We show how this negatively affects the reproduction of designed circuits and systems in different simulation levels, and more importantly in a real-world set-up with physical implementation. Following that, we look into some considerations which can improve the reproducibility of the circuits and systems to be designed in the future. We conclude the paper by suggesting certain approaches to tackle these practical challenges at device level as well as circuit and system level.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W2990351842",
    "relevance": "cites",
    "review_screen": "unclear",
    "review_reason": "no strong cues",
    "llm_verdict": "not-knowm",
    "llm_confidence": "high",
    "pdf_knowm": "cites",
    "knowm_role": "cites"
  },
  {
    "cluster_id": "4338701922128780932",
    "title": "A semi-serial topology for compact and fast IMPLY-based memristive full adders",
    "authors": [
      "N TaheriNejad",
      "T Delaroche"
    ],
    "first_author_last": "TaheriNejad",
    "year": 2019,
    "venue": "17th IEEE …",
    "link": "https://ieeexplore.ieee.org/abstract/document/8961312/",
    "doi": "10.1109/newcas44328.2019.8961312",
    "cited_by": 27,
    "snippet": "… memristors is proportional to the size of the adder, n. Most serial adders use only two work memristors, however, our three additional work memristors … ) produced by KNOWM [15]. The …",
    "pdf_url": "https://eclectx.org/Publications/2019_Semiserial_NewCAS.pdf",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "Memristive systems are among the emerging technologies that hold a great promise. They are compact, CMOS compatible, easy to fabricate and can serve for storage as well as computation purposes. Adders are one of the most basic and critical building blocks of any computing system. One of the main application areas of memristors is in Material Implication (IMPLY) based logic. IMPLY-based adders are implemented either in serial, which has a compact implementation but needs many steps for calculation, or in parallel, which is fast, however, requires a large number of memristors. In this paper we propose an IMPLY-based adder topology and its respective addition algorithm which is 54-to-65% faster than serial adders and requires 46-to-76% less memristors than parallel adders. This topology is a favorable candidate for applications where neither speed, nor cost (i.e., area or number of memristors) could be compromised to gain the required performance.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W3002848853",
    "relevance": "cites",
    "review_screen": "unclear",
    "review_reason": "no strong cues",
    "llm_verdict": "not-knowm",
    "llm_confidence": "high",
    "pdf_knowm": "cites",
    "knowm_role": "cites"
  },
  {
    "cluster_id": "17549681273188406683",
    "title": "A novel universal interface for constructing memory elements for circuit applications",
    "authors": [
      "C Zheng",
      "D Yu",
      "HHC Iu",
      "T Fernando"
    ],
    "first_author_last": "Zheng",
    "year": 2019,
    "venue": "IEEE Transactions on Circuits and Systems I Regular Papers",
    "link": "https://ieeexplore.ieee.org/abstract/document/8844258/",
    "doi": "10.1109/tcsi.2019.2938094",
    "cited_by": 43,
    "snippet": "… ) device of the commercialized Knowm memristor according to its … For example, the Knowm MR will continue to function under … As memristor technology improves in high-frequency opera…",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "The rapid expansion of analog and neuromorphic memristive applications has proven that their reconfigurable and reprogrammable characteristics will be major proponents for pushing beyond Moore's Law. The lack of easily accessible and reliable solid-state memory elements (mem-elements) results in an ever-increasing body of the research lacking physical verification, and an associated high barrier to entry for researchers. This paper serves to fix this deficiency by introducing a novel universal interface circuit, which when connected to different peripheral circuits, can be used to build fundamental mem-elements. There is an abundance of mem-element emulators, we adopt their advantages into our design to foster practical and broadly applicable mem-element circuits. In comparison to other similar state-of-the-art emulators, our circuit utilized up to 42.9% fewer active components which consumed up to 31.9% less power with an associated reduction of size by 41.7%. Our proposed emulator continues to operate with hysteresis at over 180 kHz, which is two orders of magnitude higher than other similar emulators and commercially available solid-state memristors, whilst maintaining floating terminal connections. Rigorous theoretical, simulation and experimental results are conducted with good agreement with applications given, demonstrating the ability of the universal interface to discretely build mem-elements.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W2974230004",
    "relevance": "excluded",
    "review_screen": "likely-cite-only",
    "review_reason": "cite/other-device cues: emulator, simulation",
    "pdf_knowm": null,
    "knowm_role": null,
    "human_verdict": "not-knowm",
    "human_reason": "NO (user)"
  },
  {
    "cluster_id": "15213051183158294218",
    "title": "基于 Knowm 忆阻器的新型忆感器模型的设计与分析",
    "authors": [
      "朱雷杰， 王发强"
    ],
    "first_author_last": "王发强",
    "year": 2019,
    "venue": "物理学报",
    "link": "https://wulixb.iphy.ac.cn/fileWLXB/journal/article/wlxb/2019/19/PDF/19-20190793.pdf",
    "doi": null,
    "cited_by": 2,
    "snippet": "… Design and analysis of new meminductor model based on Knowm memristor Zhu Lei-Jie Wang Fa-Qiang … Design and analysis of new meminductor model based on Knowm memristor* …",
    "pdf_url": "https://wulixb.iphy.ac.cn/fileWLXB/journal/article/wlxb/2019/19/PDF/19-20190793.pdf",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": null,
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-model",
    "knowm_role": "uses-model"
  },
  {
    "cluster_id": "nNcP3oIS1loJ",
    "title": "Design of Memristor Device Based Voltage",
    "authors": [
      "MIS Ahmed"
    ],
    "first_author_last": "Ahmed",
    "year": 2020,
    "venue": "",
    "link": "https://onelab-eg.com/wp-content/uploads/2020/12/PDF-2.pdf",
    "doi": null,
    "cited_by": 0,
    "snippet": "… Knowm Memristor Package [9]. .................................................. … Memristor programming using Knowm Kit along with analog … It is important to know how the memristor works with an external …",
    "pdf_url": "https://onelab-eg.com/wp-content/uploads/2020/12/PDF-2.pdf",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": null,
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "662422482151286687",
    "title": "Post-binary robotics: Using memristors with ternary states for robotics control",
    "authors": [
      "S Bos",
      "JB Nilsen",
      "H Gundersen"
    ],
    "first_author_last": "Bos",
    "year": 2020,
    "venue": "IEEE 8th Electronics …",
    "link": "https://ieeexplore.ieee.org/abstract/document/9229820/",
    "doi": "10.1109/estc48849.2020.9229820",
    "cited_by": 0,
    "snippet": "… version of the Knowm mean metastable switch model [21], [23], … of the generalized metastable switch memristor model [25], a … The metastable switch model is, like the real 16x1 SDC-W (…",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": true,
    "devices": [],
    "abstract": "This paper presents a method to read and write ternary (three-valued) signals on memristors to control a robotic actuator in real-time. The paper is a continuation of earlier work by [1] and implements a ternary memory controller for memristors in hardware. This post-binary approach with nonvolatile memory is used to program a memristor as a \"trit\". The paper contributes to the state-of-the-art in memristor controlled robotics by reporting an entropy gain of log2(3)= 58% information at (20 versus 14)= 43% more component cost compared to binary. This advantage (eg. less wire complexity) increases when multi-trit architectures are considered.This article demonstrates both an LTspice simulation of the circuit and implementation with source code. The memristor programmer circuit writes a state to the memristor using a pattern of 100us pulses at 3 different amplitudes. The memristor read circuit sends 500 nA pulses and converts these using two reference resistors to three logic levels using an op amp window comparator. An Arduino Mega microcontroller ADC pin converts the analog output to a digital trit. Strenuous effort was made for predictable and replicable applied memristor research in pursuit of a post-binary robotics era. The multiple-valued circuit has safety features to prevent harm to the memristance state, standardized forming of new memristors and programming flexibility by sending patterns of different pulse amounts, pulse width and pulse amplitudes.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W3093786219",
    "relevance": "excluded",
    "review_screen": "likely-cite-only",
    "review_reason": "cite/other-device cues: ltspice, spice, new memristor, simulation",
    "pdf_knowm": null,
    "knowm_role": null,
    "human_verdict": "not-knowm",
    "human_reason": "NO (user)"
  },
  {
    "cluster_id": "2748607712397435373",
    "title": "uMemristorToolbox: Open source framework to control memristors in Unity for ternary applications",
    "authors": [
      "S Bos",
      "H Gundersen",
      "F Sanfilippo"
    ],
    "first_author_last": "Bos",
    "year": 2020,
    "venue": "IEEE 50th …",
    "link": "https://ieeexplore.ieee.org/abstract/document/9308339/",
    "doi": "10.1109/ismvl49045.2020.000-3",
    "cited_by": 2,
    "snippet": "… in commercially available, mass-produced memristors over several months. We encourage the research community to experiment with the Knowm Memristor-Discovery (Java) and this (…",
    "pdf_url": "https://www.academia.edu/download/87936559/Sanfilippo.pdf",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": true,
    "devices": [
      "W"
    ],
    "abstract": "This paper presents uMemristorToolbox, a novel open source framework that reads and writes non-volatile ternary states to memristors. The Unity (C#) framework is a port of the open source Java project Memristor-Discovery and adds a closed-loop ternary memory controller to enable both PC and real-time embedded ternary applications. We validate the closed-loop ternary memory controller in an embedded system case study with 16 M+SDC Tungsten dopant memristors. We measure an average switching speed of 3 Hz, worst case energy usage of 1 μW per switch, 0.03% random write error and no decay in (non-volatile) state retention after 15 minutes. We conclude with observations and open questions when working with memristors for ternary applications.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://hdl.handle.net/11250/2756007",
    "openalex_id": "https://openalex.org/W3119665920",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "named-in-abstract"
  },
  {
    "cluster_id": "12933510983565765049",
    "title": "Empirical temperature model of self-directed channel memristor",
    "authors": [
      "T Bunnam",
      "A Soltan",
      "D Sokolov",
      "O Maevsky"
    ],
    "first_author_last": "Bunnam",
    "year": 2020,
    "venue": "IEEE …",
    "link": "https://ieeexplore.ieee.org/abstract/document/9278602/",
    "doi": "10.1109/sensors47125.2020.9278602",
    "cited_by": 9,
    "snippet": "… memristor chips in ceramic packages from Knowm Inc. Two out of eight memristors from each chip were selected: memristor#4 and #8 from chip#2 (C2M4 and C2M8), and memristor#1 …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": true,
    "is_mss": false,
    "devices": [],
    "abstract": "Memristors are used in many innovative research areas. However, the temperature has a strong effect on memristance, which results in malfunctions. Although commercial a memristor is available, its thermal characteristics are still under-explored. This paper presents a temperature model of a self-directed channel memristor. The experimental results of measuring high-resistive-state memristance between 253K and 383K show the inverse relation, which can be described by an exponential equation. This relation is similar to metal-oxide memristors; therefore, our model is expected to cover many memristor types. The presented model enables improved temperature tolerance in memristive circuits and temperature sensing applications.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W3113252899",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "named-in-abstract"
  },
  {
    "cluster_id": "11731335452597464508",
    "title": "The effects of radiation on memristor-based electronic spiking neural networks",
    "authors": [
      "SG Dahl"
    ],
    "first_author_last": "Dahl",
    "year": 2020,
    "venue": "",
    "link": "https://scholarworks.boisestate.edu/td/1713/",
    "doi": "10.18122/td/1713/boisestate",
    "cited_by": 2,
    "snippet": "… Self-Directed Channel (SDC) SDC memristive devices are ion-conducting devices that … into channels within its active layer. Permanent conductive channels formed in Ge2Se3 active …",
    "pdf_url": "https://scholarworks.boisestate.edu/cgi/viewcontent.cgi?article=2844&context=td",
    "is_knowm": false,
    "is_sdc": true,
    "is_mss": true,
    "devices": [],
    "abstract": "In this dissertation, memristor-based spiking neural networks (SNNs) are used to analyze the effect of radiation on the spatio-temporal pattern recognition (STPR) capability of the networks. Two-terminal resistive memory devices (memristors) are used as synapses to manipulate conductivity paths in the network. Spike-timing-dependent plasticity (STDP) learning behavior results in pattern learning and is achieved using biphasic shaped pre- and post-synaptic spikes. A TiO<sub>2</sub> based non-linear drift memristor model designed in Verilog-A implements synaptic behavior and is modified to include experimentally observed effects of state-altering, ionizing, and off-state degradation radiation on the device. The impact of neuron \"death\" (disabled neuron circuits) due to radiation is also examined. In general, radiation interaction events distort the STDP learning curve undesirably, favoring synaptic potentiation. At lower short-term flux, the network is able to recover and relearn the pattern with consistent training, although some pixels may be affected due to stability issues. As the radiation flux and duration increases, it can overwhelm the leaky integrate-and-fire (LIF) post-synaptic neuron circuit, and the network does not learn the pattern. On the other hand, in the absence of the pattern, the radiation effects cumulate, and the system never regains stability. Neuron-death simulation results emphasize the importance of non-participating neurons during the learning process, concluding that non-participating afferents contribute to improving the learning ability of the neural network. Instantaneous neuron death proves to be more detrimental for the network compared to when the afferents die over time thus, retaining the network's pattern learning capability.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://scholarworks.boisestate.edu/cgi/viewcontent.cgi?article=2844&context=td",
    "openalex_id": "https://openalex.org/W3087402912",
    "relevance": "excluded",
    "review_screen": "unclear",
    "review_reason": "weak use cues: experimental, experiment",
    "llm_verdict": "not-knowm",
    "llm_confidence": "high",
    "pdf_knowm": null,
    "knowm_role": null
  },
  {
    "cluster_id": "8936290010486314593",
    "title": "Comprehensive predictive modeling of resistive switching devices using a bias-dependent window function approach",
    "authors": [
      "C Fernandez",
      "J Gomez",
      "J Ortiz",
      "I Vourkas"
    ],
    "first_author_last": "Fernandez",
    "year": 2020,
    "venue": "Solid-State Electronics",
    "link": "https://www.sciencedirect.com/science/article/pii/S0038110120300526",
    "doi": "10.1016/j.sse.2020.107833",
    "cited_by": 16,
    "snippet": "… memristors. We present a specific WF formulation and evaluate its effect on the performance of threshold-type models of voltage-controlled bipolar memristor… ) memristors of Knowm Inc. …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "Abstract Development of accurate models for resistive switching devices (memristors) is a research topic of utmost interest. Behavioral models usually employ window functions (WFs) to capture the dependency of the resistance switching-rate on the bias conditions. Several WFs have been published so far, all of them being functions of just the state variable(s), ignoring the effect of the applied signal magnitude in dynamic behavior. In this context, we describe in an extended manner a generalized concept of bias-dependent WFs, designed to enhance behavioral models in capturing rich dynamic time-response of memristors. We present a specific WF formulation and evaluate its effect on the performance of threshold-type models of voltage-controlled bipolar memristor, in simulations with LTSPICE. The obtained results not only reflect the accumulated effect of the applied signal and the proper saturation of the device at voltage-dependent levels, but are also quantitatively in line with experimental data taken from commercial self-directed channel (SDC) memristors of Knowm Inc.",
    "abstract_source": "semanticscholar",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W3024239688",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-model",
    "knowm_role": "uses-model"
  },
  {
    "cluster_id": "2672029978220200796",
    "title": "Shortest path computing in directed graphs with weighted edges mapped on random networks of memristors",
    "authors": [
      "C Fernandez",
      "I Vourkas",
      "A Rubio"
    ],
    "first_author_last": "Fernandez",
    "year": 2020,
    "venue": "Parallel Processing Letters",
    "link": "https://www.worldscientific.com/doi/abs/10.1142/S0129626420500024",
    "doi": "10.1142/S0129626420500024",
    "cited_by": 3,
    "snippet": "… by Knowm Inc. to model behavior of their commercial devices [25]. It is a semi-empirical model known as the “mean metastable switch” memristor model and it describes a memristor as …",
    "pdf_url": "https://upcommons.upc.edu/bitstreams/c4f81699-6845-4108-ac86-26b3f1f37c69/download",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": true,
    "devices": [],
    "abstract": "To accelerate the execution of advanced computing tasks, in-memory computing with resistive memory provides a promising solution. In this context, networks of memristors could be used as parallel computing medium for the solution of complex optimization problems. Lately, the solution of the shortest-path problem (SPP) in a two-dimensional memristive grid has been given wide consideration. Some still open problems in such computing approach concern the time required for the grid to reach to a steady state, and the time required to read the result, stored in the state of a subset of memristors that represent the solution. This paper presents a circuit simulation-based performance assessment of memristor networks as SPP solvers. A previous methodology was extended to support weighted directed graphs. We tried memristor device models with fundamentally different switching behavior to check their suitability for such applications and the impact on the timely detection of the solution. Furthermore, the requirement of binary vs. analog operation of memristors was evaluated. Finally, the memristor network-based computing approach was compared to known algorithmic solutions to the SPP over a large set of random graphs of different sizes and topologies. Our results contribute to the proper development of bio-inspired memristor network-based SPP solvers.",
    "abstract_source": "openalex",
    "oa_pdf_url": "http://hdl.handle.net/2117/332095",
    "openalex_id": "https://openalex.org/W3011640300",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "llm_verdict": "not-knowm",
    "llm_confidence": "high",
    "pdf_knowm": "uses-model",
    "knowm_role": "uses-model"
  },
  {
    "cluster_id": "14238725014824951095",
    "title": "An FPGA based system for interfacing with crossbar arrays",
    "authors": [
      "P Foster",
      "J Huang",
      "A Serb"
    ],
    "first_author_last": "Foster",
    "year": 2020,
    "venue": "… on Circuits and …",
    "link": "https://ieeexplore.ieee.org/abstract/document/9180671/",
    "doi": null,
    "cited_by": 8,
    "snippet": "… a memristor also allows for much smaller cells than with alternative technologies, and a crossbar comfiguration allows high density arrangement for memristor … crossbar arrays; Knowm’s …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "Memristor crossbar arrays offer a novel new approach for designing high density non-volatile memory; however, precise measurement of resistive crossbar elements requires parallel current sensing capability not found in existing instruments. To provide this capability, we have designed and built an FPGA-based crossbar control instrument with independent per-channel biasing and measuring. In this paper, we cover the architecture of this new instrument, its operation and interface, and the results of testing conducted on the instruments pulse driver circuitry.",
    "abstract_source": "ieee-xplore",
    "oa_pdf_url": null,
    "openalex_id": null,
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "uses-knowm-device",
    "human_verdict": "uses-knowm-device",
    "human_reason": "YES (user)"
  },
  {
    "cluster_id": "1049213589051462108",
    "title": "On the Development of MCU-based ad hoc HW Interface Circuitry for Memristor Characterization",
    "authors": [
      "R De La Fuente",
      "I Vourkas"
    ],
    "first_author_last": "Fuente",
    "year": 2020,
    "venue": "… European Conference on …",
    "link": "https://ieeexplore.ieee.org/abstract/document/9218418/",
    "doi": "10.1109/ecctd49232.2020.9218418",
    "cited_by": 7,
    "snippet": "… software, which is extensible and supports several different experiments with memristors. … of up to 1024 memristors in a 32×32 configuration, were recently released by Knowm Inc. …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "The evolution of resistive switching device (memristor) technology during the last ten years has shown the great potential of such emerging nanoelectronic devices in several potential applications, ranging from memory to computing and sensing. As memristor technology is continuously maturing, more devices become commercially available and thus accessible to investigators working on relevant research topics, as well as to university teaching labs and academics who wish to incorporate memristor-related experiments in their classrooms. However, experimental work on circuits with memristors requires particular caution and supervision, given that such devices are both highly sensitive (i.e., can easily burn out) and still quite expensive compared to other discrete circuit components. In this context, the development of integrated instrumentation solutions that provide a safe way to experimental work with memristors is becoming increasingly relevant, and some such tools have already reached the market. In this direction, we present some early results from our experience on the design and development of an instrumentation printed circuit board (PCB), designed to provide an ad hoc low-cost solution for measurements on memristors. The driving circuitry on the PCB is interfaced through a microcontroller-based system, providing easy programming and acquisition for a variety of measurements.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W3092057602",
    "relevance": "excluded",
    "review_screen": "likely-use",
    "review_reason": "use cues: commercially available, measurement, experimental, experiment",
    "llm_verdict": "uncertain",
    "llm_confidence": "medium",
    "human_verdict": "not-knowm",
    "human_reason": "NO (user)",
    "pdf_knowm": null,
    "knowm_role": null
  },
  {
    "cluster_id": "10746301784907456468",
    "title": "A comparative study on the forming methods of chalcogenide memristors to optimize the resistive switching performance",
    "authors": [
      "HJ Gogoi",
      "AT Mallajosyula"
    ],
    "first_author_last": "Gogoi",
    "year": 2020,
    "venue": "Journal of Physics D Applied Physics",
    "link": "https://iopscience.iop.org/article/10.1088/1361-6463/aba56e/meta",
    "doi": "10.1088/1361-6463/aba56e/meta",
    "cited_by": 12,
    "snippet": "… Ge2Se3 chalcogenide memristors … channel oscilloscope shows the voltage change across the standard resistor Rload (Va at channel 1) and the voltage change across the memristor …",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": true,
    "devices": [
      "W"
    ],
    "abstract": "Abstract Most of the memristor devices require an electroforming step to initiate resistance switching in them. Electroforming a pristine memristor could alter the material composition and/or the device structure, thereby, altering its electrical resistance. This acts as a vital step to optimize the devices for memory applications. In this work, commercially available Ge 2 Se 3 chalcogenide memristors have been characterized electrically. In these devices, the active layer is sandwiched between a tungsten bottom electrode and a silver top layer, and their operation is based on the migration of silver ions into the active layer. Different electroforming methods, such as the use of sinusoidal signal, linear voltage sweep, linear current sweep, constant voltage bias, and fast voltage pulse have been applied to form pristine memristors and their effects on memristor performance has been studied. A current sweep signal cannot provide high enough electric field to obtain a reasonable ON/OFF ratio during forming. In fact, forming using this method is found to be redundant since the subsequent voltage sweep for device operation itself acts as a forming step. Forming with a constant bias signal provides the information regarding switching times and forming rate can be controlled. However, devices formed using this method are found to show unpredictable switching behaviour and it is challenging to choose the suitable voltage level for forming. The devices formed using positive voltage sweep method have been found to give the most repeatable switching characteristics. This method is essential to study the switching mechanism and current conduction in the device during the operation. On the other hand, ultra-fast voltage pulses form the memristor at a much faster rate in comparison to the other DC forming methods, however, at the cost of using a higher voltage level.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W3043715094",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "llm_verdict": "uses-knowm-device",
    "llm_confidence": "high",
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "16246407770031333105",
    "title": "Controlling Real Memristors in Embedded Systems",
    "authors": [
      "P Grothe",
      "J Haase"
    ],
    "first_author_last": "Grothe",
    "year": 2020,
    "venue": "IEEE 29th International Symposium …",
    "link": "https://ieeexplore.ieee.org/abstract/document/9152495/",
    "doi": "10.1109/isie45063.2020.9152495",
    "cited_by": 0,
    "snippet": "… Real memristors have been available through Knowm Inc. for some years now. This allows for researchers that are not associated with the few institutions that produce …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "Memristors are a relatively new and immensely promising type of basic circuit element. As variable resistors the state of which depends on its former resistances, as well as applied voltage and flowing current, it behaves in a way that is not simply replicated by other components and therefore makes possible new types of analog implementations.While numerous models have been created since the discovery of the memristor, real memristors have not been around for long and in some ways drastically differ from models that simulate the ideal and hypothetically one day achievable ideal memristor. To account for the behavior of real memristors is however of utmost importance.In this work a preferably simple controller was implemented to enable reading and setting of memristors. It was designed with the constraints in mind to be of low complexity and use only unipolar DC voltages so that it may be applied in embedded systems.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W3046729480",
    "relevance": "excluded",
    "review_screen": "unclear",
    "review_reason": "weak use cues: real memristor",
    "llm_verdict": "uncertain",
    "llm_confidence": "medium",
    "pdf_knowm": null,
    "knowm_role": null,
    "human_verdict": "not-knowm",
    "human_reason": "NO (user): not sure from abstract"
  },
  {
    "cluster_id": "4570914761763142650",
    "title": "An experimental proof that resistance‐switching memory cells are not memristors",
    "authors": [
      "J Kim",
      "YV Pershin",
      "M Yin",
      "T Datta"
    ],
    "first_author_last": "Kim",
    "year": 2020,
    "venue": "Advanced Electronic Materials",
    "link": "https://advanced.onlinelibrary.wiley.com/doi/abs/10.1002/aelm.202000010",
    "doi": "10.1002/aelm.202000010",
    "cited_by": 38,
    "snippet": "… the memristor test to commercially available EMCs [ 19 ] (Knowm, … memristor, the measurement results would group between the dashed lines. Clearly, it is not the case of both BS-AF-W …",
    "pdf_url": "https://arxiv.org/pdf/1909.07238",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": true,
    "devices": [],
    "abstract": "Abstract It has been suggested that all resistive‐switching memory cells are memristors. The latter are hypothetical, ideal devices whose resistance, as originally formulated, depends only on the net charge that traverses them. Recently, an unambiguous test has been proposed to determine whether a given physical system is indeed a memristor or not. Here, such a test is experimentally applied to both in‐house fabricated Cu‐SiO 2 and commercially available electrochemical metallization cells. The results unambiguously show that electrochemical metallization memory cells are not memristors. Since the particular resistance‐switching memories employed in the study share similar features with many other memory cells, the findings refute the claim that all resistance‐switching memories are memristors. They also cast doubts on the existence of ideal memristors as actual physical devices that can be fabricated experimentally. The results then lead to formulate two memristor impossibility conjectures regarding the impossibility of building a model of physical resistance‐switching memories based on the memristor model.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://arxiv.org/pdf/1909.07238",
    "openalex_id": "https://openalex.org/W2972940114",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "human_verdict": "uses-knowm-device",
    "human_reason": "YES: tests commercially available ECMs by Knowm Inc. (BS-AF-W and M+SDC Cr devices)",
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-knowm-device"
  },
  {
    "cluster_id": "3062374994988710826",
    "title": "Towards in-memory computing: Arithmetic operations on real memristors",
    "authors": [
      "T Kolms",
      "C Lang",
      "A Waldner",
      "P Grothe"
    ],
    "first_author_last": "Kolms",
    "year": 2020,
    "venue": "IECON 2020 The 46th Annual Conference of the IEEE Industrial Electronics Society",
    "link": "https://ieeexplore.ieee.org/abstract/document/9254441/",
    "doi": "10.1109/iecon43393.2020.9254441",
    "cited_by": 2,
    "snippet": "… For the memristor memory cells a Knowm tier-1 BS-AF-W memristor was used in a voltage divider configuration with a 100kΩ resistor. The threshold of these memristors … , the memristor …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": true,
    "devices": [],
    "abstract": "In-memory-computing is an emerging approach that aims to shift computational load away from CPUs. It does so by taking over simple calculations that can be performed in memory. Apart from improving performance for these operations, this also results in a lower energy consumption, effectively rendering this technique very suitable for embedded systems. Due to being variable as well as non-volatile resistors, memristors are capable of storing analog values. This renders them particularly useful for in-memory computing. This paper presents a prototypical implementation of analog calculations (addition, subtraction and multiplication), including a way of representing the value zero. The prototype shown is based on an ESP32 microcontroller and typical calculations currently take around 1μs.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W3104886172",
    "relevance": "excluded",
    "review_screen": "unclear",
    "review_reason": "no strong cues",
    "llm_verdict": "uncertain",
    "llm_confidence": "low",
    "pdf_knowm": "uses-device",
    "knowm_role": null,
    "human_verdict": "not-knowm",
    "human_reason": "NO (user): not sure from abstract"
  },
  {
    "cluster_id": "6862829915069874136",
    "title": "Analog implementation of arithmetic operations on real memristors",
    "authors": [
      "T Kolms",
      "A Waldner",
      "C Lang",
      "P Grothe"
    ],
    "first_author_last": "Kolms",
    "year": 2020,
    "venue": "Proceedings of the 23th …",
    "link": "https://dl.acm.org/doi/abs/10.1145/3378678.3391883",
    "doi": "10.1145/3378678.3391883",
    "cited_by": 1,
    "snippet": "… memristor memory cells a Knowm tier-1 BS-AF-W memristor was used in a voltage divider configuration with a 100𝑘Ω resistor. The threshold of these memristors is … , the memristor cells …",
    "pdf_url": "https://dl.acm.org/doi/pdf/10.1145/3378678.3391883",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": true,
    "devices": [],
    "abstract": "The upcoming topic of in-memory-computing tries to support CPUs by taking over simple calculations that can be done in memory. This leads to less performance drain caused by those simple calculations as well as lower energy consumption for the whole system, which is particularly important for embedded systems.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W3031713074",
    "relevance": "excluded",
    "review_screen": "unclear",
    "review_reason": "no strong cues",
    "llm_verdict": "uncertain",
    "llm_confidence": "low",
    "pdf_knowm": "uses-device",
    "knowm_role": null,
    "human_verdict": "not-knowm",
    "human_reason": "NO (user)"
  },
  {
    "cluster_id": "2751952256279772604",
    "title": "Memristive GAN in analog",
    "authors": [
      "O Krestinskaya",
      "B Choubey",
      "AP James"
    ],
    "first_author_last": "Krestinskaya",
    "year": 2020,
    "venue": "Scientific Reports",
    "link": "https://www.nature.com/articles/s41598-020-62676-7",
    "doi": "10.1038/s41598-020-62676-7",
    "cited_by": 57,
    "snippet": "… This method allows to illustrate a generalized scenario of memristor failures and their effect … G m is a total memristor conductance over N metastable switches and ΔG m is a change in …",
    "pdf_url": "https://www.nature.com/articles/s41598-020-62676-7.pdf",
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": true,
    "devices": [],
    "abstract": "Abstract Generative Adversarial Network (GAN) requires extensive computing resources making its implementation in edge devices with conventional microprocessor hardware a slow and difficult, if not impossible task. In this paper, we propose to accelerate these intensive neural computations using memristive neural networks in analog domain. The implementation of Analog Memristive Deep Convolutional GAN (AM-DCGAN) using Generator as deconvolutional and Discriminator as convolutional memristive neural network is presented. The system is simulated at circuit level with 1.7 million memristor devices taking into account memristor non-idealities, device and circuit parameters. The design is modular with crossbar arrays having a minimum average power consumption per neural computation of 47nW. The design exclusively uses the principles of neural network dropouts resulting in regularization and lowering the power consumption. The SPICE level simulation of GAN is performed with 0.18 μ m CMOS technology and WO x memristive devices with R O N = 40 kΩ and R O F F = 250 kΩ, threshold voltage 0.8 V and write voltage at 1.0 V.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://www.nature.com/articles/s41598-020-62676-7.pdf",
    "openalex_id": "https://openalex.org/W3014166398",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-model",
    "knowm_role": "uses-model"
  },
  {
    "cluster_id": "2277293639212271031",
    "title": "Stochastic and novel generic scalable window function-based deterministic memristor SPICE model comparison and implementation for synaptic circuit design",
    "authors": [
      "M Nigus",
      "R Priyadarshini",
      "RM Mehra"
    ],
    "first_author_last": "Nigus",
    "year": 2019,
    "venue": "SN Applied Sciences",
    "link": "https://www.academia.edu/download/91163545/s42452-019-1888-z.pdf",
    "doi": "10.1007/s42452-019-1888-z",
    "cited_by": 6,
    "snippet": "… memristor model, whereas the general metastable switch (MSS) memristor model [22] is classified as stochastic memristor … memristor model they call which the generalized metastable …",
    "pdf_url": "https://www.academia.edu/download/91163545/s42452-019-1888-z.pdf",
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": true,
    "devices": [],
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": "https://link.springer.com/content/pdf/10.1007/s42452-019-1888-z.pdf",
    "openalex_id": "https://openalex.org/W2996601717",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "6370123254138151694",
    "title": "A comprehensive study on the characteristics, complex materials and applications of memristor",
    "authors": [
      "N Nithya",
      "K Paramasivam"
    ],
    "first_author_last": "Nithya",
    "year": 2020,
    "venue": "6th International Conference …",
    "link": "https://ieeexplore.ieee.org/abstract/document/9074392/",
    "doi": "10.1109/icaccs48705.2020.9074392",
    "cited_by": 8,
    "snippet": "… memristor was released in the market by Knowm Inc., in July 2015. The Knowm memristor … The key players in memristor market includes HP, Intel, Knowm Inc., Micron etc., This review …",
    "pdf_url": "https://www.researchgate.net/profile/Nithya-Natarajan-4/publication/340888414_A_Comprehensive_Study_on_the_Characteristics_Complex_Materials_and_Applications_of_Memristor/links/5eb4d26f4585152169be805f/A-Comprehensive-Study-on-the-Characteristics-Complex-Materials-and-Applications-of-Memristor.pdf",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "In 1971, Leon Chua postulated the fourth passive element memristor [1], which establishes a nexus between charge and flux. The memory property of the proposed memristor portrays the fact that its memristance is obtained by the past history of driving input. If the driving input is detached, the ideal memristor device will maintain its current state until the device was driven by new input. By using this property, the existing Complementary Metal Oxide Semiconductor (CMOS) based memory block can be replaced by memristor based memory block for potentially higher density, low energy and low power consumption. This review paper throws research highlights on the characteristics, complex materials used for fabrication, various applications and approaches of memristor.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W3018320985",
    "relevance": "excluded",
    "review_screen": "likely-cite-only",
    "review_reason": "cite/other-device cues: proposed memristor",
    "pdf_knowm": null,
    "knowm_role": null,
    "human_verdict": "not-knowm",
    "human_reason": "NO (user)"
  },
  {
    "cluster_id": "855505125953164657",
    "title": "Knowm Memristor Discovery Manual",
    "authors": [
      "A Nugent"
    ],
    "first_author_last": "Nugent",
    "year": 2020,
    "venue": "Knowm Inc., September",
    "link": "",
    "doi": null,
    "cited_by": 3,
    "snippet": "",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": true,
    "devices": [],
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": null,
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "named-in-abstract"
  },
  {
    "cluster_id": "6605034744396407401",
    "title": "Flux-controlled memristor emulator and its experimental results",
    "authors": [
      "N Raj",
      "RK Ranjan",
      "F Khateb"
    ],
    "first_author_last": "Raj",
    "year": 2022,
    "venue": "Research Square",
    "link": "https://ieeexplore.ieee.org/abstract/document/8976216/",
    "doi": "10.21203/rs.3.rs-1414009/v1",
    "cited_by": 1,
    "snippet": "… Similarly, a known SDC memristor [15] is an integrated circuit based on a chalcogenide layer having four variants depending on the dopant introduced in the active layer. Several …",
    "pdf_url": "https://www.researchgate.net/profile/Niranjan-Raj/publication/338927442_Flux-Controlled_Memristor_Emulator_and_Its_Experimental_Results/links/5e3c092992851c7f7f208667/Flux-Controlled-Memristor-Emulator-and-Its-Experimental-Results.pdf",
    "is_knowm": false,
    "is_sdc": true,
    "is_mss": false,
    "devices": [],
    "abstract": "Abstract In this article, a flux-controlled memristor emulator is proposed. The proposed memristor emulator is designed using a single DVCC, three MOSFETs, and one capacitor. Among three MOSFETs, two MOS is used to create an active resistor, and one MOS is used to generate the multiplication factor required for the memristor emulator. The proposed emulator work for both incremental and decremental configurations. PSpice simulation with 180 nm CMOS technology is performed to validate the proposed memristor emulator. The proposed design operates up to 100 MHz frequency. The proposed memristor emulator is experimentally verified using AD844AN and CD4007 ICs. A high pass filter is implemented using the emulator for validating the resistive property of the proposed memristor emulator.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://www.researchsquare.com/article/rs-1414009/latest.pdf",
    "openalex_id": "https://openalex.org/W4311479435",
    "relevance": "excluded",
    "review_screen": "likely-cite-only",
    "review_reason": "cite/other-device cues: emulator, spice, proposed memristor, simulation",
    "pdf_knowm": "none",
    "knowm_role": null
  },
  {
    "cluster_id": "1048985422354653720",
    "title": "Hybrid CMOS/Memristor Circuits Emulator",
    "authors": [
      "AFÁ Silva"
    ],
    "first_author_last": "Silva",
    "year": 2020,
    "venue": "",
    "link": "https://search.proquest.com/openview/be69b0eb8a38f6dbb2736ab05cf23e44/1?pq-origsite=gscholar&cbl=2026366&diss=y",
    "doi": null,
    "cited_by": 0,
    "snippet": "… The Knowm’s memristor model is also explored and a model parameter fitting is done from real data. A problem with this model is presented and a modification is proposed. All …",
    "pdf_url": "https://repositorio-aberto.up.pt/bitstream/10216/132686/2/429939.pdf",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": null,
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "17537921629528048105",
    "title": "Flux controlled floating memristor employing VDTA: Incremental or decremental operation",
    "authors": [
      "J Vista",
      "A Ranjan"
    ],
    "first_author_last": "Vista",
    "year": 2020,
    "venue": "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems",
    "link": "https://ieeexplore.ieee.org/abstract/document/9108235/",
    "doi": "10.1109/tcad.2020.2999919",
    "cited_by": 57,
    "snippet": "… In [17] and [18], solid-state memristors are commercialized by KNOWM with prominent usage in memory, logic, and machine learning applications. However, the commercial memristor …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "This research article offers a floating memristor model using single voltage difference transconductance amplifier (VDTA) and grounded passive components. The proper utilization of VDTA port characteristics with passive components exhibits both incremental and decremental modes of operation without multiplier circuit. The performance analysis of proposed memristor is verified by using post layout Cadence Virtuoso simulation to examine the characteristics of all possible temperature and process Corners. In addition, experimental verification of VDTA-based memristor is done using commercially available operational transconductance amplifier (OTA) as IC CA3080. The results obtained through simulation and experiment follows the theoretical aspects. Moreover, an application perspective of the proposed design includes a brief neuromorphic circuit implementation for Pavlovian associative learning experiment.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W3033566110",
    "relevance": "excluded",
    "review_screen": "likely-use",
    "review_reason": "use cues: commercially available, experimental, experiment",
    "llm_verdict": "not-knowm",
    "llm_confidence": "high",
    "pdf_knowm": null,
    "knowm_role": null
  },
  {
    "cluster_id": "12536717283094894249",
    "title": "A dream that has come true: Chaos from a nonlinear circuit with a real memristor",
    "authors": [
      "CK Volos",
      "VT Pham",
      "HE Nistazakis"
    ],
    "first_author_last": "Volos",
    "year": 2020,
    "venue": "International Journal of Bifurcation and Chaos",
    "link": "https://www.worldscientific.com/doi/abs/10.1142/S0218127420300360",
    "doi": "10.1142/S0218127420300360",
    "cited_by": 44,
    "snippet": "… nonlinear circuit, in which its nonlinear element has been replaced with a commercially available memristor (KNOWM memristor), is presented in this work. Interesting phenomena …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "In the last decade, researchers, who work in the field of nonlinear circuits, have the “dream” to use a real memristor, which is the only nonlinear fundamental circuit element, in a new or other reported nonlinear circuit in literature, in order to experimentally investigate chaos. With this intention, for the first time, a well-known nonlinear circuit, in which its nonlinear element has been replaced with a commercially available memristor (KNOWM memristor), is presented in this work. Interesting phenomena concerning chaos theory, such as period-doubling route to chaos, coexisting attractors, one-scroll and double-scroll chaotic attractors are experimentally observed.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W3097440240",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "1140860150242837214",
    "title": "The first experimental evidence of chaos from a nonlinear circuit with a real memristor",
    "authors": [
      "C Volos",
      "H Nistazakis",
      "VT Pham"
    ],
    "first_author_last": "Volos",
    "year": 2020,
    "venue": "9th International …",
    "link": "https://ieeexplore.ieee.org/abstract/document/9200269/",
    "doi": "10.1109/mocast49295.2020.9200269",
    "cited_by": 10,
    "snippet": "… the nonlinear element is a real memristor. To the best of our knowledge, this is the first nonlinear circuit with a commercially available memristor (KNOWM memristor), which has been …",
    "pdf_url": "http://www.ids.uni-bremen.de/conf/mocast2020/papers/MOCAST_2020_paper_75.pdf",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "In this work, chaos is experimentally observed from a circuit, in which the nonlinear element is a real memristor. To the best of our knowledge, this is the first nonlinear circuit with a commercially available memristor (KNOWM memristor), which has been implemented in order to experimentally investigate chaos and phenomena related with it, such as a route to chaos via period-doubling, one-scroll and the well-known double-scroll chaotic attractors.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W3088556682",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "15488650972845289737",
    "title": "The Effects of Conductance on Metastable Switches in Memristive Devices Based on Anti-Hebbian and Hebbian (AHaH) Learning Rules",
    "authors": [
      "AD Abbood",
      "AA Hasan",
      "BA Attea"
    ],
    "first_author_last": "Abbood",
    "year": 2021,
    "venue": "Iraqi Journal of Science",
    "link": "https://www.ijs.uobaghdad.edu.iq/index.php/eijs/article/view/3713",
    "doi": "10.24996/ijs.2021.62.10.31",
    "cited_by": 1,
    "snippet": "… the changes in memristance of the memristors. This research will concentrate on … memristors. A single synapse is presented by a couple of memristors to mimic its resistance switching. …",
    "pdf_url": "https://www.ijs.uobaghdad.edu.iq/index.php/eijs/article/download/3713/1697",
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": true,
    "devices": [],
    "abstract": "In the last few years, the literature conferred a great interest in studying the feasibility of using memristive devices for computing. Memristive devices are important in structure, dynamics, as well as functionalities of artificial neural networks (ANNs) because of their resemblance to biological learning in synapses and neurons regarding switching characteristics of their resistance. Memristive architecture consists of a number of metastable switches (MSSs). Although the literature covered a variety of memristive applications for general purpose computations, the effect of low or high conductance of each MSS was unclear. This paper focuses on finding a potential criterion to calculate the conductance of each MMS rather than the whole conductance as reported in the literature. Anti-Hebbian and Hebbian (AHaH) learning rules are used to mimic the changes in memristance of the memristors. This research will concentrate on the effect of conductance on an individual MSS to simulate the nanotechnology devices of the memristors. A single synapse is presented by a couple of memristors to mimic its resistance switching. The learning circuit of artificial synapses could be used in many applications, such as image processing and neural networks, for pattern classification of synapses, represented by a map of the memeristors. These synapses are essential elements for data processing and information storage in both real and artificial neural systems.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://ijs.uobaghdad.edu.iq/index.php/eijs/article/download/3713/1697",
    "openalex_id": "https://openalex.org/W3209403309",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-model",
    "knowm_role": "uses-model"
  },
  {
    "cluster_id": "9144698537029791173",
    "title": "Memristor-based design solutions for mitigating parametric variations in IoT applications",
    "authors": [
      "T Bunnam"
    ],
    "first_author_last": "Bunnam",
    "year": 2021,
    "venue": "",
    "link": "http://theses.ncl.ac.uk/jspui/handle/10443/5398",
    "doi": null,
    "cited_by": 2,
    "snippet": "… -based delay element (MemDE), we applied a memristor between two inverters to vary the … Knowm Inc. for providing me with useful information regarding silver-chalcogenide memristors…",
    "pdf_url": "http://theses.ncl.ac.uk/jspui/bitstream/10443/5398/1/Bunnam%20T%202021.pdf",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": null,
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "16114442521781947751",
    "title": "Spreading operation frequency ranges of memristor emulators via a new sine-based method",
    "authors": [
      "H Cao",
      "F Wang"
    ],
    "first_author_last": "Cao",
    "year": 2021,
    "venue": "IEEE Transactions on Very Large Scale Integration (VLSI) Systems",
    "link": "https://ieeexplore.ieee.org/abstract/document/9354229/",
    "doi": "10.1109/tvlsi.2021.3056472",
    "cited_by": 20,
    "snippet": "… Nevertheless, there are few physical memristors that can be used as commercial components so far. In [17], the Knowm memristor was realized as a commercial component, but it is …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "The operation frequency of memristor seriously affects its applications in high-frequency working conditions. In this article, a new method using a sine-based function instead of the linear term in memristor models to spread the operation frequency ranges of memristor emulators is proposed. Via using this method on a flux-controlled memristor with smooth continuous cubic function as an example, research shows that the operation frequency range of this improved flux-controlled memristor is spread greatly. In particular, the improved memristor can still display an excellent pinched hysteresis loop even when the operation frequency is up to a few gigahertz, which is higher than most of the previously reported memristor emulators. The typical dynamic characteristics and the operation frequency range of the improved memristor are studied theoretically and numerically. The circuit simulations and physical experiments agree well with the theoretical analyses, which together demonstrate the effectiveness of the proposed methodology. Then, the improved memristor is applied to realize a chaotic oscillator to show its practical applications. In addition, the new method has universality, and it can be used by many other existing memristor emulators for spreading their operation frequency ranges.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W3130581373",
    "relevance": "excluded",
    "review_screen": "likely-cite-only",
    "review_reason": "cite/other-device cues: emulator, simulation",
    "pdf_knowm": null,
    "knowm_role": null,
    "human_verdict": "not-knowm",
    "human_reason": "NO (user)"
  },
  {
    "cluster_id": "1741554997539031462",
    "title": "Pinched hysteresis loops in non‐linear resonators",
    "authors": [
      "AS Elwakil",
      "ME Fouda",
      "S Majzoub"
    ],
    "first_author_last": "Elwakil",
    "year": 2020,
    "venue": "IET Circuits Devices & Systems",
    "link": "https://ietresearch.onlinelibrary.wiley.com/doi/abs/10.1049/cds2.12003",
    "doi": "10.1049/cds2.12003",
    "cited_by": 7,
    "snippet": "… resonator described above and (ii) from a KNOWM commercial memristor device using their discovery kit [30]. The gates are built using two memristor devices, as shown in Figure 8, …",
    "pdf_url": "https://ietresearch.onlinelibrary.wiley.com/doi/pdf/10.1049/cds2.12003",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "Abstract This study shows that pinched hysteresis can be observed in simple non‐linear resonance circuits containing a single diode that behaves as a voltage‐controlled switch. Mathematical models are derived and numerically validated for both series and parallel resonator circuits. The lobe area of the pinched loop is found to increase with increased frequency and multiple pinch points are possible with an odd‐symmetrical non‐linearity such as a cubic non‐linearity. Experiments have been performed to prove the existence of pinched hysteresis with a single diode and with two anti‐parallel diodes. The formation of a pinched loop in these circuits confirms the following: (1) pinched hysteresis is not a fingerprint of memristors, and (2) the existence of a non‐linearity is essential for generating this behaviour. Finally, an application in a digital logic circuit is validated.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://ietresearch.onlinelibrary.wiley.com/doi/pdfdirect/10.1049/cds2.12003",
    "openalex_id": "https://openalex.org/W3118199233",
    "relevance": "excluded",
    "review_screen": "likely-cite-only",
    "review_reason": "cite/other-device cues: mathematical model",
    "pdf_knowm": null,
    "knowm_role": null,
    "human_verdict": "not-knowm",
    "human_reason": "NO (user)"
  },
  {
    "cluster_id": "6C-EyKM4j2AJ",
    "title": "Modeling of Memristors under Periodic Signals of Different Parameters. Energies 2021, 14, 7264",
    "authors": [
      "B Garda"
    ],
    "first_author_last": "Garda",
    "year": 2021,
    "venue": "Energies",
    "link": "https://pdfs.semanticscholar.org/c655/7e1eaa7d3f446b6cf9a360dc96a084679290.pdf",
    "doi": "10.3390/en14217264",
    "cited_by": 9,
    "snippet": "… memristors in ferroelectric tunnel barriers [13]. In this paper, the investigated elements are the self-directed channel (… device is made of chalcogenide material Ge2Se3/SnSe/Ag. Unlike …",
    "pdf_url": "https://pdfs.semanticscholar.org/c655/7e1eaa7d3f446b6cf9a360dc96a084679290.pdf",
    "is_knowm": false,
    "is_sdc": true,
    "is_mss": true,
    "devices": [
      "C",
      "W"
    ],
    "abstract": "In this paper, the problem of modeling memristors is studied. Two types of memristors with carbon and tungsten doping fabricated by the Knowm Inc. are tested. The memristors have been examined with either sinusoidal or triangle voltage wave periodic excitation. Some different frequencies, amplitudes and signal shapes have been applied. The collected data have been averaged and subjected to high frequency filtering. The quality of measurement data has also been discussed. The averaged measurement has been modeled using three popular memristor models: Strukov, Biolek and VTEAM. Some additional feathers to the considered models have been proposed and tested. Memristor is usually modeled by a set of algebraic-differential equations which link both electrical values (i.e., voltage and current) and the internal variable(s) responsible for the element dynamics. The interior-point with box constrains optimization method has been used to obtain the optimal parameters of the memristor model that fit best to the collected data. The results of the optimization process have been discussed and compared. The sensitivity to the different frequency range has been also examined and reviewed. Some conclusions and future work ideas have been postulated.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://www.mdpi.com/1996-1073/14/21/7264/pdf?version=1636044964",
    "openalex_id": "https://openalex.org/W3208245467",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "8081845850313508137",
    "title": "Modeling of memristors under periodic signals of different parameters",
    "authors": [
      "B Garda"
    ],
    "first_author_last": "Garda",
    "year": 2021,
    "venue": "Energies",
    "link": "https://www.mdpi.com/1996-1073/14/21/7264",
    "doi": "10.3390/en14217264",
    "cited_by": 9,
    "snippet": "… Two types of memristors with carbon and tungsten doping fabricated by the Knowm Inc. are tested. The memristors have been examined with either sinusoidal or triangle voltage wave …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [
      "C",
      "W"
    ],
    "abstract": "In this paper, the problem of modeling memristors is studied. Two types of memristors with carbon and tungsten doping fabricated by the Knowm Inc. are tested. The memristors have been examined with either sinusoidal or triangle voltage wave periodic excitation. Some different frequencies, amplitudes and signal shapes have been applied. The collected data have been averaged and subjected to high frequency filtering. The quality of measurement data has also been discussed. The averaged measurement has been modeled using three popular memristor models: Strukov, Biolek and VTEAM. Some additional feathers to the considered models have been proposed and tested. Memristor is usually modeled by a set of algebraic-differential equations which link both electrical values (i.e., voltage and current) and the internal variable(s) responsible for the element dynamics. The interior-point with box constrains optimization method has been used to obtain the optimal parameters of the memristor model that fit best to the collected data. The results of the optimization process have been discussed and compared. The sensitivity to the different frequency range has been also examined and reviewed. Some conclusions and future work ideas have been postulated.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://www.mdpi.com/1996-1073/14/21/7264/pdf?version=1636044964",
    "openalex_id": "https://openalex.org/W3208245467",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "13474172275425430408",
    "title": "How to build a memristive integrate-and-fire model for spiking neuronal signal generation",
    "authors": [
      "SM Kang",
      "D Choi",
      "JK Eshraghian"
    ],
    "first_author_last": "Kang",
    "year": 2021,
    "venue": "IEEE Transactions on Circuits and Systems I Regular Papers",
    "link": "https://ieeexplore.ieee.org/abstract/document/9618724/",
    "doi": "10.1109/tcsi.2021.3126555",
    "cited_by": 61,
    "snippet": "… Knowm memristors to demonstrate generality. Although alternative devices may be better suited for use in the MIF family of neuron models, the Knowm … used Knowm memristors with a …",
    "pdf_url": "https://ieeexplore.ieee.org/ielaam/8919/9629436/9618724-aam.pdf",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "We present and experimentally validate two minimal compact memristive models for spiking neuronal signal generation using commercially available low-cost components. The first neuron model is called the Memristive Integrate-and-Fire (MIF) model, for neuronal signaling with two voltage levels: the spike-peak, and the rest-potential. The second model MIF2 is also presented, which promotes local adaptation by accounting for a third refractory voltage level during hyperpolarization. We show both compact models are minimal in terms of the number of circuit elements and integration area. Using the MIF and MIF2 models, we postulate the design of a memristive solid-state brain with an estimation of its surface area and power consumption. Analytical projections show that a memristive solid-state brain could be realized within (i) the surface area of the median human brain, 2,400cm<sup>2</sup>, (ii) the same volume of the median human brain, and (iii) a total power budget of approximately 20 W using a 3.5 nm technology. Distinct from the past decade of memristive neuron literature, our benchmarks are attained using generic commercially available memristors that are reproducible using off-the-shelf components. We expect this work can promote more experimental demonstrations of memristive circuits that do not rely on prohibitively expensive fabrication processes.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W3213168237",
    "relevance": "excluded",
    "review_screen": "likely-use",
    "review_reason": "use cues: off-the-shelf, commercially available, experimental, experiment",
    "llm_verdict": "not-knowm",
    "llm_confidence": "medium",
    "pdf_knowm": null,
    "knowm_role": null
  },
  {
    "cluster_id": "12724917690684740155",
    "title": "Device variability analysis for memristive material implication",
    "authors": [
      "SM Laube",
      "N TaheriNejad"
    ],
    "first_author_last": "Laube",
    "year": 2021,
    "venue": "arXiv preprint arXiv:2101.07231",
    "link": "https://arxiv.org/abs/2101.07231",
    "doi": null,
    "cited_by": 5,
    "snippet": "… Rather than introducing arbitrary parameter values, we experimentally fitted [18] our VTEAM model to Knowm BS-AF-W [42] memristors we had at the time. Parameters shown in Table III…",
    "pdf_url": "https://arxiv.org/pdf/2101.07231",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": true,
    "devices": [],
    "abstract": "Currently, memristor devices suffer from variability between devices and from cycle to cycle. In this work, we study the impact of device variations on memristive Material Implication (IMPLY). New constraints for different parameters and variables are analytically derived and compared to extensive simulation results, covering single gate and 1T1R crossbar structures. We show that a static analysis based on switching conditions is not sufficient for an overall assessment of robustness against device variability. Furthermore, we outline parameter ranges within which the IMPLY gate is predicted to produce correct output values. Our study shows that threshold voltage is the most critical parameter. This work helps scientists and engineers to understand the pitfalls of designing reliable IMPLY-based calculation units better and design them with more ease. Moreover, these analyses can be used to determine whether a certain memristor technology is suitable for implementation of IMPLY-based circuits and systems.",
    "abstract_source": "arxiv",
    "oa_pdf_url": null,
    "openalex_id": null,
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "18103062478160785",
    "title": "Dynamically configurable physical unclonable function based on RRAM crossbar",
    "authors": [
      "J Li",
      "Y Cui",
      "C Gu",
      "C Wang",
      "W Liu"
    ],
    "first_author_last": "Li",
    "year": 2021,
    "venue": "IEEE/ACM International …",
    "link": "https://ieeexplore.ieee.org/abstract/document/9642245/",
    "doi": "10.1109/nanoarch53687.2021.9642245",
    "cited_by": 5,
    "snippet": "… , the true randomness of the proposed PUF using self-directed channel (SDC) RRAMs is validated, … [14] KA Campbell, “Self-directed channel memristor for high temperature operation,” …",
    "pdf_url": "https://pure.qub.ac.uk/files/251017077/NANOARCH_2021_paper_23.pdf",
    "is_knowm": false,
    "is_sdc": true,
    "is_mss": false,
    "devices": [],
    "abstract": "Physical unclonable function (PUF) has been an effective solution for hardware security with the popularity of the internet of things (IoT). Due to low power consumption and high area efficiency, an emerging nonvolatile memory, resistive random access memory (RRAM) based PUF designs have attracted many attentions. Due to the bottleneck in the existing RRAM PUFs that it can not be fully compatible with the memory architecture, a dynamically configurable PUF based on the mainstream RRAM crossbar is proposed in this paper. Utilizing the device-to-device variation of the RRAM resistance, abundant challenge-response pairs (CRPs) are generated with a flexible configuration of an RRAM crossbar. Furthermore, different from the existing RRAM-based PUF designs, the proposed RRAM PUF can be dynamically configured between a memory cell and a PUF cell, without requiring additional sense circuits, leading to a minimal design overhead. The simulation results show that the proposed PUF exhibits good performance with a high uniqueness and reliability. Moreover, it achieves a great resistance against machine learning (ML) attack.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://pureadmin.qub.ac.uk/ws/files/251017077/NANOARCH_2021_paper_23.pdf",
    "openalex_id": "https://openalex.org/W3205376211",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "llm_verdict": "not-knowm",
    "llm_confidence": "high",
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "17504181576782640573",
    "title": "Comparative analysis of memristor devices as neuron.",
    "authors": [
      "R Manu",
      "MR Ahmed"
    ],
    "first_author_last": "Manu",
    "year": 2021,
    "venue": "",
    "link": "https://www.researchgate.net/profile/Mohammed-Riyaz-Ahmed/publication/357671489_Comparative_analysis_of_memristor_devices_as_neuron/links/61d92466d45006081696cb7e/Comparative-analysis-of-memristor-devices-as-neuron.pdf",
    "doi": null,
    "cited_by": 1,
    "snippet": "… various organizations like HP, Intel, Knowm, Rain Neuromorphic, and a programable memristor computer reported by Wei D. Lu [60]. Memristor fabrication based on various printing …",
    "pdf_url": "https://www.researchgate.net/profile/Mohammed-Riyaz-Ahmed/publication/357671489_Comparative_analysis_of_memristor_devices_as_neuron/links/61d92466d45006081696cb7e/Comparative-analysis-of-memristor-devices-as-neuron.pdf",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": null,
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "uses-knowm-device",
    "human_verdict": "uses-knowm-device",
    "human_reason": "YES (user): cites Knowm BS-AF-W and M+SDC Cr I–V curves"
  },
  {
    "cluster_id": "lI_IW5juUMIJ",
    "title": "Memristors as Candidates for Replacing Digital Potentiometers in Electric Circuits. Electronics 2021, 10, 181",
    "authors": [
      "I Markovic",
      "M Potrebic",
      "D Tošic"
    ],
    "first_author_last": "Markovic",
    "year": 2021,
    "venue": "Electronics",
    "link": "https://search.proquest.com/openview/e7f4948632a10c1bb624e31b4d4041be/1?pq-origsite=gscholar&cbl=2032404",
    "doi": "10.3390/electronics10020181",
    "cited_by": 8,
    "snippet": "… encapsulated edge board is placed in a PCI-E 36 breakout board [31]. The KnowM memristor is … In this research, the KnowM memristor and AD2750 Analog Design potentiometer have …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "Digital potentiometers are substantial components for the design of many mixed-signal electronic circuits and systems. Their capability to program resistance value almost instantly provides hardware designers an additional level of freedom. Unfortunately, this feature is limited to DC and lower frequencies, due to parasitic effects. Nowadays, memristors as continuously tunable resistors are becoming candidates for potentiometer successors. Memristors are two-terminal non-volatile devices which have less significant parasitic effects and a wide resistance range. The memristance value can be changed on the fly. Using nanotechnology, memristor implementation has a nanoscale footprint with nanosecond transition between resistive states. In this paper, we present a comparison between the frequency characteristics of digital potentiometers and the only commercially available memristors. Memristor parasitic effects dominate at higher frequencies which extends the bandwidth. In order to present the advantages of memristive circuits, we have analyzed and implemented tunable circuits such as a voltage divider, an inverting amplifier, a high-pass filter, and a phase shifter. A commercially available memristor by KnowM Inc. is used for this purpose. Experimental results obtained by the measurements verify that a memristor has equal or better characteristics than a digital potentiometer. Memristive realizations of voltage dividers and inverting amplifiers have a wider bandwidth, while filters and phase shifters with a memristor have almost identical frequency characteristics as the corresponding realizations with a digital potentiometer.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://www.mdpi.com/2079-9292/10/2/181/pdf",
    "openalex_id": "https://openalex.org/W3120120531",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "named-in-abstract"
  },
  {
    "cluster_id": "13732161367476761381",
    "title": "Memristors as candidates for replacing digital potentiometers in electric circuits",
    "authors": [
      "I Marković",
      "M Potrebić",
      "D Tošić"
    ],
    "first_author_last": "Marković",
    "year": 2021,
    "venue": "Electronics",
    "link": "https://www.mdpi.com/2079-9292/10/2/181",
    "doi": "10.3390/electronics10020181",
    "cited_by": 8,
    "snippet": "… In this research, the KnowM memristor and AD2750 Analog Design potentiometer have been compared, whereas Table 1 presents a summary view of this comparison. …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "Digital potentiometers are substantial components for the design of many mixed-signal electronic circuits and systems. Their capability to program resistance value almost instantly provides hardware designers an additional level of freedom. Unfortunately, this feature is limited to DC and lower frequencies, due to parasitic effects. Nowadays, memristors as continuously tunable resistors are becoming candidates for potentiometer successors. Memristors are two-terminal non-volatile devices which have less significant parasitic effects and a wide resistance range. The memristance value can be changed on the fly. Using nanotechnology, memristor implementation has a nanoscale footprint with nanosecond transition between resistive states. In this paper, we present a comparison between the frequency characteristics of digital potentiometers and the only commercially available memristors. Memristor parasitic effects dominate at higher frequencies which extends the bandwidth. In order to present the advantages of memristive circuits, we have analyzed and implemented tunable circuits such as a voltage divider, an inverting amplifier, a high-pass filter, and a phase shifter. A commercially available memristor by KnowM Inc. is used for this purpose. Experimental results obtained by the measurements verify that a memristor has equal or better characteristics than a digital potentiometer. Memristive realizations of voltage dividers and inverting amplifiers have a wider bandwidth, while filters and phase shifters with a memristor have almost identical frequency characteristics as the corresponding realizations with a digital potentiometer.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://www.mdpi.com/2079-9292/10/2/181/pdf",
    "openalex_id": "https://openalex.org/W3120120531",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "named-in-abstract"
  },
  {
    "cluster_id": "nsqIihR8DnoJ",
    "title": "Chaotic circuit based on physical memristor",
    "authors": [
      "L Minati",
      "LV Gambuzza",
      "WJ Thio"
    ],
    "first_author_last": "Minati",
    "year": 2021,
    "venue": "… Networks and their …",
    "link": "https://ieeexplore.ieee.org/abstract/document/9610781/",
    "doi": null,
    "cited_by": 0,
    "snippet": "… The top-left op-amp circuit containing the memristor M replaces the diode of the original … The memristors we have used are discrete devices, produced by Knowm Inc. (Santa Fe NM, …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [
      "C",
      "W"
    ],
    "abstract": "In this paper, we briefly discuss the main features of the memristor-based autonomous oscillator introduced and extensively characterized in [1]. The circuit is based on two feedback loops, a linear one and a non-linear one involving a self-directed channel memristor. In particular, we consider two different types of devices, one tungsten-based and one carbon-based, and show experimental results proving that chaos can be readily obtained in both cases, despite the device non-idealities.",
    "abstract_source": "ieee-xplore",
    "oa_pdf_url": null,
    "openalex_id": null,
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "named-in-abstract"
  },
  {
    "cluster_id": "16240694440103538872",
    "title": "Structural and parametric identification of knowm memristors",
    "authors": [
      "V Ostrovskii",
      "P Fedoseev",
      "Y Bobrova",
      "D Butusov"
    ],
    "first_author_last": "Ostrovskii",
    "year": 2021,
    "venue": "Nanomaterials",
    "link": "https://www.mdpi.com/2079-4991/12/1/63",
    "doi": "10.3390/nano12010063",
    "cited_by": 55,
    "snippet": "… The suggested identification method is presented as a generalized process for a wide range of … A metastable switch memristor can be represented as a set of N switching elements with …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": true,
    "devices": [],
    "abstract": "This paper proposes a novel identification method for memristive devices using Knowm memristors as an example. The suggested identification method is presented as a generalized process for a wide range of memristive elements. An experimental setup was created to obtain a set of intrinsic I-V curves for Knowm memristors. Using the acquired measurements data and proposed identification technique, we developed a new mathematical model that considers low-current effects and cycle-to-cycle variability. The process of parametric identification for the proposed model is described. The obtained memristor model represents the switching threshold as a function of the state variables vector, making it possible to account for snapforward or snapback effects, frequency properties, and switching variability. Several tools for the visual presentation of the identification results are considered, and some limitations of the proposed model are discussed.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://www.mdpi.com/2079-4991/12/1/63/pdf?version=1640605633",
    "openalex_id": "https://openalex.org/W4200251181",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "11879356524377331394",
    "title": "Memristor based tunable negative group delay circuit",
    "authors": [
      "CL Palson",
      "RK Sreelal",
      "DD Krishna"
    ],
    "first_author_last": "Palson",
    "year": 2021,
    "venue": "… on Advances in …",
    "link": "https://ieeexplore.ieee.org/abstract/document/9708356/",
    "doi": "10.1109/icacc-202152719.2021.9708356",
    "cited_by": 0,
    "snippet": "… Thus we have used a memristor connection across a slot in the NGD circuit to change … memristor’s resistance. It has a wide resistance range of 400 Ω to 1 MΩ. One KnowM memristor …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "The rise of new generation communication systems requires high-quality signal transmission with significantly less signal distortion. Hence to ensure the quality, a tri-band Negative Group Delay Circuit (NGDC) is designed utilizing bandstop characteristics to compensate for the undesired positive group delays. In this work, L and U shaped stubs are etched on the 50 Ohm transmission line to generate NGD. Further, a memristor is connected across a slot to bring about tunability to the group delays, wherein it acts as a tunable resistance.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4213162398",
    "relevance": "excluded",
    "review_screen": "unclear",
    "review_reason": "no strong cues",
    "llm_verdict": "uncertain",
    "llm_confidence": "low",
    "pdf_knowm": null,
    "knowm_role": null,
    "human_verdict": "not-knowm",
    "human_reason": "NO (user): not sure from abstract"
  },
  {
    "cluster_id": "7498934355986402659",
    "title": "Behavioral leakage and inter-cycle variability emulator model for rerams (BELIEVER)",
    "authors": [
      "D Radakovits",
      "N Taherinejad"
    ],
    "first_author_last": "Radakovits",
    "year": 2021,
    "venue": "arXiv preprint arXiv:2103.04179",
    "link": "https://arxiv.org/abs/2103.04179",
    "doi": null,
    "cited_by": 10,
    "snippet": "… The memristors that have been studied in this work, are of the Self … a memristor model, that is well received by the memristor community to SDC memristor devices built by KNOWM Inc., …",
    "pdf_url": "https://arxiv.org/pdf/2103.04179",
    "is_knowm": true,
    "is_sdc": true,
    "is_mss": false,
    "devices": [],
    "abstract": "Emerging electronic devices are promising to drive the performance of computer systems to new heights, against the notable saturation in traditional transistor-based architectures. Among them, resistive RAM -- or ReRAM -- has attracted a lot of attention among scientists since its practical realization was reported in 2008 and numerous devices, circuits and systems, and also models have been described in the literature. However, behavioral models fail to reproduce device parameter variations and the drift of device state in the absence of a stimulus. This shortcoming substantially reduces the practical relevance of systems and circuits designed with existing models. The work at hand deals with the development of a behavioral model that integrates device parameter variation and state drift based on data collected from our measurements of real devices. As we show in this paper, BELIEVER model enables engineers to conduct more reliable and meaningful design and simulations of circuits and systems that use ReRAMs.",
    "abstract_source": "arxiv",
    "oa_pdf_url": null,
    "openalex_id": null,
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "9668492142673282378",
    "title": "Hybrid memristor-CMOS implementation of logic gates design using LTSpice",
    "authors": [
      "WMHWM Sharif",
      "MFM Idros",
      "SAM Al-Junid"
    ],
    "first_author_last": "Sharif",
    "year": 2021,
    "venue": "International Journal of Power Electronics and Drive Systems/International Journal of Electrical and Computer Engineering",
    "link": "https://www.academia.edu/download/67424103/18_22910_ED_6oct_14apr_Y.pdf",
    "doi": "10.11591/ijece.v11i3.pp2003-2010",
    "cited_by": 3,
    "snippet": "… All of the simulations in this work are done using the generalized metastable switch memristor (MSS) model proposed by Knowm Inc. [19]. The MSS model is capable of modeling the …",
    "pdf_url": "https://www.academia.edu/download/67424103/18_22910_ED_6oct_14apr_Y.pdf",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": true,
    "devices": [],
    "abstract": "In this paper, a hybrid memristor-CMOS implementation of logic gates simulated using LTSpice. Memristors' implementation in computer architecture designs explored in various design structures proposed by researchers from all around the world. However, all prior designs have some drawbacks in terms of applicability, scalability, and performance. In this research, logic gates design based on the hybrid memristor-CMOS structure presented. 2-inputs AND, OR, NAND, NOR, XOR, and XNOR are demonstrated with minimum components requirements. In addition, a 1-bit full adder circuit with high performance and low area consumption is also proposed. The proposed full adder only consists of 4 memristors and 7 CMOS transistors. Half design of the adder base on the memristor component created. Through analysis and simulations, the memristor implementation on designing logic gates using memristor-CMOS structure demonstrated using the generalized metastable switch memristor (MSS) model and LTSpice. In conclusion, the proposed approach improves speed and require less area.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://ijece.iaescore.com/index.php/IJECE/article/download/22910/14746",
    "openalex_id": "https://openalex.org/W3124395761",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-model",
    "knowm_role": "uses-model"
  },
  {
    "cluster_id": "_bA762b2-vIJ",
    "title": "Hybrid memristor-CMOS implementation of logic gates design using LTSpice.",
    "authors": [
      "WM Hashimi Wan Mohamad Sharif"
    ],
    "first_author_last": "Sharif",
    "year": 2021,
    "venue": "International Journal of Power Electronics and Drive Systems/International Journal of Electrical and Computer Engineering",
    "link": "https://search.ebscohost.com/login.aspx?direct=true&profile=ehost&scope=site&authtype=crawler&jrnl=20888708&AN=148685263&h=W7GHuOZU4oDChMS7OWMe55Rml3lf01TbAGfodGAwRN0wWsWj%2BUoV5GXF1ZQoeDt6Gy728JpZNbo4n2AwqMmH1A%3D%3D&crl=c",
    "doi": "10.11591/ijece.v11i3.pp2003-2010",
    "cited_by": 3,
    "snippet": "… All of the simulations in this work are done using the generalized metastable switch memristor (MSS) model proposed by Knowm Inc. [19]. The MSS model is capable of modeling the …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": true,
    "devices": [],
    "abstract": "In this paper, a hybrid memristor-CMOS implementation of logic gates simulated using LTSpice. Memristors' implementation in computer architecture designs explored in various design structures proposed by researchers from all around the world. However, all prior designs have some drawbacks in terms of applicability, scalability, and performance. In this research, logic gates design based on the hybrid memristor-CMOS structure presented. 2-inputs AND, OR, NAND, NOR, XOR, and XNOR are demonstrated with minimum components requirements. In addition, a 1-bit full adder circuit with high performance and low area consumption is also proposed. The proposed full adder only consists of 4 memristors and 7 CMOS transistors. Half design of the adder base on the memristor component created. Through analysis and simulations, the memristor implementation on designing logic gates using memristor-CMOS structure demonstrated using the generalized metastable switch memristor (MSS) model and LTSpice. In conclusion, the proposed approach improves speed and require less area.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://ijece.iaescore.com/index.php/IJECE/article/download/22910/14746",
    "openalex_id": "https://openalex.org/W3124395761",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-model",
    "knowm_role": "uses-model"
  },
  {
    "cluster_id": "326470076261270761",
    "title": "History erase effect of real memristors",
    "authors": [
      "Y Shen",
      "G Wang"
    ],
    "first_author_last": "Shen",
    "year": 2021,
    "venue": "Electronics",
    "link": "https://www.mdpi.com/2079-9292/10/3/303",
    "doi": "10.3390/electronics10030303",
    "cited_by": 4,
    "snippet": "… studies the history erase effect of two practical memristor devices, namely the HP TiO 2 memristor and the Knowm self-aligning channel memristor. The authors found that the HP TiO 2 …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "Different from the static (power-off) nonvolatile property of a memristor, the history erase effect of a memristor is a dynamic characteristic, which means that under the excitation of switching or different signals, the memristor can forget its initial value and reach a unique stable state. The stable state is determined only by the excitation signal and has nothing to do with its initial state. The history erase effect is a desired effect in memristor applications such as memory. It can simplify the complexity of the writing circuit and improve the storage speed. If the memristor’s response depends on the initial state, a state reset operation is required before each writing operation. Therefore, it is of great theoretical and practical significance to judge whether the memristor has a history erase effect. Based on the study of the history erase effect of real memristors, this paper focuses on the history erase effect of a Hewlett-Packard (HP) TiO2 memristor and the Self-Directed Channel (SDC) memristor of Knowm Company. The DC and AC responses of the HP TiO2 memristor are given, and it is pointed out that there is no AC history erase effect. However, considering the parasitic memcapacitance effect, it is found that it has the effect. Based on the theoretical model of the SDC memristor, its history erase properties with and without considering parasitic effects are studied. It should be noted that this study method can be useful for other materials such as Al2O3 and MoS2.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://www.mdpi.com/2079-9292/10/3/303/pdf?version=1611752569",
    "openalex_id": "https://openalex.org/W3125729002",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "named-in-abstract"
  },
  {
    "cluster_id": "UYczTJOjpE4J",
    "title": "History Erase Effect of Real Memristors. Electronics 2021, 10, 303",
    "authors": [
      "Y Shen",
      "G Wang"
    ],
    "first_author_last": "Shen",
    "year": 2021,
    "venue": "Electronics",
    "link": "https://search.proquest.com/openview/1a6f357692655d010e808a371c14efc0/1?pq-origsite=gscholar&cbl=2032404",
    "doi": "10.3390/electronics10030303",
    "cited_by": 4,
    "snippet": "… studies the history erase effect of two practical memristor devices, namely the HP TiO2 memristor and the Knowm self-aligning channel memristor. The authors found that the HP TiO2 …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "Different from the static (power-off) nonvolatile property of a memristor, the history erase effect of a memristor is a dynamic characteristic, which means that under the excitation of switching or different signals, the memristor can forget its initial value and reach a unique stable state. The stable state is determined only by the excitation signal and has nothing to do with its initial state. The history erase effect is a desired effect in memristor applications such as memory. It can simplify the complexity of the writing circuit and improve the storage speed. If the memristor’s response depends on the initial state, a state reset operation is required before each writing operation. Therefore, it is of great theoretical and practical significance to judge whether the memristor has a history erase effect. Based on the study of the history erase effect of real memristors, this paper focuses on the history erase effect of a Hewlett-Packard (HP) TiO2 memristor and the Self-Directed Channel (SDC) memristor of Knowm Company. The DC and AC responses of the HP TiO2 memristor are given, and it is pointed out that there is no AC history erase effect. However, considering the parasitic memcapacitance effect, it is found that it has the effect. Based on the theoretical model of the SDC memristor, its history erase properties with and without considering parasitic effects are studied. It should be noted that this study method can be useful for other materials such as Al2O3 and MoS2.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://www.mdpi.com/2079-9292/10/3/303/pdf?version=1611752569",
    "openalex_id": "https://openalex.org/W3125729002",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "named-in-abstract"
  },
  {
    "cluster_id": "13861930262071260293",
    "title": "Demonstration of three true random number generator circuits using memristor created entropy and commercial off-the-shelf components",
    "authors": [
      "S Stoller",
      "KA Campbell"
    ],
    "first_author_last": "Stoller",
    "year": 2021,
    "venue": "Entropy",
    "link": "https://www.mdpi.com/1099-4300/23/3/371",
    "doi": "10.3390/e23030371",
    "cited_by": 15,
    "snippet": "… are licensed to Knowm, Inc. by Boise State University. KC is the patent inventor and may potentially receive royalties from Boise State University through memristor sales by Knowm, Inc. …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "In this work, we build and test three memristor-based true random number generator (TRNG) circuits: two previously presented in the literature and one which is our own design. The functionality of each circuit is assessed using the National Institute of Standards and Technology (NIST) Statistical Test Suite (STS). The TRNG circuits were built using commercially available off-the-shelf parts, including the memristor. The results of this work confirm the usefulness of memristors for successful implementation of TRNG circuits, as well as the ease with which a TRNG can be built using simple circuit designs and off-the-shelf breadboard circuit components.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://www.mdpi.com/1099-4300/23/3/371/pdf?version=1616555364",
    "openalex_id": "https://openalex.org/W3137054824",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "llm_verdict": "uses-knowm-device",
    "llm_confidence": "medium",
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "17329788795206890631",
    "title": "SIXOR: Single-cycle in-memristor XOR",
    "authors": [
      "N TaheriNejad"
    ],
    "first_author_last": "TaheriNejad",
    "year": 2021,
    "venue": "IEEE Transactions on Very Large Scale Integration (VLSI) Systems",
    "link": "https://ieeexplore.ieee.org/abstract/document/9382267/",
    "doi": "10.1109/tvlsi.2021.3062293",
    "cited_by": 42,
    "snippet": "… Model settings are shown in Table II (fitted to our measurements [8] of Knowm “BS-AF-W” discrete memristors [40]). In these simulations, Vsupply = Vx = 1.3v and tpulse = 2 μs. …",
    "pdf_url": "https://eclectx.org/Publications/2021_SIXOR_TVLSI.pdf",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": true,
    "devices": [],
    "abstract": "With the fast approach of the end of silicon scaling and existing problems, such as the Von-Neumann bottleneck, alternative computing paradigms are in demand. In-memory computation (IMC) is one of the most promising solutions, and memristive technology is one of the best platforms for that purpose. Many logic families have been proposed to enable memristive IMC, among which stateful logic family stands out due to its minimal power consumption and simplicity. In this work, to complement existing works, we propose the first stateful crossbar-compatible XOR atomic logic operation that requires only one cycle for its completion, which is two times faster than the current minimum required time for performing XOR (which is two cycles) using other atomic operations in comparable memristive stateful logic families. We show that, in an example case of an adder, by taking advantage of the proposed single-cycle in-memristor XOR (SIXOR), up to 4.5× speedup can be achieved compared to other SoA stateful adders. The gained speed-up scales up in more complex systems and calculations that use XOR.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W3136861880",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "llm_verdict": "not-knowm",
    "llm_confidence": "high",
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "6014603571954765916",
    "title": "FPGA synthesis of ternary memristor-CMOS decoders",
    "authors": [
      "X Wang",
      "Z Wu",
      "P Zhou",
      "HHC Iu",
      "JK Eshraghian"
    ],
    "first_author_last": "Wang",
    "year": 2022,
    "venue": "IEEE Transactions on Circuits and Systems I Regular Papers",
    "link": "https://arxiv.org/abs/2104.10297",
    "doi": "10.1109/tcsi.2022.3141087",
    "cited_by": 14,
    "snippet": "… 2(b) using Knowm’s memristor model [35] using the parameters in Table II. The transistor SPICE models (Level 54 BSIM4) are based on a 50nm process where VDD=1 V. The results …",
    "pdf_url": "https://arxiv.org/pdf/2104.10297",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "The search for a compatible application of memristor-CMOS logic gates has remained elusive, as the data density benefits are offset by slow switching speeds and resistive dissipation. Active microdisplays typically prioritize pixel density (and therefore resolution) over that of speed, where the most widely used refresh rates fall between 25–240 Hz. Therefore, memristor-CMOS logic is a promising fit for peripheral I/O logic in active matrix displays. In this paper, we design and implement a ternary 1–3 line decoder and a ternary 2–9 line decoder which are used to program a seven segment LED display. SPICE simulations are conducted in a 50-nm process, and the decoders are synthesized on an Altera Cyclone IV field-programmable gate array (FPGA) development board which implements a ternary memristor model designed in Quartus II. Our approach to logic synthesis demonstrates a potential way forward for simulating large-scale memristor-CMOS circuits without embedded RRAM for functional verification, and our SPICE results show an improvement in data density of a variety of decoders by a factor between 3.6-8.5. While the switching speed of memristors are one of several bottlenecks to using them in combinational logic, the comparatively slow refresh rates of typical microdisplays indicate this to be a tolerable trade-off, which promotes data density over speed.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4205281504",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-model",
    "knowm_role": "uses-model"
  },
  {
    "cluster_id": "14168704574088223408",
    "title": "On Memristor Modeling for a VGA Application",
    "authors": [
      "T Wey",
      "E Crippen"
    ],
    "first_author_last": "Wey",
    "year": 2021,
    "venue": "IEEE International Midwest …",
    "link": "https://ieeexplore.ieee.org/abstract/document/9531716/",
    "doi": "10.1109/mwscas47672.2021.9531716",
    "cited_by": 0,
    "snippet": "… memristor emulators [13]. More recently, SDC memristor devices have been made available by Knowm, Inc. [… In this work, a CR-type SDC memristor from Knowm Inc. is studied in a VGA …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": true,
    "is_mss": false,
    "devices": [],
    "abstract": "A variable gain amplifier application featuring a physical memristor available from Knowm Inc. is considered. A hardware prototype of the amplifier is built and variable gain programming response verified. An in situ current-voltage characterization of the device is performed, and a SPICE circuit model for the memristor is extracted and implemented for LTSpice simulations. Simulation results show good agreement with measured variable gain amplifier responses of the experimental hardware. The proposed memristor characterization method and SPICE modeling technique provide a useful approach for further simulation evaluation of application specific analog memristor circuits such as a variable gain amplifier.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W3199010280",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "named-in-abstract"
  },
  {
    "cluster_id": "4826128871665352160",
    "title": "A practical implementation of the ternary logic using memristors and MOSFETs",
    "authors": [
      "J Yang",
      "H Lee",
      "JH Jeong",
      "TH Kim"
    ],
    "first_author_last": "Yang",
    "year": 2021,
    "venue": "IEEE 51st …",
    "link": "https://ieeexplore.ieee.org/abstract/document/9459666/",
    "doi": "10.1109/ismvl51352.2021.00039",
    "cited_by": 16,
    "snippet": "… memristors and MOSFETs. We present how a general ternary logic is implemented in memristor… We use Knowm’s memristor model [14] in Verilog-A, which is the same model used in [8], …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "Due to the impotent forecasts of binary systems, ternary systems are regaining attention. Among many ternary devices, a passive device called memristor that is based on resistance switching is considered a good candidate when integrated with MOSFETs. Therefore, in this paper, we design ternary logic based on memristors and MOSFETs. We highlight the design issues that should be resolved (e.g., signal distortion and high static current) and present practical solutions. To the best of the authors' knowledge, we present 15 novel ternary logic cells and circuitry that include the design of the first balanced ternary full adder (TFA). By our TFA, we visualize that it is possible to design the most practical ternary circuits using memristors and MOSFETs. Our TFA uses 97 transistors and 87 memristors, which is the most reasonable TFA design that has the highest potential to be implemented in the near future.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W3177093730",
    "relevance": "excluded",
    "review_screen": "unclear",
    "review_reason": "no strong cues",
    "llm_verdict": "not-knowm",
    "llm_confidence": "medium",
    "pdf_knowm": null,
    "knowm_role": null
  },
  {
    "cluster_id": "9290252619166628850",
    "title": "Temperature-frequency study of germanium selenide memristors with a self-directed current-conducting channel",
    "authors": [
      "AN Aleshin",
      "OA Ruban"
    ],
    "first_author_last": "Aleshin",
    "year": 2022,
    "venue": "Russian Microelectronics",
    "link": "https://link.springer.com/article/10.1134/S1063739722020020",
    "doi": "10.1134/S1063739722020020",
    "cited_by": 3,
    "snippet": "… The SDC-memristors studied in this paper were purchased from Knowm In (United States). The memristors were studied on an automated measuring stand created at the Institute of …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "Abstract The experimental data on the measurement of resistance and electrical conductivity in a low-resistance mode of operation of a memristor based on germanium selenide with a self-directed conductive channel in the range of switching frequencies and temperatures are presented. In the frequency experiment, the switching frequency effect is conducted at room temperature in the range of 1 to 10 000 Hz. An experiment to study the effect of temperature on resistance and electrical conductivity is carried out in the temperature range –10–65°C at a switching frequency of 10 Hz. The aim of this study is to determine the activation energy of the formation of a conductive channel. It is shown that in the temperature range 22–65°C electrical conductivity obeys the Arrhenius law with an activation energy of 0.19 eV; at temperatures below room temperature, the electrical conductivity is insensitive to temperature changes. The reasons for the low value of the activation energy are discussed.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4220982140",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "llm_verdict": "uses-knowm-device",
    "llm_confidence": "high",
    "pdf_knowm": null,
    "knowm_role": "named-in-abstract"
  },
  {
    "cluster_id": "9219399253406336162",
    "title": "A MOS-DTMOS implementation of floating memristor emulator for high-frequency applications",
    "authors": [
      "YR Ananda",
      "N Raj",
      "G Trivedi"
    ],
    "first_author_last": "Ananda",
    "year": 2022,
    "venue": "IEEE Transactions on Very Large Scale Integration (VLSI) Systems",
    "link": "https://ieeexplore.ieee.org/abstract/document/9983991/",
    "doi": "10.1109/tvlsi.2022.3227201",
    "cited_by": 26,
    "snippet": "… As we know, solid-state memristors are commercialized by KNOWM [… memristor emulator is validated by implementing memristor-based applications. Note that the proposed memristor …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "The work presented in this article focuses on designing a floating MOS-dynamic threshold voltage MOSFET (DTMOS)-based circuit to emulate a memristor. The proposed circuit consists of four transistors, including a DT-MOSFET and an external capacitor, which helps obtain high-frequency operations up to 3 MHz. This facilitates easier integration of the devices and monolithic IC fabrication. The correctness of the proposed emulator is validated by conducting various parametric analyses at different operating frequencies and process corners, and it generates acceptable pinched hysteresis loops (PHLs) at various frequencies. Furthermore, pre- and post-layout validation of the proposed emulator are also performed using Cadence Virtuoso with Taiwan Semiconductor Manufacturing Company (TSMC) 180-nm process design kits (PDKs) to prove its effectiveness as a memristor. The area and power consumption of the proposed emulator are <inline-formula xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\"> <tex-math notation=\"LaTeX\">$157.48~\\mu \\text {m}^{2}$ </tex-math></inline-formula> and <inline-formula xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\"> <tex-math notation=\"LaTeX\">$8.24~\\mu \\text {W}$ </tex-math></inline-formula> , respectively. The physical experiment of the proposed memristor emulator is performed using ALD <inline-formula xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\"> <tex-math notation=\"LaTeX\">$1106~n$ </tex-math></inline-formula> -channel MOSFETs to characterize its functionality as a real-life memristor. It is also used in designing a memristor-based application to showcase its applicability in power and area optimal circuit design.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4312321320",
    "relevance": "excluded",
    "review_screen": "likely-cite-only",
    "review_reason": "cite/other-device cues: emulator, proposed memristor",
    "pdf_knowm": null,
    "knowm_role": null,
    "human_verdict": "not-knowm",
    "human_reason": "NO (user)"
  },
  {
    "cluster_id": "Jb9Orq14raAJ",
    "title": "Learning about nanodevices using experimental characterization equipment",
    "authors": [
      "LA Camuñas-Mesa"
    ],
    "first_author_last": "Camuñas-Mesa",
    "year": 2022,
    "venue": "2022 Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica (XV Technologies Applied to Electronics Teaching Conference)",
    "link": "https://ieeexplore.ieee.org/abstract/document/9840704/",
    "doi": "10.1109/taee54169.2022.9840704",
    "cited_by": 0,
    "snippet": "… is the Self Directed Channel (SDC) memristor developed by … and pushes them into the active Ge2Se3 layer, which facilitates the … The self-directed channel is a result of the natural glass …",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": true,
    "is_mss": true,
    "devices": [],
    "abstract": "Learning about emerging nanodevices for university students is usually limited to theoretical descriptions, given the lack of availability of such devices and appropriate test equipment in standard electronics labs. However, the possibil-ity to develop some practical work is crucial to improve the understanding of theoretical concepts. In the framework of the ‘Nanomaterials and nanotechnology’ course (4th year of the Degree on Materials Engineering), this paper presents some practical experiments to test and characterize memristive devices using an affordable lab setup with commercial equipment.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4292074838",
    "relevance": "excluded",
    "review_screen": "unclear",
    "review_reason": "weak use cues: experiment, characteriz",
    "llm_verdict": "uncertain",
    "llm_confidence": "low",
    "pdf_knowm": null,
    "knowm_role": null,
    "human_verdict": "not-knowm",
    "human_reason": "NO (user): not sure from abstract"
  },
  {
    "cluster_id": "15071894132443917661",
    "title": "Stochastic resonance exploration in current-driven reram devices",
    "authors": [
      "A Cirera",
      "I Vourkas",
      "A Rubio"
    ],
    "first_author_last": "Cirera",
    "year": 2022,
    "venue": "2022 IEEE 22nd International Conference on Nanotechnology (NANO)",
    "link": "https://ieeexplore.ieee.org/abstract/document/9928748/",
    "doi": "10.1109/nano54668.2022.9928748",
    "cited_by": 7,
    "snippet": "… set of commercially available memristors by Knowm Inc [15] … Current-based programming of memristors can be … , a set of BS-AF-W discrete SDC bipolar ReRAM devices by Knowm Inc. …",
    "pdf_url": "https://upcommons.upc.edu/bitstreams/e52b02e1-dfb8-4588-a743-b937af855cad/download",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": true,
    "devices": [],
    "abstract": "Advances in emerging resistive random-access memory (ReRAM) technology show promise for its use in future computing systems, enabling neuromorphic and memory-centric computing architectures. However, one aspect that holds back the widespread practical use of ReRAM is the behavioral variability of resistive switching devices. In this context, a radically new path towards ReRAM-based electronics concerns the exploitation of noise and the Stochastic Resonance (SR) phenomenon as a mechanism to mitigate the impact of variability. While SR has been already demonstrated in ReRAM devices and its potential impact has been analyzed for memory applications, related works have only focused on voltage input signals. In this work we present preliminary results concerning the exploration of SR in current-driven ReRAM devices, commercially available by Knowm Inc. Our results indicate that additive noise of amplitude σ = 0.125uA can stabilize the cycling performance of the devices, whereas higher noise amplitude improves the HRS-LRS resistance window, thus could affect positively the Bit Error Rate (BER) metric in ReRAM memory applications.",
    "abstract_source": "openalex",
    "oa_pdf_url": "http://hdl.handle.net/2117/381475",
    "openalex_id": "https://openalex.org/W4312375471",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "16199124578532969335",
    "title": "Exploring different circuit-level approaches to the forming of resistive random access memories",
    "authors": [
      "A Cirera",
      "C Fernandez",
      "I Vourkas"
    ],
    "first_author_last": "Cirera",
    "year": 2022,
    "venue": "11th International …",
    "link": "https://ieeexplore.ieee.org/abstract/document/9837684/",
    "doi": "10.1109/mocast54814.2022.9837684",
    "cited_by": 7,
    "snippet": "… -driven characterization strategy for memristors which practically … 16-pin ceramic DIP package by Knowm Inc., using a custom … BS-AF-W discrete SDC bipolar RS devices by Knowm Inc. …",
    "pdf_url": "http://www.ids.uni-bremen.de/conf/mocast2022/papers/91.pdf",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": true,
    "devices": [],
    "abstract": "Advances in emerging resistive random-access memory (ReRAM) technology show promise to be used in future memory-centric computing systems. In ReRAM arrays that consist of two-terminal bipolar resistive switching (RS) devices, SET/RESET programming voltage pulses are used to switch them from low resistance state (LRS) to high resistance state (HRS). The recent commercialization of discrete and crossbar-array organized RS devices have certainly pushed forward experimentation with such emerging memory technology. One barrier still preventing their widespread practical use is the behavioral variability and the lack of a straightforward manner to implement the forming process and achieve uniform SET/RESET programing. In this paper, different circuit topologies and approaches are explored to perform the forming of the conductive channel in commercial discrete RS devices by Knowm Inc. A target-resistance is pursued through pulsed voltage stress, followed by cycle-to-cycle stabilization using a custom transimpedance amplifier circuit. Moreover, a voltage controlled low–current source is proposed as an approach to alleviate the complexity and risk of the forming process in device characterization.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4288389097",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "5577082696425880968",
    "title": "A hybrid CMOS-memristor spiking neural network supporting multiple learning rules",
    "authors": [
      "D Florini",
      "D Gandolfi",
      "J Mapelli",
      "L Benatti"
    ],
    "first_author_last": "Florini",
    "year": 2022,
    "venue": "IEEE Transactions on Neural Networks and Learning Systems",
    "link": "https://ieeexplore.ieee.org/abstract/document/9889230/",
    "doi": "10.1109/tnnls.2022.3202501",
    "cited_by": 23,
    "snippet": "… -doped self-directed channel (SDC) memristors fabricated and … In SDC memristors, Ag agglomerated in a Ge2Se3 layer is … memristor is a multilayer stack composed of W/Ge2Se3/Ag/…",
    "pdf_url": "https://ieeexplore.ieee.org/iel7/5962385/6104215/09889230.pdf",
    "is_knowm": false,
    "is_sdc": true,
    "is_mss": true,
    "devices": [],
    "abstract": "Artificial intelligence (AI) is changing the way computing is performed to cope with real-world, ill-defined tasks for which traditional algorithms fail. AI requires significant memory access, thus running into the von Neumann bottleneck when implemented in standard computing platforms. In this respect, low-latency energy-efficient in-memory computing can be achieved by exploiting emerging memristive devices, given their ability to emulate synaptic plasticity, which provides a path to design large-scale brain-inspired spiking neural networks (SNNs). Several plasticity rules have been described in the brain and their coexistence in the same network largely expands the computational capabilities of a given circuit. In this work, starting from the electrical characterization and modeling of the memristor device, we propose a neuro-synaptic architecture that co-integrates in a unique platform with a single type of synaptic device to implement two distinct learning rules, namely, the spike-timing-dependent plasticity (STDP) and the Bienenstock-Cooper-Munro (BCM). This architecture, by exploiting the aforementioned learning rules, successfully addressed two different tasks of unsupervised learning.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://ieeexplore.ieee.org/ielx7/5962385/6104215/09889230.pdf",
    "openalex_id": "https://openalex.org/W4295442031",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "llm_verdict": "not-knowm",
    "llm_confidence": "medium",
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "13576388698464954138",
    "title": "Using memristor arrays as physical unclonable functions",
    "authors": [
      "F Frank",
      "T Arul",
      "NA Anagnostopoulos"
    ],
    "first_author_last": "Frank",
    "year": 2022,
    "venue": "Lecture notes in computer science",
    "link": "https://link.springer.com/chapter/10.1007/978-3-031-17143-7_13",
    "doi": "10.1007/978-3-031-17143-7_13",
    "cited_by": 6,
    "snippet": "… 3 V is applied to the memristor. For our experiments, we are using two memristor arrays of the brand Knowm, each consisting of 16 memristor cells [11]. Further information is given in . …",
    "pdf_url": "https://drive.google.com/file/d/1CPPG0cccfAfCcq8PkNKWvIaj6uVCHwFr/view",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4296831652",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "uses-knowm-device",
    "human_verdict": "uses-knowm-device",
    "human_reason": "YES (user)"
  },
  {
    "cluster_id": "12263639880997978904",
    "title": "BPSK circuit based on SDC memristor",
    "authors": [
      "R Gao",
      "Y Shen"
    ],
    "first_author_last": "Gao",
    "year": 2022,
    "venue": "Micromachines",
    "link": "https://www.mdpi.com/2072-666X/13/8/1306",
    "doi": "10.3390/mi13081306",
    "cited_by": 5,
    "snippet": "… on a commercial Knowm memristor. Based on the simulation model of the Knowm memristor, the modulation circuit is designed by using the polarity and symmetry of the memristor and …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": true,
    "is_mss": false,
    "devices": [],
    "abstract": "Digital communication based on memristors is a new field. The main principle is to construct a modulation and demodulation circuit by using the resistance variation characteristics of the memristor. Based on the establishment of the Knowm memristor simulation model, firstly, the modulation circuit is designed by using the polarity and symmetry of the memristor and combined with the commercial current feedback amplifier AD844. It is proved that the modulated signal based on the memristor is a strong function of phase, and the demodulation circuit is designed accordingly. All simulation circuits are based on the actual commercial physical device model. The analytical expression of the output signal of the modulation and demodulation circuit is deduced theoretically, and the communication performance of the whole system is simulated by LTSpice. At the same time, the influence of the parasitic capacitance of the memristor on the circuit performance is also considered. After the simulation verification, the hardware circuit experiment of the modulation and demodulation circuit is carried out. The waveforms of the modulated signal and the demodulated signal are measured by an oscilloscope. The experimental results are completely consistent with the simulation and theoretical results.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://www.mdpi.com/2072-666X/13/8/1306/pdf?version=1660530049",
    "openalex_id": "https://openalex.org/W4291891184",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "12490430211980114821",
    "title": "Ion intercalation enabled tunable frequency response in lithium niobite memristors",
    "authors": [
      "A Ghosh",
      "AS Weidenbach"
    ],
    "first_author_last": "Ghosh",
    "year": 2022,
    "venue": "IEEE Transactions on Electron Devices",
    "link": "https://ieeexplore.ieee.org/abstract/document/9991248/",
    "doi": "10.1109/ted.2022.3227498",
    "cited_by": 5,
    "snippet": "… has since been analytically studied in ion-channel memristors in … Ge2Se3-based selfdirected-channel (SDC) memristors [20], [21], GaOx switching memristors [22], and some memristor …",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": true,
    "devices": [],
    "abstract": "Memristors have emerged as a viable component for developing neuromorphic hardware platforms, which can compete with biological systems in density, accuracy, and energy efficiency. Among contemporary memristive systems, intercalation-driven lithium niobite (LiNbO2) memristors have the advantage of inherent flux-driven large analog conductance tunability ( <inline-formula xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\"> <tex-math notation=\"LaTeX\">$\\Delta {R}/{R} &gt;89$ </tex-math></inline-formula> ), a wide resistance range (~10–1E <inline-formula xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\"> <tex-math notation=\"LaTeX\">$7 \\Omega $ </tex-math></inline-formula> ) selected via geometry selection, and low-power (~100–150 mV) neuromorphic functionality resembling synaptic weight updates in the synaptic membrane. Emerging neural systems require nonstatic temporal responses to implement temporally diverse architectures, such as recurrent neural networks (RNNs), yet these temporally diverse memristors are rare. There is a gap in understanding of the frequency response of nonvolatile memristors, which is a fundamental characteristic in memristive systems and ultimately dictates the speed of adaptive learning in deployed neural networks and the memory windows available for designers in RNNs. Using both large and small signal characterization methods, these memristors demonstrate up to a decade of span in tunable frequency-dependent response, statically controlled via device geometry and scaling design rules, and dynamically tuned via channel lithium concentration. Thus, the tunable frequency dependence of resistance modulation in LiNbO2 memristors is evaluated, enabling future neural network design rules to be identified for scalable multifunctional memristive systems for neuromorphic computing applications.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4312646343",
    "relevance": "excluded",
    "review_screen": "unclear",
    "review_reason": "weak use cues: characteriz",
    "llm_verdict": "not-knowm",
    "llm_confidence": "high",
    "pdf_knowm": null,
    "knowm_role": null
  },
  {
    "cluster_id": "7396390186997046912",
    "title": "MOSFET-based memristor for high-frequency signal processing",
    "authors": [
      "M Ghosh",
      "A Singh",
      "SS Borah",
      "J Vista"
    ],
    "first_author_last": "Ghosh",
    "year": 2022,
    "venue": "IEEE Transactions on Electron Devices",
    "link": "https://ieeexplore.ieee.org/abstract/document/9745268/",
    "doi": "10.1109/ted.2022.3160940",
    "cited_by": 69,
    "snippet": "… The Knowm memristor [14] is commercially available, but still, there is a scope for more research in this domain. Bio-inspired technologies have launched the world’s first commercially …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "This research article proposes a floating memristor emulator configuration based on n-type MOSFETs only. The proposed memristor comprises three nMOS and an extra nMOS for an external grounded capacitor. Compared to the existing literature, the proposed floating MOS memristor enables a simple design without any sophisticated design complexity. The actual fingerprint of the memristor as a pinched hysteresis loop with different frequency domains and composite characteristics as incremental and decremental are well examined using computer simulation with 90-nm CMOS technology parameters for MOSFETs. The power consumed by the proposed circuit is <inline-formula xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\"> <tex-math notation=\"LaTeX\">$2.6~\\mu \\text{W}$ </tex-math></inline-formula> . In addition, an experimental test using off-the-shelf components is investigated to verify the theoretical and simulated results. Moreover, the proposed nMOS-memristor emulator application is suitable for the modulation and demodulation of binary frequency-shift keying (BFSK) and Boolean logic gates.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4225894738",
    "relevance": "excluded",
    "review_screen": "likely-cite-only",
    "review_reason": "cite/other-device cues: emulator, proposed memristor, simulation, simulated",
    "pdf_knowm": null,
    "knowm_role": null,
    "human_verdict": "not-knowm",
    "human_reason": "NO (user)"
  },
  {
    "cluster_id": "14536434241189332431",
    "title": "A single-T chaotic circuit based on a physical memristor",
    "authors": [
      "M Guo",
      "Y Zhu",
      "R Yang",
      "M Zhang",
      "K Zhao"
    ],
    "first_author_last": "Guo",
    "year": 2022,
    "venue": "The European Physical Journal Special Topics",
    "link": "https://link.springer.com/article/10.1140/epjs/s11734-022-00565-y",
    "doi": "10.1140/epjs/s11734-022-00565-y",
    "cited_by": 13,
    "snippet": "… A chaotic oscillator circuit based on the self-directed channel memristor was realized [26]. Many strange phenomena have been found in memristor-based chaotic circuits [27,28,29,30,…",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": true,
    "is_mss": false,
    "devices": [],
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4224061101",
    "relevance": "excluded",
    "review_screen": "no-abstract",
    "review_reason": "no abstract — manual check",
    "pdf_knowm": null,
    "knowm_role": null,
    "human_verdict": "not-knowm",
    "human_reason": "NO (user)"
  },
  {
    "cluster_id": "14695170672879572261",
    "title": "Combined CMOS-Memristor-Based Phase Frequency Detector",
    "authors": [
      "K Hosseini",
      "F Ebrahimabadi"
    ],
    "first_author_last": "Hosseini",
    "year": 2022,
    "venue": "Preprints.org",
    "link": "https://www.researchgate.net/profile/Kamran-Hosseini/publication/360826514_Combined_CMOS-Memristor-Based_Phase_Frequency_Detector/links/628d17e0d4e5243d9b9633d9/Combined-CMOS-Memristor-Based-Phase-Frequency-Detector.pdf",
    "doi": "10.20944/preprints202205.0308.v1",
    "cited_by": 0,
    "snippet": "… the KNOWM memristor model at VDD=1V supply voltage. … The proposed memristor-based DFF and PFD along with the … the KNOWM memristor model [13] at VDD=1V supply voltage. …",
    "pdf_url": "https://www.researchgate.net/profile/Kamran-Hosseini/publication/360826514_Combined_CMOS-Memristor-Based_Phase_Frequency_Detector/links/628d17e0d4e5243d9b9633d9/Combined-CMOS-Memristor-Based-Phase-Frequency-Detector.pdf",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "This paper presents the first demonstrations of the memristor-CMOS logic family for phase-frequency detection. We systematically design and simulate basic AND, OR, NOT, and more complex XOR and D flip-flop (DFF) cells that use a set of basic logic functions. The results obtained from the outputs show the correct operation of the designed PFD block. The proposed memristor-based cell can have significant advantages over other similar transistor-based cells in terms of low power dissipation, lower number of devices, chip area and dense fabrication. This PFD can be used to design phase-locked circuits with charge pump (CP-PLL) at high-frequency input clocks up to a few GHz. Our simulations are performed in 50nm process with the KNOWM memristor model at VDD=1V supply voltage.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://doi.org/10.20944/preprints202205.0308.v1",
    "openalex_id": "https://openalex.org/W4293062019",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "named-in-abstract"
  },
  {
    "cluster_id": "8129335370289816012",
    "title": "Review on the basic circuit elements and memristor interpretation: Analysis, technology and applications",
    "authors": [
      "A Isah",
      "JM Bilbault"
    ],
    "first_author_last": "Isah",
    "year": 2022,
    "venue": "Journal of Low Power Electronics and Applications",
    "link": "https://www.mdpi.com/2079-9268/12/3/44",
    "doi": "10.3390/jlpea12030044",
    "cited_by": 48,
    "snippet": "… the memristor because it is an active device while the memristor is … , because one memristor can replace multiple transistors. … (from KNOWM [33]) are examples of a memristor with a self-…",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "Circuit or electronic components are useful elements allowing the realization of different circuit functionalities. The resistor, capacitor and inductor represent the three commonly known basic passive circuit elements owing to their fundamental nature relating them to the four circuit variables, namely voltage, magnetic flux, current and electric charge. The memory resistor (or memristor) was claimed to be the fourth basic passive circuit element, complementing the resistor, capacitor and inductor. This paper presents a review on the four basic passive circuit elements. After a brief recall on the first three known basic passive circuit elements, a thorough description of the memristor follows. Memristor sparks interest in the scientific community due to its interesting features, for example nano-scalability, memory capability, conductance modulation, connection flexibility and compatibility with CMOS technology, etc. These features among many others are currently in high demand on an industrial scale. For this reason, thousands of memristor-based applications are reported. Hence, the paper presents an in-depth overview of the philosophical argumentations of memristor, technologies and applications.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://www.mdpi.com/2079-9268/12/3/44/pdf?version=1663817142",
    "openalex_id": "https://openalex.org/W4289711800",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "llm_verdict": "cites-only",
    "llm_confidence": "medium",
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "13427577459587403634",
    "title": "Memristor− the fourth fundamental passive electronic component and its memory interpretation",
    "authors": [
      "A Isah",
      "S Binczak",
      "ASN Tchakoutio",
      "JM Bilbault"
    ],
    "first_author_last": "Isah",
    "year": 2022,
    "venue": "J3eA",
    "link": "https://www.j3ea.org/articles/j3ea/abs/2022/02/j3ea222055/j3ea222055.html",
    "doi": "10.1051/j3ea/20222055",
    "cited_by": 0,
    "snippet": "… (a1-a3) 𝑅𝑅 = 1𝐾𝐾𝐾𝐾, (b1-b3) 𝜇𝜇 = 10𝑛𝑛𝜇𝜇, (c1c3) 𝐿𝐿 = 10𝑚𝑚𝐻𝐻 and (d1-d3) KNOWM memristor chip. The current through each component is measured and the corresponding IV …",
    "pdf_url": "https://www.j3ea.org/articles/j3ea/pdf/2022/02/j3ea222055.pdf",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "This paper aims to present to master students in electronics the recently discovered fourth basic passive circuit element − called memristor − and to better understand how the history memory of the already passed charge through it is taken into account in its I-V characteristic. In this attempt, a simple coupling device between 2 RC cells is investigated. Our calculations are in very good agreement with experiments on SPICE and Matlab softwares.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://www.j3ea.org/articles/j3ea/pdf/2022/02/j3ea222055.pdf",
    "openalex_id": "https://openalex.org/W4312236027",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "llm_verdict": "not-knowm",
    "llm_confidence": "high",
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "10092835116644672471",
    "title": "Application of the Test for Memristor to Experimental Memory Devices",
    "authors": [
      "J Kim"
    ],
    "first_author_last": "Kim",
    "year": 2022,
    "venue": "",
    "link": "https://search.proquest.com/openview/6525c97bda2cfcd7a16d0f08745410d5/1?pq-origsite=gscholar&cbl=18750&diss=y",
    "doi": null,
    "cited_by": 0,
    "snippet": "… tor with dopant W and Knowm Self-Directed-Channel (M+SDC) memristor with dopant Cr [61… atoms through a stack of chalcogenide layers with Ge2Se3 layers doped either by W (BS-AF…",
    "pdf_url": "https://scholarcommons.sc.edu/cgi/viewcontent.cgi?article=7702&context=etd",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": true,
    "devices": [],
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": null,
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "uses-knowm-device",
    "human_verdict": "uses-knowm-device",
    "human_reason": "YES (user): cites Knowm BS-AF-W and M+SDC Cr I–V"
  },
  {
    "cluster_id": "18356278531628773653",
    "title": "Study of a chaotic circuit with a physical memristor as a nonlinear resistor",
    "authors": [
      "L Laskaridis",
      "C Volos"
    ],
    "first_author_last": "Laskaridis",
    "year": 2022,
    "venue": "11th International …",
    "link": "https://ieeexplore.ieee.org/abstract/document/9837699/",
    "doi": "10.1109/mocast54814.2022.9837699",
    "cited_by": 6,
    "snippet": "… KNOWM’s memristor prompts its use as a nonlinear reistor in chaotic circuits. Therefore, in this work, for the first time, the KNOWM memristor … use of the KNOWM physical memristor has …",
    "pdf_url": "http://www.ids.uni-bremen.de/conf/mocast2022/papers/71.pdf",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "In this paper, a novel approach of the KNOWM’s physical memristor behavior is introduced. It has been experimentally observed that this memristor, under certain conditions, can behave as a static nonlinear resistor. This inherent property of the KNOWM’s memristor prompts its use as a nonlinear reistor in chaotic circuits. Therefore, in this work, for the first time, the KNOWM memristor is used as a static nonlinear resistor in a well-known chaotic oscillator circuit. In order to examine circuit’s dynamical behavior a host of nonlinear simulation tools, such as phase portraits, bifurcation and continuation diagrams, as well as maximal Lyapunov exponent diagram, are used. Interesting phenomena related to chaos theory are observed. More specifically, period-doubling route to chaos, crisis phenomena, antimonotonicity, hysteresis and coexisting attractors, are investigated.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4288389147",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "15157313077195544550",
    "title": "Antimonotonicity, hysteresis and coexisting attractors in a shinriki circuit with a physical memristor as a nonlinear resistor",
    "authors": [
      "L Laskaridis",
      "C Volos",
      "I Stouboulos"
    ],
    "first_author_last": "Laskaridis",
    "year": 2022,
    "venue": "Electronics",
    "link": "https://www.mdpi.com/2079-9292/11/12/1920",
    "doi": "10.3390/electronics11121920",
    "cited_by": 8,
    "snippet": "… KNOWM memristor behaves approximately as a static nonlinear resistor. This drawback of the KNOWM memristor … Therefore, by using the experimental data of the KNOWM memristor’s …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "A novel approach to the physical memristor’s behavior of the KNOWM is presented in this work. The KNOWM’s memristor’s intrinsic feature encourages its use as a nonlinear resistor in chaotic circuits. Furthermore, this memristor has been shown to act like a static nonlinear resistor under certain situations. Consequently, for the first time, the KNOWM memristor is used as a static nonlinear resistor in the well-known chaotic Shinriki oscillator. In order to examine the circuit’s dynamical behavior, a host of nonlinear simulation tools, such as phase portraits, bifurcation and continuation diagrams, as well as a maximal Lyapunov exponent diagram, are used. Interesting phenomena related to chaos theory are observed. More specifically, the entrance to chaotic behavior through the antimonotonicity phenomenon is observed. Furthermore, the hysteresis phenomenon, as well as the existence of coexisting attractors in regards to the initial conditions and the parameters of the system, are investigated. Moreover, the period-doubling route to chaos and crisis phenomena are observed too.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://www.mdpi.com/2079-9292/11/12/1920/pdf?version=1655784402",
    "openalex_id": "https://openalex.org/W4283204775",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "18075538967490388744",
    "title": "A ternary memristor full adder based on literal operation and module operation",
    "authors": [
      "M Lin",
      "Q Han",
      "W Luo",
      "X Wang",
      "J Chen"
    ],
    "first_author_last": "Lin",
    "year": 2022,
    "venue": "International Journal of Circuit Theory and Applications",
    "link": "https://onlinelibrary.wiley.com/doi/abs/10.1002/cta.3287",
    "doi": "10.1002/cta.3287",
    "cited_by": 4,
    "snippet": "… first commercial memristor Knowm 10 makes memristor become … more sophisticated and optimized memristor logic circuit design. … on the commercial memristor such as the Knowm chip. …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "Abstract A ternary memristor full adder is designed based on the literal operation and module‐3 plus operation. Literal operation and module‐3 plus operation are the important operations in the tri‐valued algebra system. Multiple‐valued logic can increase the amount of information carried by the signals and reduce the number of devices and connections. The combination of multiple‐valued logic and memristor is an exploration of new devices and new structures. The novel ternary memristor full adder owns the advantage of simpler structure without decoding units to convert ternary signals to binary at the terminals, and all the signals operated by the circuit are ternary. Compared with the traditional ternary full adder, the number of devices and the power consumption are greatly reduced. Simulation results of different memristor models verified the correctness and applicability of the circuit design. It provides a new idea for the design method of memristor circuits, especially multiple‐valued memristors.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4224739826",
    "relevance": "excluded",
    "review_screen": "unclear",
    "review_reason": "no strong cues",
    "llm_verdict": "not-knowm",
    "llm_confidence": "high",
    "pdf_knowm": null,
    "knowm_role": null
  },
  {
    "cluster_id": "4588562610835540763",
    "title": "Electromagnetic Interference Effects of Continuous Waves on Memristors: A Simulation Study",
    "authors": [
      "G Ma",
      "M Man",
      "Y Zhang",
      "S Liu"
    ],
    "first_author_last": "Ma",
    "year": 2022,
    "venue": "Sensors",
    "link": "https://www.mdpi.com/1424-8220/22/15/5785",
    "doi": "10.3390/s22155785",
    "cited_by": 8,
    "snippet": "… work is the Knowm SDC memristor, a BS-AF-W discrete bipolar memristor with tungsten (W) … in a 16-pin ceramic DIP package by Knowm Inc. It operates primarily through the electric field…",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": true,
    "is_mss": true,
    "devices": [],
    "abstract": "As two-terminal passive fundamental circuit elements with memory characteristics, memristors are promising devices for applications such as neuromorphic systems, in-memory computing, and tunable RF/microwave circuits. The increasingly complex electromagnetic interference (EMI) environment threatens the reliability of memristor systems. However, various EMI signals' effects on memristors are still unclear. This paper selects continuous waves (CWs) as EMI signals. It provides a deeper insight into the interference effect of CWs on the memristor driven by a sinusoidal excitation voltage, as well as a method for investigating the EMI effect of memristors. The optimal memristor model is obtained by the exhaustive traversing of the possible model parameters, and the interference effect of CWs on memristors is quantified based on this model and the proposed evaluation metrics. Simulation results indicate that CW interference may affect the switching time, dynamic range, nonlinearity, symmetry, time to the boundary, and variation of memristance. The specific interference effect depends on the operating mode of the memristor, the amplitude, and the frequency of the CW. This research provides a foundation for evaluating EMI effects and designing electromagnetic protection for memristive neuromorphic systems.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://www.mdpi.com/1424-8220/22/15/5785/pdf?version=1659509928",
    "openalex_id": "https://openalex.org/W4289731527",
    "relevance": "excluded",
    "review_screen": "unclear",
    "review_reason": "no strong cues",
    "llm_verdict": "not-knowm",
    "llm_confidence": "high",
    "pdf_knowm": null,
    "knowm_role": null
  },
  {
    "cluster_id": "5862064120205570374",
    "title": "Oscillatory circuits with a real non-volatile Stanford memristor model",
    "authors": [
      "M Di Marco",
      "M Forti",
      "L Pancioni",
      "G Innocenti"
    ],
    "first_author_last": "Marco",
    "year": 2022,
    "venue": "IEEE Access",
    "link": "https://ieeexplore.ieee.org/abstract/document/9693946/",
    "doi": "10.1109/access.2022.3146419",
    "cited_by": 16,
    "snippet": "… a non-volatile Knowm memristor [7]. Similarly, [38] investigated the nonlinear dynamics and bifurcations in a modified Shinriki oscillatory circuit also using a Knowm memristor. We also …",
    "pdf_url": "https://ieeexplore.ieee.org/iel7/6287639/6514899/09693946.pdf",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "Stanford memristor model is a widely used model that accurately characterizes real non-volatile metal-oxide resistive random access memory (RRAM) devices with bipolar switching characteristics. The paper studies for the first time the dynamics and bifurcations in a class of nonlinear oscillators with <italic xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\">real non-volatile memristor devices</i> obeying Stanford model. This is in contrast with papers in the literature considering oscillators with ideal, abstract, or artificial memristor models, that are unable to describe physical memristors implemented in nanotechnology. One main new idea in the paper is to use the memristor as a <italic xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\">programmable nonlinear resistor</i> . Namely, two principal modes of operation are considered. 1) Analogue transient phase: the oscillator is designed so that in the transient oscillations the voltage on the memristor is below threshold, hence the main memristor state variable, i.e., the gap of the insulating material, is almost constant and the memristor behaves as a static nonlinear resistor. 2) Programming phase: the nonlinear characteristic of the memristor, which depends on the gap, can be changed via the application of voltages above threshold. The paper studies nonlinear oscillations in the transient phase for a fixed gap as well as the bifurcations phenomena displayed when the gap is varied. The paper also discusses the differences between the approach in the paper and those to design other memristor oscillators with non-volatile memristors.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://ieeexplore.ieee.org/ielx7/6287639/9668973/09693946.pdf",
    "openalex_id": "https://openalex.org/W4210665017",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "llm_verdict": "not-knowm",
    "llm_confidence": "high",
    "pdf_knowm": "uses-model",
    "knowm_role": "uses-model"
  },
  {
    "cluster_id": "16580746734689162570",
    "title": "Comparative Analysis of Reconfigurable Platforms for Memristor Emulation. Materials 2022, 15, 4487",
    "authors": [
      "M Mayacela",
      "L Rentería",
      "L Contreras",
      "S Medina"
    ],
    "first_author_last": "Mayacela",
    "year": 2022,
    "venue": "Materials",
    "link": "https://www.academia.edu/download/91141135/pdf.pdf",
    "doi": "10.3390/ma15134487",
    "cited_by": 7,
    "snippet": "… works like a real memristor, that is, a memristor emulator. This memristor emulator is an electronic … and analysis of new meminductor model based on Knowm memristor. Acta Phys. Sin. …",
    "pdf_url": "https://www.academia.edu/download/91141135/pdf.pdf",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "The memristor is the fourth fundamental element in the electronic circuit field, whose memory and resistance properties make it unique. Although there are no electronic solutions based on the memristor, interest in application development has increased significantly. Nevertheless, there are only numerical Matlab or Spice models that can be used for simulating memristor systems, and designing is limited to using memristor emulators only. A memristor emulator is an electronic circuit that mimics a memristor. In this way, a research approach is to build discrete-component emulators of memristors for its study without using the actual models. In this work, two reconfigurable hardware architectures have been proposed for use in the prototyping of a non-linearity memristor emulator: the FPAA (Field Programing Analog Arrays) and the FPGA (Field Programming Gate Array). The easy programming and reprogramming of the first architecture and the performance, high area density, and parallelism of the second one allow the implementation of this type of system. In addition, a detailed comparison is shown to underline the main differences between the two approaches. These platforms could be used in more complex analog and/or digital systems, such as neural networks, CNN, digital circuits, etc.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://www.mdpi.com/1996-1944/15/13/4487/pdf?version=1656153612",
    "openalex_id": "https://openalex.org/W4283589234",
    "relevance": "excluded",
    "review_screen": "likely-cite-only",
    "review_reason": "cite/other-device cues: emulator, spice model, spice",
    "pdf_knowm": null,
    "knowm_role": null,
    "human_verdict": "not-knowm",
    "human_reason": "NO (user)"
  },
  {
    "cluster_id": "12457191015286688307",
    "title": "Available online: https://knowm. org/downloads",
    "authors": [
      "KM Memristors"
    ],
    "first_author_last": "Memristors",
    "year": 2022,
    "venue": "Knowm_Memristors. pdf (accessed on 17 May )",
    "link": "",
    "doi": null,
    "cited_by": 8,
    "snippet": "",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": null,
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "named-in-abstract"
  },
  {
    "cluster_id": "2117746159957520303",
    "title": "A variable bandwidth memristor‐based Legendre Optimum low pass filter for radio frequency applications",
    "authors": [
      "E Onyejegbu",
      "Z Zhumabay",
      "A Marzuki"
    ],
    "first_author_last": "Onyejegbu",
    "year": 2022,
    "venue": "Engineering Reports",
    "link": "https://onlinelibrary.wiley.com/doi/abs/10.1002/eng2.12513",
    "doi": "10.1002/eng2.12513",
    "cited_by": 4,
    "snippet": "… Furthermore, unlike in any work found in literature, this study examines the effect of the Knowm memristor model on L-Opt LPFs of the third order. This work presents a unique approach …",
    "pdf_url": "https://onlinelibrary.wiley.com/doi/pdf/10.1002/eng2.12513",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "Abstract This article presents the enhancement of Legendre Optimum low pass filter (LPF) in terms of reusability and bandwidth, based on the programmable memristance of memristors. Two LPFs of the third order, operating in the MF and VHF range, and designed using the insertion loss method are presented. At 600 kHz and 110 MHz, two Knowm memristors working in the forward ion‐conduction mode replace and in the filter circuit. Their conductance and therefore memristance is varied such that decreases monotonically and. Results show a bandwidth enhancement of up to 540 at 600 kHz, and up to 100 at 110 MHz. A reusable, cost‐effective, variable bandwidth filter is achieved from the original fixed bandwidth filter.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://onlinelibrary.wiley.com/doi/pdfdirect/10.1002/eng2.12513",
    "openalex_id": "https://openalex.org/W4223543553",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "named-in-abstract"
  },
  {
    "cluster_id": "17150326073675225577",
    "title": "Computer simulation of a memristor-based neuron circuit",
    "authors": [
      "VY Ostrovskii",
      "GY Kolev",
      "EA Rodionova"
    ],
    "first_author_last": "Ostrovskii",
    "year": 2022,
    "venue": "2022 Conference of Russian Young Researchers in Electrical and Electronic Engineering (ElConRus)",
    "link": "https://ieeexplore.ieee.org/abstract/document/9755702/",
    "doi": "10.1109/elconrus54750.2022.9755702",
    "cited_by": 1,
    "snippet": "… model that includes only one nonlinear element – memristor. We applied the generalized mean metastable switch (GMMS [6]) memristor model modified for the correct display of the …",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": true,
    "devices": [],
    "abstract": "Nowadays, the emerging memristor devices are considered among the most promising elements for creating neuromorphic systems. The distinguishing properties of such devices include suitable non-linear characteristics, high energy efficiency, and a CMOS-compatible manufacturing process. In this paper, we propose a novel single-compartment neuron model which represents a memristor-based electronic circuit. The principal feature of the model is the allowance for the threshold voltage snapback effect of the memristive element. The neuron model as a nonautonomous dynamical system is studied using computer simulation. The response of the system to various stimuli is shown in time series diagrams.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4224297499",
    "relevance": "excluded",
    "review_screen": "unclear",
    "review_reason": "no strong cues",
    "llm_verdict": "not-knowm",
    "llm_confidence": "high",
    "pdf_knowm": null,
    "knowm_role": null
  },
  {
    "cluster_id": "6999099267504620360",
    "title": "KNOWM memristors in a bridge synapse delay-based reservoir computing system for detection of epileptic seizures",
    "authors": [
      "D Przyczyna",
      "G Hess",
      "K Szaciłowski"
    ],
    "first_author_last": "Przyczyna",
    "year": 2022,
    "venue": "International Journal of Parallel Emergent and Distributed Systems",
    "link": "https://www.tandfonline.com/doi/abs/10.1080/17445760.2022.2088751",
    "doi": "10.1080/17445760.2022.2088751",
    "cited_by": 9,
    "snippet": "… In the studies cases, we can see that the thermal noise of the KNOWM memristor evolved … This behaviour indicates that the charge carrier dynamics in multilayer KNOWM memristors …",
    "pdf_url": "https://arxiv.org/pdf/2502.20351",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "Nanodevices that show the potential for non-linear transformation of electrical signals and various forms of memory can be successfully used in new computational paradigms, such as neuromorphic or reservoir computing. In this work, we present single-node Echo State Machine (SNESM) RC system based on bridge synapse as a computational substrate (consisting of 4 memristors and a differential amplifier) used for epileptic seizure detection. The results show that the evolution of the signal in a feedback loop helps improve the classification accuracy of the system for that task. The transformation in SNESM changes the correlation and distribution of the complexity parameters of the input signal. In general, there are more differences in the correlation of complexity parameters between the transformed signal and the input signal, which may explain the improvement in the classification scores. SNESM could prove to be a useful time series signal processing system designed to improve accuracy in classification tasks.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://arxiv.org/pdf/2502.20351",
    "openalex_id": "https://openalex.org/W4283589155",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "14035557464554258527",
    "title": "Optimization of memristor based ultrasonic transducers for mesoscopic characterization of biomaterials",
    "authors": [
      "S Dos Santos",
      "P Hemmati"
    ],
    "first_author_last": "Santos",
    "year": 2022,
    "venue": "IEEE International …",
    "link": "https://ieeexplore.ieee.org/abstract/document/9870130/",
    "doi": "10.1109/isaf51494.2022.9870130",
    "cited_by": 4,
    "snippet": "… impedance modified by an array of BS-AF-W discrete selfdirected-channel … Knowm Inc. In order to control/program the optimized distribution of set/reset inputs applied to the Knowm …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": true,
    "devices": [
      "W"
    ],
    "abstract": "A nonlinear time reversal ultrasonic (US) imaging set-up coupled with memristors was used to define the concept of memosducer in order to measure locally the characterization and aging of the skin. Each memosducer consists of a ultrasonic transducer (Panametrics 2.5 MHz) with an internal electrical impedance modified by an array of BS-AF-W discrete self-directed-channel bipolar devices commercialized in 8-pin ceramics DIP packages by Knowm Inc. In order to control/program the optimized distribution of set/reset inputs applied to the Knowm Inc. memristors, a amplitude modulated chirp-coded excitation is applied to the memosducer. The typical test equipment consists of a preamplifier Juvitek TRA-02 (0.02-5MHz) connected to a computer, an VBA100-110 Acquitek amplifier, a shear wave transducer Technisonic (2.25MHz), and a longitudinal wave transducer Panametrics V155 (5MHz). Packaged chips are presented with 8 discrete memristors in 16 Pin Ceramic DIP (Dual Inline Package) with wafer batch (DM8-16DIP-BS-AF1403272-9 226,DM8-I6DIP-BSAF 1403272-9230 Tier 3, Knowm Inc, Santa Fe, USA). The experimental set-up constitutes a basis of a reservoir computing system for US nonlinear imaging of mesoscopi properties of biomaterials.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4294338899",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "named-in-abstract"
  },
  {
    "cluster_id": "15127268999788261405",
    "title": "Memristor based ultrasonic optimized excitations for mesoscopic nonlinear characterization of biomedical tissues",
    "authors": [
      "S Dos Santos",
      "P Hemmati"
    ],
    "first_author_last": "Santos",
    "year": 2022,
    "venue": "18th Biennial Baltic …",
    "link": "https://ieeexplore.ieee.org/abstract/document/9935594/",
    "doi": "10.1109/bec56180.2022.9935594",
    "cited_by": 1,
    "snippet": "… 23]: the Knowm Inc board containing memristors ships for controlling … BS-AF-W discrete self-directed-channel bipolar devices commercialized in 8-pin ceramics DIP packages by Knowm …",
    "pdf_url": "https://www.academia.edu/download/125299038/BEC2022_paper_5151.pdf",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": true,
    "devices": [],
    "abstract": "The electronic calibration process of the nonlin-ear time reversal based ultrasonic (US) imaging device (TR-NEWS) including the memosducer is presented and fabricated experimentally using Knowm Inc. memristors. Due to the wide frequency bandwidth of the instrumentation, an amplitude mod-ulated chirp-coded optimized US excitation is suggested in order to satisfy all constraints induced by the use of memristors, ultrasonic sensors and the biomedical tissues under analysis. The proof of concept is proposed and optimized with a 8-components memosducer prototype providing low and high resistance states values statistically distributed respectively around 200Ω and 5k Ω and associated to the [100kHz-5MHz] TR-NEWS imaging device bandwidth. Experimentally tested on a polymer phantom with analogue properties of the human skin, the demonstrator constitutes a promizing reservoir computing system based on the principle of neuromorphic devices, providing new generation of multiscale data highly compatible within the Health 4.0 community.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4308823737",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "named-in-abstract"
  },
  {
    "cluster_id": "17737011101938970988",
    "title": "Measurement of Memristor Characteristics at NI ELVIS Workstation",
    "authors": [
      "EB Solovyeva",
      "YM Inshakov"
    ],
    "first_author_last": "Solovyeva",
    "year": 2022,
    "venue": "2022 Conference of Russian Young Researchers in Electrical and Electronic Engineering (ElConRus)",
    "link": "https://ieeexplore.ieee.org/abstract/document/9755797/",
    "doi": "10.1109/elconrus54750.2022.9755797",
    "cited_by": 2,
    "snippet": "… In the case of the M+SDC Memristor 8 Discrete 16 DIP manufactured by the Knowm Company, the abilities of the NI ELVIS complex to obtain and research the ampere-volt …",
    "pdf_url": "https://www.researchgate.net/profile/Elena-Solovyeva/publication/363053292_Measurement_of_Memristor_Characteristics_at_NI_ELVIS_Workstation/links/655761133fa26f66f40b6e3f/Measurement-of-Memristor-Characteristics-at-NI-ELVIS-Workstation.pdf",
    "is_knowm": true,
    "is_sdc": true,
    "is_mss": false,
    "devices": [],
    "abstract": "The analyses of current-voltage characteristics of metal oxide memristors resulted from the investigation of a real memristor is represented. The characteristics of the real memristor are measured with the help of the NI ELVIS workstation. The electrical properties of the memristor with bipolar resistive switching and the transformation of hysteresis curve into a line under increasing the frequency of the harmonic input voltage are observed on oscillograms. The estimation of resistances in low and high states on the bases of measured current-voltage characteristics is discussed.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4224253721",
    "relevance": "excluded",
    "review_screen": "likely-use",
    "review_reason": "use cues: real memristor, measured",
    "llm_verdict": "not-knowm",
    "llm_confidence": "high",
    "pdf_knowm": null,
    "knowm_role": null
  },
  {
    "cluster_id": "10633115886247722315",
    "title": "Floating memcapacitor based on knowm memristor and its dynamic behaviors",
    "authors": [
      "F Wang",
      "F Wang"
    ],
    "first_author_last": "Wang",
    "year": 2022,
    "venue": "IEEE Transactions on Circuits & Systems II Express Briefs",
    "link": "https://ieeexplore.ieee.org/abstract/document/9866566/",
    "doi": "10.1109/tcsii.2022.3201225",
    "cited_by": 10,
    "snippet": "… materials (eg, Ge2Se3). The amount of Ag + determines the resistance of Knowm memristor. So the … [27] KA Campbell, “Self-directed channel memristor for high temperature operation,” …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": true,
    "is_mss": true,
    "devices": [],
    "abstract": "Previous studies about mem-element model focus on basic concept and equivalent circuit model of mem-elements while has little research based on commercial memristor. The object of this brief is to design and implement a voltage controlled floating memcapacitor based on Knowm memristor. On the one hand, a small number of off the shelf components of the memcapacitor model makes it easier for researchers to complete the experiment. On the other hand, nonlinear dynamical behaviors are investigated, such as power-off plot, dynamic route map (DRM) and DC V-Q plot. It is found that DRM of memcapacitor demonstrate different characteristics after considering current limiting resistor. Finally, PSPICE circuit model is designed and hardware experimental results are presented.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4292969521",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-model",
    "knowm_role": "uses-model"
  },
  {
    "cluster_id": "15400833646801805114",
    "title": "Low-variance memristor-based multi-level ternary combinational logic",
    "authors": [
      "XY Wang",
      "CT Dong",
      "PF Zhou",
      "SK Nandi"
    ],
    "first_author_last": "Wang",
    "year": 2022,
    "venue": "IEEE Transactions on Circuits and Systems I Regular Papers",
    "link": "https://ieeexplore.ieee.org/abstract/document/9724615/",
    "doi": "10.1109/tcsi.2022.3151920",
    "cited_by": 32,
    "snippet": "… memristor-CMOS ternary combinational … Knowm memristor model, and we perform experimental validation of individual stages using an in-house fabricated Si-doped HfOx memristor …",
    "pdf_url": "https://www.researchgate.net/profile/Sanjoy-Nandi/publication/358973797_Low-Variance_Memristor-Based_Multi-Level_Ternary_Combinational_Logic/links/638541c348124c2bc67d0866/Low-Variance-Memristor-Based-Multi-Level-Ternary-Combinational-Logic.pdf",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "This paper presents a series of multi-stage hybrid memristor-CMOS ternary combinational logic stages that are optimized for reducing silicon area occupation. Prior demonstrations of memristive logic are typically constrained to single-stage logic due to the variety of challenges that affect device performance. Noise accumulation across subsequent stages can be amortized by integrating ternary logic gates, thus enabling higher density data transmission, where more complex computation can take place within a smaller number of stages when compared to single-bit computation. We present the design of a ternary half adder, a ternary full adder, a ternary multiplier, and a ternary magnitude comparator. These designs are simulated in SPICE using the broadly accessible Knowm memristor model, and we perform experimental validation of individual stages using an in-house fabricated Si-doped HfO <sub xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\">x</sub> memristor which exhibits low cycle-to-cycle variation, and thus contributes to robust long-term performance. We ultimately show an improvement in data density in each logic block of between <inline-formula xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\"> <tex-math notation=\"LaTeX\">$5.2\\times - 17.3\\times $ </tex-math></inline-formula> , which also accounts for intermediate voltage buffering to alleviate the memristive loading problem.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4214901488",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-model",
    "knowm_role": "uses-model"
  },
  {
    "cluster_id": "5222519010723870180",
    "title": "FPGA synthesis of ternary memristor-CMOS decoders for active matrix microdisplays",
    "authors": [
      "XY Wang",
      "ZR Wu",
      "PF Zhou",
      "HHC Iu"
    ],
    "first_author_last": "Wang",
    "year": 2022,
    "venue": "IEEE Transactions on Circuits and Systems I Regular Papers",
    "link": "https://ieeexplore.ieee.org/abstract/document/9686058/",
    "doi": "10.1109/tcsi.2022.3141087",
    "cited_by": 14,
    "snippet": "… 2(b) using Knowm’s memristor model [39] using the parameters in Table II. The transistor SPICE models (Level 54 BSIM4) are based on a 50-nm process where VDD = 1 V. The results …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "The search for a compatible application of memristor-CMOS logic gates has remained elusive, as the data density benefits are offset by slow switching speeds and resistive dissipation. Active microdisplays typically prioritize pixel density (and therefore resolution) over that of speed, where the most widely used refresh rates fall between 25–240 Hz. Therefore, memristor-CMOS logic is a promising fit for peripheral I/O logic in active matrix displays. In this paper, we design and implement a ternary 1–3 line decoder and a ternary 2–9 line decoder which are used to program a seven segment LED display. SPICE simulations are conducted in a 50-nm process, and the decoders are synthesized on an Altera Cyclone IV field-programmable gate array (FPGA) development board which implements a ternary memristor model designed in Quartus II. Our approach to logic synthesis demonstrates a potential way forward for simulating large-scale memristor-CMOS circuits without embedded RRAM for functional verification, and our SPICE results show an improvement in data density of a variety of decoders by a factor between 3.6-8.5. While the switching speed of memristors are one of several bottlenecks to using them in combinational logic, the comparatively slow refresh rates of typical microdisplays indicate this to be a tolerable trade-off, which promotes data density over speed.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4205281504",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-model",
    "knowm_role": "uses-model"
  },
  {
    "cluster_id": "3149481648064160407",
    "title": "From memristor-modeled jerk system to the nonlinear systems with memristor",
    "authors": [
      "X Wu",
      "S He",
      "W Tan",
      "H Wang"
    ],
    "first_author_last": "Wu",
    "year": 2022,
    "venue": "Symmetry",
    "link": "https://www.mdpi.com/2073-8994/14/4/659",
    "doi": "10.3390/sym14040659",
    "cited_by": 11,
    "snippet": "… using the memristor devices, although a memristor model can be … , the Knowm memristor is also considered for comparison. The i − v hysteresis loops observed in the Knowm memristor …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "Based on the proposed generalized memristor, a new jerk system is proposed. The complex dynamics of the system are investigated by means of bifurcation diagrams, Lyapunov exponents, and MSampEn, and rich dynamics are observed. Moreover, the circuits of the generalized memristor and the jerk system are physically implemented in the hardware level. The experimental results show that the memristor circuit can generate “8”-shaped pinched hysteresis loops, and the observed attractors match well with the numerical simulations results. In this paper, we summarize nonlinear systems with memristors in the references. It indicates that there are two symmetry methods to find a memristor model in nonlinear systems. However, some of them cannot be realized using the memristor devices, although a memristor model can be found. For example, the famous Lorenz system contains a memristor function, but it cannot be realized using the memristor device. The principles regarding whether nonlinear systems with a memristor function can be realized using a memristor device are discussed.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://www.mdpi.com/2073-8994/14/4/659/pdf?version=1648102063",
    "openalex_id": "https://openalex.org/W4220654448",
    "relevance": "excluded",
    "review_screen": "unclear",
    "review_reason": "weak use cues: experimental, experiment",
    "llm_verdict": "not-knowm",
    "llm_confidence": "high",
    "pdf_knowm": null,
    "knowm_role": null
  },
  {
    "cluster_id": "4019096111482488286",
    "title": "Gradient-based neuromorphic learning on dynamical RRAM arrays",
    "authors": [
      "P Zhou",
      "DU Choi",
      "WD Lu",
      "SM Kang"
    ],
    "first_author_last": "Zhou",
    "year": 2022,
    "venue": "IEEE Journal on Emerging and Selected Topics in Circuits and Systems",
    "link": "https://ieeexplore.ieee.org/abstract/document/9961206/",
    "doi": "10.1109/jetcas.2022.3224071",
    "cited_by": 32,
    "snippet": "… Although Knowm memristors are not known for their reliability, their metastable switching dynamics are accounted for within the … The memristor model used is based on the generalized …",
    "pdf_url": "https://arxiv.org/pdf/2206.12992",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": true,
    "devices": [],
    "abstract": "We present MEMprop, the adoption of gradient-based learning to train fully memristive spiking neural networks (MSNNs). Our approach harnesses intrinsic device dynamics to trigger naturally arising voltage spikes. These spikes emitted by memristive dynamics are analog in nature, and thus fully differentiable, which eliminates the need for surrogate gradient methods that are prevalent in the spiking neural network (SNN) literature. Memristive neural networks typically either integrate memristors as synapses that map offline-trained networks, or otherwise rely on associative learning mechanisms to train networks of memristive neurons. We instead apply the backpropagation through time (BPTT) training algorithm directly on analog SPICE models of memristive neurons and synapses. Our implementation is fully memristive, in that synaptic weights and spiking neurons are both integrated on resistive RAM (RRAM) arrays without the need for additional circuits to implement spiking dynamics, e.g., analog-to-digital converters (ADCs) or thresholded comparators. As a result, higher-order electrophysical effects are fully exploited to use the state-driven dynamics of memristive neurons at run time. By moving towards non-approximate gradient-based learning, we obtain highly competitive accuracy amongst previously reported lightweight dense fully MSNNs on several benchmarks.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4312081476",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-model",
    "knowm_role": "uses-model"
  },
  {
    "cluster_id": "16537900730899686853",
    "title": "A fully memristive spiking neural network with unsupervised learning",
    "authors": [
      "P Zhou",
      "DU Choi",
      "JK Eshraghian"
    ],
    "first_author_last": "Zhou",
    "year": 2022,
    "venue": "2022 IEEE International Symposium on Circuits and Systems (ISCAS)",
    "link": "https://ieeexplore.ieee.org/abstract/document/9937309/",
    "doi": "10.1109/iscas48785.2022.9937309",
    "cited_by": 9,
    "snippet": "… memristor models, and has been used to emulate the commercially available Knowm memristor [35]… the resultant memristor internal states and voltage waveforms shown below in Fig. 2: …",
    "pdf_url": "https://arxiv.org/pdf/2203.01416",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "We present a fully memristive spiking neural network (MSNN) consisting of physically-realizable memristive neurons and memristive synapses to implement an unsupervised Spike Timing Dependent Plasticity (STDP) learning rule. The system is fully memristive in that both neuronal and synaptic dynamics can be realized by using memristors. The neuron is implemented using the SPICE-level memristive integrate-and-fire (MIF) model, which consists of a minimal number of circuit elements necessary to achieve distinct depolarization, hyperpolarization, and repolarization voltage waveforms. The proposed MSNN uniquely implements STDP learning by using cumulative weight changes in memristive synapses from the voltage waveform changes across the synapses, which arise from the presynaptic and postsynaptic spiking voltage signals during the training process. Two types of MSNN architectures are investigated: 1) a biologically plausible memory retrieval system, and 2) a multi-class classification system. Our circuit simulation results verify the MSNN’s unsupervised learning efficacy by replicating biological memory retrieval mechanisms, and achieving 97.5% accuracy in a 4-pattern recognition problem in a large scale discriminative MSNN.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4312788071",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-model",
    "knowm_role": "uses-model"
  },
  {
    "cluster_id": "204870459549437324",
    "title": "Estimation of the activation energy in the Ag/SnSe/Ge2Se3/W self-directed channel memristor",
    "authors": [
      "AN Aleshin",
      "OA Ruban"
    ],
    "first_author_last": "Aleshin",
    "year": 2023,
    "venue": "Modern Electronic Materials",
    "link": "https://moem.pensoft.net/article/113245/download/pdf/",
    "doi": "10.3897/j.moem.9.3.113245",
    "cited_by": 1,
    "snippet": "… In this study, we conducted an investigation into the Ag/SnSe/Ge2Se3/W ionic memristor, … filaments and memristor degradation. To ascertain the electrical conductivity of the memristor in …",
    "pdf_url": "https://moem.pensoft.net/article/113245/download/pdf/",
    "is_knowm": false,
    "is_sdc": true,
    "is_mss": true,
    "devices": [],
    "abstract": "In this study, we conducted an investigation into the Ag/SnSe/Ge 2 Se 3 /W ionic memristor, focusing on the determination of activation energies associated with its two primary operational processes: the formation of conductive filaments and memristor degradation. To ascertain the electrical conductivity of the memristor in both its basic electronic states, a low resistance state and a high resistance state, we constructed current-voltage characteristics. The estimation of activation energy values was carried out employing the Arrhenius law and the provisions of irreversible thermodynamics, with specific reference to Onsager's second postulate. This fundamental concept posits that the growth rate of irreversible component of entropy can be expressed as the summation of products involving fluxes and thermodynamic forces when a system tends towards its equilibrium state. In the context of this study, the equilibrium state of the memristor is defined as the condition at which the memristor can no longer function as a resistive memory cell. Our experimentation involved the application of a flux of Ag + ions (electromigration). The calculated activation energy values were found to be 0.24 eV for the initial process and 1.16 eV for the latter. These divergent activation energy values indicate the differentiation between the agglomerative mechanism that governs the formation of conductive channels, prevalent in the Ag/SnSe/Ge 2 Se 3 /W memristor, and the \"conventional\" substance transfer mechanism based on a group of point defects that manifests itself during the memristor's degradation.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://moem.pensoft.net/article/113245/download/pdf/",
    "openalex_id": "https://openalex.org/W4389629834",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "fdTjI31N0-YJ",
    "title": "Activation processes during operation of an Ag/SnSe/Ge2Se3/W ion memristor with a self− directed current− conducting channel",
    "authors": [
      "AN Aleshin",
      "OA Ruban"
    ],
    "first_author_last": "Aleshin",
    "year": 2023,
    "venue": "Izvestiya Vysshikh Uchebnykh Zavedenii Materialy Elektronnoi Tekhniki = Materials of Electronics Engineering",
    "link": "https://met.misis.ru/jour/issue/download/56/54#page=37",
    "doi": "10.17073/1609-3577j.met202308.550",
    "cited_by": 0,
    "snippet": "… memristor was taken to be the state in which the memristor … conducting channel, typical of an Ag/SnSe/Ge2Se3/W memristor, … , which accompanies the process of memristor degradation. …",
    "pdf_url": "https://met.misis.ru/jour/issue/download/56/54#page=37",
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": true,
    "devices": [],
    "abstract": "In an Ag/SnSe/Ge 2 Se 3 /W ionic type memristor, the activation energy of two main processes responsible for its operation has been determined, namely: the activation energy for the formation of a conductive channel and the activation energy for memristor degradation. By measuring the current-voltage characteristics, the electrical conductivity of the memristor in low- and high-resistance operating modes was assessed. To determine the activation energy, the Arrhenius law and the provisions of the thermodynamics of irreversible processes were used, in particular the second postulate of Onsager, according to which the growth rate of the irreversible part of the entropy of a system tending to equilibrium is proportional to the sum of the products of the flows occurring in the system and the generalized thermodynamic force corresponding to each flow. The equilibrium state of the memristor was taken to be the state in which the memristor lost the ability to function as a resistive memory cell. The flow of Ag+ ions – electromigration was used as a substance flow. For the first process, the activation energy was 0.24 eV, and for the second, 1.16 eV. The different values of activation energy reflect the difference between the agglomeration mechanism of formation of a current-conducting channel, typical of an Ag/SnSe/Ge 2 Se 3 /W memristor, and the “standard” mechanism of substance transfer based on a group of point defects, which accompanies the process of memristor degradation.",
    "abstract_source": "openalex",
    "oa_pdf_url": "http://dx.doi.org/10.17073/1609-3577j.met202308.550",
    "openalex_id": "https://openalex.org/W4386967830",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "5581400763630711583",
    "title": "Experimental results of 1C1R structure based on Knowm memristor",
    "authors": [
      "A Alshaya",
      "A Malik",
      "A Mifsud"
    ],
    "first_author_last": "Alshaya",
    "year": 2023,
    "venue": "30th IEEE …",
    "link": "https://ieeexplore.ieee.org/abstract/document/10382807/",
    "doi": "10.1109/icecs58634.2023.10382807",
    "cited_by": 2,
    "snippet": "… In this paper, we have implemented a 1C1R structure utilizing a discrete Knowm memristor with Self-Directed Channel (SDC) Memristor material stack. Our experiment involved …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": true,
    "is_mss": false,
    "devices": [],
    "abstract": "This paper presents experimental findings of a new passive memristive memory structure called ICIR, which involves the series connection of one capacitor and one ReRAM. The ICIR configuration, illustrated in Fig. 1, shows great potential as a memory structure due to its high density, reduced power consumption, improved switching speed, and, notably, the monotonic relationship between the charges on the capacitor and the memristance. In this paper, we have implemented a ICIR structure utilizing a discrete Knowm memristor with Self-Directed Channel (SDC) Memristor material stack. Our experiment involved performing forming, writing, and reading operations. The forming and writing operation were done by applying pulses with a width lower than $\\frac{1}{5} R_{m e m} C$. This approach was adopted considering the high-pass filter characteristics inherent in the ICIR configuration. The results demonstrate that the ICIR structure effectively stores 1-bit of information by dividing the memristor’s resistance (memristance) into two states: 15.17 K$\\Omega$ (bit 1) and $282 \\mathrm{~K} \\Omega$ (bit 0). The memristance reading operation in this experiment was based on measuring the time required for the capacitor to charge $\\left(\\tau=R_{m e m} C\\right)$.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4390693279",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "named-in-abstract"
  },
  {
    "cluster_id": "8811513371160107390",
    "title": "Biologically plausible information propagation in a CMOS integrate-and-fire artificial neuron circuit with memristive synapses",
    "authors": [
      "L Benatti",
      "T Zanotti",
      "D Gandolfi",
      "J Mapelli",
      "FM Puglisi"
    ],
    "first_author_last": "Benatti",
    "year": 2023,
    "venue": "Nano Futures",
    "link": "https://iris.unimore.it/handle/11380/1304253",
    "doi": "10.1088/2399-1984/accf53",
    "cited_by": 8,
    "snippet": "… available Cdoped Self-Directed Channel (SDC) memristors by Knowm [36], … memristor consists of a stack composed of W/Ge2Se3/Ag/Ge2Se3/SnSe/Ge2Se3:C/W, where Ge2Se3…",
    "pdf_url": "https://iris.unimore.it/bitstream/11380/1304253/1/Benatti%2Bet%2Bal_2023_Nano_Futures_10.1088_2399-1984_accf53.pdf",
    "is_knowm": true,
    "is_sdc": true,
    "is_mss": true,
    "devices": [],
    "abstract": "Abstract Neuromorphic circuits based on spikes are currently envisioned as a viable option to achieve brain-like computation capabilities in specific electronic implementations while limiting power dissipation given their ability to mimic energy-efficient bioinspired mechanisms. While several network architectures have been developed to embed in hardware the bioinspired learning rules found in the biological brain, such as spike timing-dependent plasticity, it is still unclear if hardware spiking neural network architectures can handle and transfer information akin to biological networks. In this work, we investigate the analogies between an artificial neuron combining memristor synapses and rate-based learning rule with biological neuron response in terms of information propagation from a theoretical perspective. Bioinspired experiments have been reproduced by linking the biological probability of release with the artificial synapse conductance. Mutual information and surprise have been chosen as metrics to evidence how, for different values of synaptic weights, an artificial neuron allows to develop a reliable and biological resembling neural network in terms of information propagation and analysis.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://iopscience.iop.org/article/10.1088/2399-1984/accf53/pdf",
    "openalex_id": "https://openalex.org/W4366605893",
    "relevance": "core",
    "review_screen": "unclear",
    "review_reason": "weak use cues: experiment",
    "llm_verdict": "not-knowm",
    "llm_confidence": "high",
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "519987637193814688",
    "title": "Memristive circuit design for personalized emotion generation with memory and retrieval functions",
    "authors": [
      "Z Chen",
      "X Wang",
      "C Yang",
      "Z Wang"
    ],
    "first_author_last": "Chen",
    "year": 2023,
    "venue": "IEEE Transactions on Cognitive and Developmental Systems",
    "link": "https://ieeexplore.ieee.org/abstract/document/10255254/",
    "doi": "10.1109/tcds.2023.3317066",
    "cited_by": 13,
    "snippet": "… Hence, in this work, the memristor model is made several improvements based on the model of Knowm Inc. In addition, volatile memristors are suitable to mimic behaviors of biological …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "The generation of human emotion is often influenced by memory and personality. However, few reported circuits of emotion generation have considered this view. This work proposes a memristive emotion generation circuit with the functions of emotional memory and retrieval, and personality traits deployment. It mimics the emotional circuit of the brain and consists of six modules, which are input module, sensory cortex module, amygdala module, orbitofrontal module, hippocampus module and personality module. When inputting multimodal signals, the proposed design can not only generate two-dimensional continuous emotions, but also perform emotional memory and retrieval. Meanwhile, it provides various personality traits to mimic individual differences amid emotion generation based on the Big Five model. All in all, the designed memristive circuit provides a brain-like hierarchical and parallel emotion-generating method. It offers advantages in lower power consumption, area, and in-memory processing. In addition, the non-ideality analysis shows the circuit’s robustness. This work could provide a reference for the implementation of human-like emotional robots.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4386869692",
    "relevance": "excluded",
    "review_screen": "unclear",
    "review_reason": "no strong cues",
    "llm_verdict": "not-knowm",
    "llm_confidence": "high",
    "pdf_knowm": null,
    "knowm_role": null
  },
  {
    "cluster_id": "9692864270755465819",
    "title": "Effective current-driven memory operations for low-power reram applications",
    "authors": [
      "A Cirera",
      "B Garrido",
      "A Rubio",
      "I Vourkas"
    ],
    "first_author_last": "Cirera",
    "year": 2023,
    "venue": "IEEE Access",
    "link": "https://ieeexplore.ieee.org/abstract/document/10124933/",
    "doi": "10.1109/access.2023.3276825",
    "cited_by": 10,
    "snippet": "… RS devices are also termed memristors and/or memristive … (CBRAM) and the self-directed channel (SDC) devices [6… Ag ions into the chalcogenide Ge2Se3 layer during the first forming …",
    "pdf_url": "https://ieeexplore.ieee.org/iel7/6287639/10005208/10124933.pdf",
    "is_knowm": false,
    "is_sdc": true,
    "is_mss": true,
    "devices": [],
    "abstract": "Resistive switching (RS) devices are electronic components which exhibit a resistive state that can be adjusted to different nonvolatile levels via electrical stressing, fueling the development of future resistive memories (ReRAM) and enabling innovative solutions for several applications. Most works so far have used voltage-based driving schemes for both WRITE and READ operations. However, results from current-driven WRITE operations have shown high uniformity in switching performance, and thus constitute a valid alternative to consider, but current-driven READ operations have rarely been explored. In this context, here we tested a current-based READ/WRITE memory driving scheme on commercial self-directed channel (SDC) devices, while operating constantly at low current levels between tenths of nA and 1.5 uA. We propose a novel method to carry out efficient READ operations exploiting the transient response of the voltage on the current-driven ReRAM memory cells. For READ operations performed at 100 nA, we calculated the cumulative probability distribution of the standard deviation of the measured voltage ( <inline-formula xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\"> <tex-math notation=\"LaTeX\">$\\sigma _{\\mathrm {V}}$ </tex-math></inline-formula> ) on the devices and we observed a ratio <inline-formula xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\"> <tex-math notation=\"LaTeX\">$\\sigma _{\\mathrm {V-HRS}}/\\sigma _{\\mathrm {V-LRS}} \\sim 10\\times $ </tex-math></inline-formula> . Moreover, the HRS and LRS states were distinguishable in all the tested devices with less than 0.5% error. Finally, the calculated energy consumption ( <inline-formula xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\"> <tex-math notation=\"LaTeX\">$E_{\\mathrm {SET}} \\approx 10$ </tex-math></inline-formula> nJ, <inline-formula xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\"> <tex-math notation=\"LaTeX\">$E_{\\mathrm {RESET}} \\approx 30$ </tex-math></inline-formula> nJ, and <inline-formula xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\"> <tex-math notation=\"LaTeX\">$E_{\\mathrm {READ}}$ </tex-math></inline-formula> between 80–400 pJ) was competitive even when the duration of the READ/WRITE current pulses was suboptimal in the millisecond range. Therefore, the presented results validate the promising characteristics and the power-efficiency of the proposed READ method for current-driven ReRAM circuits and applications.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://ieeexplore.ieee.org/ielx7/6287639/10005208/10124933.pdf",
    "openalex_id": "https://openalex.org/W4376849814",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "10783135359386465873",
    "title": "Using Current to Drive Two SDC Memristors Connected in Series and in Anti-Series",
    "authors": [
      "A Cirera",
      "P Miribel-Catala",
      "A Rubio"
    ],
    "first_author_last": "Cirera",
    "year": 2023,
    "venue": "… 38th Conference on …",
    "link": "https://ieeexplore.ieee.org/abstract/document/10335996/",
    "doi": "10.1109/dcis58620.2023.10335996",
    "cited_by": 0,
    "snippet": "… To this end, here we present preliminary experimental results from two bipolar self-directed channel (SDC) memristors by Knowm Inc., connected in series with the same or the opposite …",
    "pdf_url": "https://upcommons.upc.edu/bitstreams/9c530f10-1db2-42d0-80c5-68e3188baaee/download",
    "is_knowm": true,
    "is_sdc": true,
    "is_mss": false,
    "devices": [],
    "abstract": "Networks of bipolar memristors have a rich collective switching behavior, which can be exploited in computing applications. Such a small network is formed by a pair of bipolar memristors connected in a series or anti-series configuration. The latter is known as complementary resistive switch (CRS), and has been studied for memory and for logic applications. While CRS structures have been investigated with voltage-based driving schemes, the collective behavior of current-driven networks of memristors has not yet been explored. To this end, here we present preliminary experimental results from two bipolar self-directed channel (SDC) memristors by Knowm Inc., connected in series with the same or the opposite polarity, driven by current. The amplitude of the applied current pulses varied between |0.1 uA| and |1.0 uA|. The results demonstrate that current-based driving is effective for programming simultaneously memristors that are connected in series. Moreover, the devices in the CRS configuration respond in a complementary way to the applied input current. We observed a stable and uniform performance of the devices in all our experiments. Current pulses of |0.1 uA| did not affect the state of the memristors, so they can be used to perform READ operations in current-driven resistive memory modules.",
    "abstract_source": "openalex",
    "oa_pdf_url": "http://hdl.handle.net/2117/400868",
    "openalex_id": "https://openalex.org/W4389544631",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "14003760787479925925",
    "title": "Current Driven Random Exploration of Resistive Switching Devices, an Opportunity to Improve Bit Error Ratio",
    "authors": [
      "A Cirera",
      "B Garrido",
      "A Rubio"
    ],
    "first_author_last": "Cirera",
    "year": 2023,
    "venue": "14th Spanish …",
    "link": "https://ieeexplore.ieee.org/abstract/document/10339522/",
    "doi": "10.1109/cde58627.2023.10339522",
    "cited_by": 2,
    "snippet": "… For our measurements, we used commercial self-directedchannel (SDC) bipolar devices by Knowm Inc. [6]. In our setup, along with the function generator and the digital oscilloscope of …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "Advances in resistive random-access memory (ReRAM) show promise to be used in future unconventional computing systems. Voltage-based driving schemes have been normally used both for WRITE and for READ operations on ReRAM cells. An alternative method consists in using only current pulses to drive resistive switching (RS) devices, which has not been thoroughly investigated so far. In this paper, we use a custom circuit of a voltage-controlled low current source to drive self-directed channel RS devices. We measure the voltage on the current-driven devices and calculate its standard deviation. The obtained results showed that its transient response could be exploited for READ operations. With 10-ms wide low current pulses (100nA), there were no errors in several analyses of 2 <sup xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\">15</sup> pseudorandom READ/WRITE events. Moreover, while working with different devices, we found that the high resistive and the low resistive states could be READ with this method, and the average bit error ratio (BER) was 0.075%.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4389577575",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "18115177196567020419",
    "title": "Existence of Capacitive Effects in a Tungsten-based SDC Memristive System",
    "authors": [
      "C Dalmış",
      "R Mutlu",
      "E Karakulak"
    ],
    "first_author_last": "Dalmış",
    "year": 2023,
    "venue": "Informacije MIDEM - Journal of Microelectronics Electronic Components and Materials",
    "link": "http://ojs.midem-drustvo.si/index.php/InfMIDEM/article/view/1664",
    "doi": "10.33180/infmidem2023.301",
    "cited_by": 2,
    "snippet": "… The integrated circuit shown in Figure 3.b, which has 8 Tungsten-based Knowm memristors in … about Knowm memristors can be found in [38]. The pin connections of the memristors are …",
    "pdf_url": "http://ojs.midem-drustvo.si/index.php/InfMIDEM/article/download/1664/409",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [
      "W"
    ],
    "abstract": "Following the discovery of a thin-film memristive system behaving as a memristor in 2008, memcapacitor and memcapacitive systems have also been described and become hot research areas. Tungsten-based SDC (Self-Directed Channel) memristors are already in the market and have already been used in circuit applications. They are modeled with the mean metastable switch memristor model in the literature. A memristor must have the three fingerprints described by Chua et al. In this paper, it is shown that the behavior of the Tungsten-based memristors is more complex than a memristive system and they do not always meet the three fingerprints of the memristor. It has been experimentally found that the capacitive effects are dominant at low frequencies when it is excited with a square wave voltage source when the Tungsten-based memristor is connected in series with a capacitor. It is important to model the new circuit element memristor accurately. “The Tungsten-based memristors” cannot be modeled just as a memristive system and only with the mean metastable switch memristor model. It is suggested that, Perhaps, it can be modeled considering memcapacitive effects.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://ojs.midem-drustvo.si/index.php/InfMIDEM/article/download/1664/409",
    "openalex_id": "https://openalex.org/W4388862177",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "7994410716884714869",
    "title": "Memristor-based LSTM network for text classification",
    "authors": [
      "G Dou",
      "K Zhao",
      "MEI Guo",
      "JUN Mou"
    ],
    "first_author_last": "Dou",
    "year": 2023,
    "venue": "Fractals",
    "link": "https://www.worldscientific.com/doi/abs/10.1142/S0218348X23400406",
    "doi": "10.1142/S0218348X23400406",
    "cited_by": 68,
    "snippet": "… 38 Knowm memristor is a selfdirected channel memristor. … Knowm memristors are non-self-rectifying memristors. The circuit can exist sneak current if a single memristor architecture is …",
    "pdf_url": "https://www.worldscientific.com/doi/pdf/10.1142/S0218348X23400406",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "Long short-term memory (LSTM) with significantly increased complexity and a large number of parameters have a bottleneck in computing power resulting from limited memory capacity. Hardware acceleration of LSTM using memristor circuit is an effective solution. This paper presents a complete design of memristive LSTM network system. Both the LSTM cell and the fully connected layer circuit are implemented through memristor crossbars, and the 1T1R design avoids the influence of the sneak current which helps to improve the accuracy of network calculation. To reduce the power consumption, the word embedding dimensionality was reduced using the GloVe model, and the number of features in the hidden layer was reduced. The effectiveness of the proposed scheme is verified by performing the text classification task on the IMDB dataset and the hardware training accuracy reached as high as 88.58%.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://doi.org/10.1142/s0218348x23400406",
    "openalex_id": "https://openalex.org/W4315650190",
    "relevance": "excluded",
    "review_screen": "unclear",
    "review_reason": "no strong cues",
    "llm_verdict": "not-knowm",
    "llm_confidence": "high",
    "pdf_knowm": null,
    "knowm_role": null
  },
  {
    "cluster_id": "17684037267270916796",
    "title": "A chaotic circuit based on Knowm memristor: modeling, analysis, and experimental verification.",
    "authors": [
      "W Faqiang"
    ],
    "first_author_last": "Faqiang",
    "year": 2023,
    "venue": "Journal of Shenzhen University Science & …",
    "link": "https://search.ebscohost.com/login.aspx?direct=true&profile=ehost&scope=site&authtype=crawler&jrnl=10002618&AN=163555780&h=Tadb1ftc9MXtVpbyamsvzQkkyTbRAB%2FbZ7vJmmrdj%2Bp%2FvmHPwHHq5KDhFgHFaM4zFCl2BKV41Orik%2BfXm2%2FI5Q%3D%3D&crl=c",
    "doi": null,
    "cited_by": 1,
    "snippet": "… the chaotic circuit using real memristors. In order to provide a … Knowm memristor, we construct a chaotic circuit based on the Knowm memristor by selecting the parameters of the Knowm …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": null,
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "named-in-abstract"
  },
  {
    "cluster_id": "4256691807252716899",
    "title": "Design Exploration of Threshold Logic in Memory and Experimental Implementation Using Knowm Memristors.",
    "authors": [
      "C Fernandez",
      "A Cirera",
      "I Vourkas"
    ],
    "first_author_last": "Fernandez",
    "year": 2023,
    "venue": "International Journal of …",
    "link": "https://www.researchgate.net/profile/Ioannis-Vourkas/publication/382456472_Design_Exploration_of_Threshold_Logic_in_Memory_and_Experimental_Implementation_Using_Knowm_Memristors/links/669eba2d4a172d2988b99991/Design-Exploration-of-Threshold-Logic-in-Memory-and-Experimental-Implementation-Using-Knowm-Memristors.pdf",
    "doi": null,
    "cited_by": 10,
    "snippet": "… memristors: the voltage divider and the voltage adder. We provide an analytical exploration of the impact of the HRS-to-LRS ratio of memristors on … (SDC) memristors by Knowm Inc., we …",
    "pdf_url": "https://www.researchgate.net/profile/Ioannis-Vourkas/publication/382456472_Design_Exploration_of_Threshold_Logic_in_Memory_and_Experimental_Implementation_Using_Knowm_Memristors/links/669eba2d4a172d2988b99991/Design-Exploration-of-Threshold-Logic-in-Memory-and-Experimental-Implementation-Using-Knowm-Memristors.pdf",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": null,
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "named-in-abstract"
  },
  {
    "cluster_id": "16823696142376875333",
    "title": "Adaptive Oxide Based Low-Power Memristive Devices for Neuromorphic Computing",
    "authors": [
      "A Ghosh"
    ],
    "first_author_last": "Ghosh",
    "year": 2023,
    "venue": "",
    "link": "https://search.proquest.com/openview/64acd899582679a2af3346cec92d96b1/1?pq-origsite=gscholar&cbl=18750&diss=y",
    "doi": null,
    "cited_by": 1,
    "snippet": "… Figure 1-2: (a) Resistance plot for a volatile LiNbO2 memristor with Ti contact metal showing … -conducting Ge2Se3 self-directed- channel (SDC) memristors [139][140], GaOx switching …",
    "pdf_url": "https://repository.gatech.edu/bitstreams/012db0ec-6e5f-420d-9389-a06825c7da23/download",
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": true,
    "devices": [],
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": null,
    "relevance": "excluded",
    "review_screen": "no-abstract",
    "review_reason": "no abstract — manual check",
    "pdf_knowm": null,
    "knowm_role": null,
    "human_verdict": "not-knowm",
    "human_reason": "NO (user)"
  },
  {
    "cluster_id": "8299592837517463925",
    "title": "CMOS-based memristor emulator circuits for low-power edge-computing applications",
    "authors": [
      "PK Ghosh",
      "SZ Riam",
      "MS Ahmed",
      "P Sundaravadivel"
    ],
    "first_author_last": "Ghosh",
    "year": 2023,
    "venue": "Electronics",
    "link": "https://www.mdpi.com/2079-9292/12/7/1654",
    "doi": "10.3390/electronics12071654",
    "cited_by": 38,
    "snippet": "… Although the Knowm memristor [19] is commercially available, there is still room for additional study in this area. The first commercially available memristor in the world was made …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "In this paper, an optimized memristor emulator circuit is designed, by using nine MOSFET transistors and a ground capacitor. Our area- and power-optimized emulator circuit can be used for basic data storage and processing at the monitoring edge, in real-time applications. The memristor shows a nonlinear voltage–current relationship, but no multiplier circuit provides the memristor’s nonlinear characteristics. As a result, the proposed memristor emulator has a very low chip area. The memristor circuit is designed in LTSpice, using 16 nm and 45 nm CMOS technology parameters, and the operating voltage is ±0.9 V. In this research, the theoretical derivations are validated using the simulated results of the memristor emulator circuit using different frequencies, capacitors, and input voltages in SPICE simulations.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://www.mdpi.com/2079-9292/12/7/1654/pdf?version=1680491291",
    "openalex_id": "https://openalex.org/W4362585135",
    "relevance": "excluded",
    "review_screen": "likely-cite-only",
    "review_reason": "cite/other-device cues: emulator, ltspice, spice, proposed memristor",
    "pdf_knowm": null,
    "knowm_role": null,
    "human_verdict": "not-knowm",
    "human_reason": "NO (user)"
  },
  {
    "cluster_id": "6191028378763478971",
    "title": "A Field-Programmable Metamaterial Using Memristor as a Stable Switcher",
    "authors": [
      "T Hong"
    ],
    "first_author_last": "Hong",
    "year": 2023,
    "venue": "",
    "link": "https://search.proquest.com/openview/6dac2bb54dc2e1aaeafdfb022eb5899e/1?pq-origsite=gscholar&cbl=18750&diss=y",
    "doi": null,
    "cited_by": 0,
    "snippet": "… memristor to control the current inside the circuit to induce a magnetic field. By switching role of a memristor… The memristor used in this experiment is from Knowm Inc., specifically the M+…",
    "pdf_url": "https://scholarcommons.sc.edu/cgi/viewcontent.cgi?article=8534&context=etd",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": null,
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "uses-knowm-device",
    "human_verdict": "uses-knowm-device",
    "human_reason": "YES (user): shows 'single memristor (Knowm Inc.)'"
  },
  {
    "cluster_id": "9517053292868872739",
    "title": "Characterization and modeling of variability in commercial self-directed channel memristors",
    "authors": [
      "I Jiménez-Gallo",
      "P Alex-Lázaro"
    ],
    "first_author_last": "Jiménez-Gallo",
    "year": 2023,
    "venue": "14th Spanish …",
    "link": "https://ieeexplore.ieee.org/abstract/document/10339475/",
    "doi": "10.1109/cde58627.2023.10339475",
    "cited_by": 2,
    "snippet": "… A channel with Ag agglomeration sites is formed in the Ge2Se3 layer, and their distances determine the device resistance [2]. On the other hand, the development of memristors-based …",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": true,
    "is_mss": true,
    "devices": [],
    "abstract": "Commercial Ag/Ge<inf xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</inf>Se<inf xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\">3</inf>/SnSe/Ge<inf xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</inf>Se<inf xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\">3</inf> memristors have been experimentally characterized by means of I-V plots obtained under voltage ramped signals. Variability has been measured using automatic extraction procedures. The I-V curves and variability have been modeled by means of the Dynamic Memdiode Model and the corresponding model parameters have been obtained by employing a genetic algorithm.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4389577574",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "named-in-abstract"
  },
  {
    "cluster_id": "16125405986999962440",
    "title": "The probabilistic behavior of the set and reset thresholds in Knowm's SDC memristors: Characterization and Simulation",
    "authors": [
      "GA Laguna-Sanchez",
      "M Lopez-Guerrero"
    ],
    "first_author_last": "Laguna-Sanchez",
    "year": 2023,
    "venue": "IEEE Latin America Transactions",
    "link": "https://ieeexplore.ieee.org/abstract/document/10305237/",
    "doi": "10.1109/tla.2023.10305237",
    "cited_by": 2,
    "snippet": "… tured by using the self-directed channel (SDC) technique. This kind of memristors is widely … substrates, a silver layer (source layer), a SnSe layer (assist layer) and an active Ge2Se3 …",
    "pdf_url": "https://latamt.ieeer9.org/index.php/transactions/article/download/8308/2160",
    "is_knowm": true,
    "is_sdc": true,
    "is_mss": true,
    "devices": [],
    "abstract": "This paper presents a proposal for the characterization of the set and reset thresholds for Knowms SDC memristors. The purpose is to incorporate the variability of the hysteresis cycles within the Generalized Mean Metastable Switch (GMMS) memristor model and, in this way, be able to perform simulations that reproduce these phenomena in a meaningful and computationally efficient way. We depart from the assumption that their probabilistic behavior can be well represented by using -stable random variables. The main advantage of using -stable variables is that they can capture both skewness and high variability (i.e., heavy tails), which can be exhibited by the observed phenomenon. At the same time, they also include the Gaussian random variable as a particular case, thus increasing the modeling flexibility.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4388258199",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "491855757467504097",
    "title": "Ternary combinational logic gate design based on tri-valued memristors",
    "authors": [
      "XJ Li",
      "XY Wang",
      "P Li",
      "HHC Iu",
      "ZQ Cheng"
    ],
    "first_author_last": "Li",
    "year": 2023,
    "venue": "SSRN Electronic Journal",
    "link": "https://www.frontiersin.org/journals/physics/articles/10.3389/fphy.2023.1292336/full",
    "doi": "10.3389/fphy.2023.1292336/full",
    "cited_by": 1,
    "snippet": "… memristor model is obtained. Based on this model, we obtained a tri-valued memristor by putting two Knowm memristors … single memristors (M 1 and M 2 ) and the tri-valued memristor …",
    "pdf_url": "https://www.frontiersin.org/journals/physics/articles/10.3389/fphy.2023.1292336/pdf",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "Traditional binary combinational logic circuits are generally obtained by cascading multiple basic logic gate circuits, using more components and complicated wiring. In contrast to the binary logic circuit design in this method, ternary combinational logic circuit implementation is more complicated. In this paper, a ternary circuit design method that does not require cascading basic ternary logic gates is proposed based on a tri-valued memristor, which can directly realize specific logic functions through a series connection of memristors. The ternary encoder, ternary decoder, ternary comparator, and ternary data selector are implemented by this method, and the effectiveness of the circuits is verified by LTspice simulations.",
    "abstract_source": "semanticscholar",
    "oa_pdf_url": "http://dx.doi.org/10.2139/ssrn.4489169",
    "openalex_id": "https://openalex.org/W4381886655",
    "relevance": "cites",
    "review_screen": "likely-cite-only",
    "review_reason": "cite/other-device cues: ltspice, spice, simulation",
    "pdf_knowm": "cites",
    "knowm_role": "cites"
  },
  {
    "cluster_id": "15190540022759734734",
    "title": "Testability design of memristive digital circuits based on Knowm memristor",
    "authors": [
      "M Lin",
      "W Luo",
      "Q Han",
      "L Li"
    ],
    "first_author_last": "Lin",
    "year": 2023,
    "venue": "Microelectronics Reliability",
    "link": "https://www.sciencedirect.com/science/article/pii/S0026271423001099",
    "doi": "10.1016/j.microrel.2023.115009",
    "cited_by": 3,
    "snippet": "… A multi-function memristive logic test unit based on Knowm memristor is designed and … a foundation for the research on the testability design of multi fault memristor digital circuits. …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4377143080",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "named-in-abstract"
  },
  {
    "cluster_id": "T0W3mEdjVawJ",
    "title": "Compact Model Library in Simscape for Various Memristors",
    "authors": [
      "Y Liu",
      "D Wang",
      "Z Dong",
      "W Zhao"
    ],
    "first_author_last": "Liu",
    "year": 2023,
    "venue": "International Applied …",
    "link": "https://ieeexplore.ieee.org/abstract/document/10249694/",
    "doi": "10.23919/aces-china60289.2023.10249694",
    "cited_by": 0,
    "snippet": "… memristor model with temperature attribute [3], and the model of commercial KNOWM memristor … Then, a general method to model memristors using Simscape language is illustrated by …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "In this work, a memristor compact model library based on Simscape language is proposed to bridge the gap between modeling and application of memristors. The library consists of six window function-based dopant drift models, the voltage-controlled VTEAM model, one HfOx-based memristor model, and the model of commercial KNOWM memristor. Then, a general method to model memristor using Simscape language is illustrated. Finally, some exemplary usage of the library is demonstrated by simulating the I-V characteristics and temperature variation of 1-transistor-1-memristor (1T1R) structure, and power consumption of the long-term potentiation and long-term depression (LTP/LTD) process of an artificial synapse. The library file is available for downloading and can be utilized in Simulink directly, which exhibits compatibility with the original components of Simulink and Simscape. This open-source project will be continuously updated to include the most representative models based on various memristors and theories.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4386918409",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "named-in-abstract"
  },
  {
    "cluster_id": "4434655910575342486",
    "title": "Design and simulation of memristor-based neural networks",
    "authors": [
      "PA Lázaro",
      "IJ Gallo",
      "JR Aranda",
      "AB García"
    ],
    "first_author_last": "Lázaro",
    "year": 2023,
    "venue": "arXiv preprint arXiv …",
    "link": "https://arxiv.org/abs/2306.11678",
    "doi": null,
    "cited_by": 4,
    "snippet": "… KNOWM Memristor Discovery software. This functionality allows us to characterize the electrical properties of a memristor … buffer size limitation on the Discovery board itself, where the …",
    "pdf_url": "https://arxiv.org/pdf/2306.11678",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": true,
    "devices": [],
    "abstract": "In recent times, neural networks have been gaining increasing importance in fields such as pattern recognition and computer vision. However, their usage entails significant energy and hardware costs, limiting the domains in which this technology can be employed. In this context, the feasibility of utilizing analog circuits based on memristors as efficient alternatives in neural network inference is being considered. Memristors stand out for their configurability and low power consumption. To study the feasibility of using these circuits, a physical model has been adapted to accurately simulate the behavior of commercial memristors from KNOWM. Using this model, multiple neural networks have been designed and simulated, yielding highly satisfactory results.",
    "abstract_source": "semanticscholar",
    "oa_pdf_url": null,
    "openalex_id": null,
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "sPkbt4O6boQJ",
    "title": "Design and simulation of memristor-based neural networks",
    "authors": [
      "P Álex Lázaro",
      "I Jiménez Gallo"
    ],
    "first_author_last": "Lázaro",
    "year": 2023,
    "venue": "",
    "link": "https://docta.ucm.es/bitstreams/ae6a2b86-5f54-4bd6-a56d-be81a328d3c5/download",
    "doi": null,
    "cited_by": 0,
    "snippet": "… memristors functioning properly, we can now begin to conduct our own experiments using KNOWM’s memristors through the Memristor Discovery … on the Discovery board itself, where …",
    "pdf_url": "https://docta.ucm.es/bitstreams/ae6a2b86-5f54-4bd6-a56d-be81a328d3c5/download",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": true,
    "devices": [],
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": null,
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "18271184025515790534",
    "title": "A fast homeostatic inhibitory plasticity rule circuit with a memristive synapse",
    "authors": [
      "G Ma",
      "M Man",
      "Y Zhang",
      "S Liu"
    ],
    "first_author_last": "Ma",
    "year": 2023,
    "venue": "Electronics",
    "link": "https://www.mdpi.com/2079-9292/12/3/490",
    "doi": "10.3390/electronics12030490",
    "cited_by": 3,
    "snippet": "… of the Knowm memristor is more stable than that of conventional metal oxide memristors [23]… The mathematical model of the Knowm memristor can be represented by Equations (2)–(4). …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "Learning from the robust mechanism of the biological nervous system is critical for creating reliable neuromorphic hardware. The homeostatic inhibition plasticity rule is a robust biological mechanism to balance Hebbian plasticity and resist external environmental disturbances and local damage. It plays an essential role in maintaining the homeostatic sparse firing patterns of the nervous system. This paper imitates this mechanism and provides a fast homeostatic inhibitory plasticity rule circuit with a memristive synapse. Firstly, the design method and principle of the circuit are demonstrated. Secondly, the function of the circuit was verified in PSpice© using a commercial Knowm memristor as a synapse. The PSpice© simulation results show that the circuit can achieve a weight update curve similar to the biological homeostatic inhibitory plasticity rule, and the time scale of the circuit is improved by a factor of 1000 compared to that of the biological nervous system. Furthermore, the circuit has wide applicability due to the tunable qualities of the homeostatic learning window, scaling factor, and homeostatic factor. This study provides new opportunities for building fast and reliable neuromorphic hardware.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://www.mdpi.com/2079-9292/12/3/490/pdf?version=1675044173",
    "openalex_id": "https://openalex.org/W4317206907",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "named-in-abstract"
  },
  {
    "cluster_id": "6668880437575726670",
    "title": "The emergence of memristive devices in microwave circuits: A review of progress and potential application",
    "authors": [
      "I Marković",
      "MP Ivaniš",
      "D Tošić"
    ],
    "first_author_last": "Marković",
    "year": 2023,
    "venue": "10th International …",
    "link": "https://ieeexplore.ieee.org/abstract/document/10192220/",
    "doi": "10.1109/icetran59631.2023.10192220",
    "cited_by": 1,
    "snippet": "… channels determines the resistance of the device. This type of memristor is called a self-directed channel (SDC) memristor… is achieved within the active layer of Ge2Se3. It is important to …",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": true,
    "is_mss": true,
    "devices": [],
    "abstract": "The emergence of memristive devices has sparked significant interest in microwave circuits due to their potential to revolutionize traditional microwave circuits. This review paper provides a comprehensive overview of the historical background and important results of memristors. Additionally, we present recent progress and potential applications of memristive devices in microwave passive circuits, such as phase shifters and filters. Furthermore, we showcase experimental results obtained using memristors, including the implementation of circuits such as amplifiers, phase shifters, and tunable amplifiers. These results demonstrate the effectiveness and versatility of memristors in microwave circuits’ applications. Overall, this paper highlights the key findings and implications of memristor research in the field of microwave circuits, providing an insight into the exciting possibilities for future development.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4385300815",
    "relevance": "excluded",
    "review_screen": "unclear",
    "review_reason": "weak use cues: experimental, experiment",
    "llm_verdict": "not-knowm",
    "llm_confidence": "high",
    "pdf_knowm": null,
    "knowm_role": null
  },
  {
    "cluster_id": "3943905396404223003",
    "title": "The dynamic tunability of memristor-based active filters",
    "authors": [
      "I Marković",
      "M Potrebić Ivaniš",
      "D Tošić"
    ],
    "first_author_last": "Marković",
    "year": 2023,
    "venue": "Micromachines",
    "link": "https://www.mdpi.com/2072-666X/14/11/2064",
    "doi": "10.3390/mi14112064",
    "cited_by": 3,
    "snippet": "… Here, memristors function as tunable loads in filter designs like the Sallen–Key active … a TiO 2 memristor is designed in [23]. Commercial KnowM memristors are recommended for RF …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "When the memristor was fabricated for the first time, it launched an entirely new field of research. Many of the published papers regarding memristors are primarily theoretical and are based on computer simulations. Some recent papers analyze the memristor's programming circuits, but to the best of the authors' knowledge, no memristor has been embedded into a commercial analog circuit. This paper is practically oriented and it is based on the experimental results obtained by measurements on the circuit prototype. We present a solution for automated programming of a commercially available memristor and its implementation in tunable active bandpass filter design. The novelty of this paper is that the active bandpass filter's central frequency could be programmed during the filter operation, so a pause for memristor state-switching is not required. The experimental results are promising, and open up possibilities for the memristor's application in analog systems.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://www.mdpi.com/2072-666X/14/11/2064/pdf?version=1699180630",
    "openalex_id": "https://openalex.org/W4388380194",
    "relevance": "excluded",
    "review_screen": "likely-use",
    "review_reason": "use cues: commercially available, measurement, experimental, experiment",
    "llm_verdict": "not-knowm",
    "llm_confidence": "medium",
    "pdf_knowm": null,
    "knowm_role": null
  },
  {
    "cluster_id": "5609334167504055866",
    "title": "Memristive pixel-CNN loop generate for CNN generalisations",
    "authors": [
      "V Nair",
      "A Radhakrishnan",
      "A James"
    ],
    "first_author_last": "Nair",
    "year": 2023,
    "venue": "IEEE Transactions on Nanotechnology",
    "link": "https://ieeexplore.ieee.org/abstract/document/10050814/",
    "doi": "10.1109/tnano.2023.3248108",
    "cited_by": 15,
    "snippet": "… The proposed memristive loop generate architecture was designed using 22nm CMOS technology and Knowm Meta-Stable Switch (MSS) memristor model (WOx device parameters) …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "Noisein test images can significantly reduce the inference accuracy of Convolution Neural Networks (CNNs). The learning alogrithm that optimise the CNN for inference often use training images that represent a limited number of variations of objects. Any variations from the training set makes it harder to recognise test images, thereby indicating lose of generalisation. We propose to use Gated Pixel Convolution Neural Network (PixelCNN) for generating training images to readjust the weights of pretrained CNN network. This way, the readjustment of weights using generated images, helps to improve the generalisation ability of the CNNs. Through this approach the CNN learning becomes continuous even with a limited training data and can be limited by the amount of generalisation and robustness to variability required for a given task. The proposed memristive loop generate architecture was designed using 22 nm CMOS technology and Knowm Meta-Stable Switch (MSS) memristor model ( <inline-formula xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\"><tex-math notation=\"LaTeX\">$WO_{x}$</tex-math></inline-formula> device parameters) with an on-chip area of <inline-formula xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\"><tex-math notation=\"LaTeX\">$\\text{1.54}\\;\\text{mm}^{2}$</tex-math></inline-formula> and reduced power consumption.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4321608069",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "named-in-abstract"
  },
  {
    "cluster_id": "15361244303596271843",
    "title": "A brief introduction to memristor device",
    "authors": [
      "E Omar",
      "HH Aly",
      "M Fedawy"
    ],
    "first_author_last": "Omar",
    "year": 2023,
    "venue": "International Journal of Advanced Engineering and Business Science",
    "link": "https://journals.ekb.eg/article_302656.html",
    "doi": "10.21608/ijaebs.2023.172239.1067",
    "cited_by": 5,
    "snippet": "… model then generalized mean metastable model and the … metastable switch memristor (MMS) model implements the limiting case when N⟶ ∞. The change in the number of switches X, …",
    "pdf_url": "https://journals.ekb.eg/article_302656_bfcfb015f5f98605fe88b14808688fb7.pdf",
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": true,
    "devices": [],
    "abstract": "In this paper, a brief introduction to memristor device will be presented. Since 1971, memristor device invented by Leo Chua which included in the fundamental electrical elements besides resistors, capacitors and inductors. Memristor consider as the missing elements that correlate between the flux and the charges of the electrons. Memristor was not realized as a physical component until recently. HP and Knowm are the available physical memristor device in the market with different structure. However, HP memristor is considered to be the most structure have been studied from the researchers. Now a days considered is the core element in AI accelerators which depends on memory processor structure. This paper will discuss the history of memristor and its structure based on HP and Knowm approach with mathematical models. Some fabrication techniques will be discussed and the applications.This paper will discuss the history of memristor and its structure based on HP and Knowm approach with mathematical models. Some fabrication techniques will be discussed and the applications.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://ijaebs.journals.ekb.eg/article_302656_c59e2418b6e140b180be4259833e1f4b.pdf",
    "openalex_id": "https://openalex.org/W4380152455",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "named-in-abstract"
  },
  {
    "cluster_id": "12305660298589336061",
    "title": "Design of a memristor-based neuron for spiking neural networks",
    "authors": [
      "VY Ostrovskii",
      "OS Druzhina",
      "O Kamal",
      "TI Karimov"
    ],
    "first_author_last": "Ostrovskii",
    "year": 2023,
    "venue": "Genes and Cells",
    "link": "https://genescells.ru/2313-1829/article/view/623428",
    "doi": "10.17816/gc623428",
    "cited_by": 1,
    "snippet": "… to sustain the resistive switching cycles of the memristor. … of the generalized mean metastable switch of the memristor with self-directed channel [3] represent the current in the memristor …",
    "pdf_url": "https://genescells.ru/2313-1829/article/download/623428/142865",
    "is_knowm": false,
    "is_sdc": true,
    "is_mss": true,
    "devices": [],
    "abstract": "The primary objective of neuromorphic system design is to surpass limitations in energy efficiency and scaling of classical von Neumann computing systems, through the emulation of animals’ nervous systems. This is achieved by conducting calculations in memory and encoding information in impulse signals, ultimately leading to enhanced adaptability. Adhering to these principles allows for improved energy efficiency and computational speed when solving machine learning problems, encompassing biomedical applications, embedded systems, and cyber-physical systems. Functional blocks modeling the main elements of the central nervous system, namely neurons and synapses, offer an advantage in implementing learning on a chip. The use of memristive electronic components, capable of altering their resistance based on the charge flowing through them, opens new doors for hardware implementation of neuromorphic systems. These devices offer advantages over conventional transistor electronics with respect to power consumption, component density, and performance. To achieve optimal results, the architecture of neuromorphic systems should be optimized at the device level. Memristive components are utilized to create neurons and synapses. This thesis is specifically focused on producing memristive neuron-like spike signal generators. Previously, memristive neurons were crafted using a locally active element comprised of vanadium dioxide VO2, which incorporated a negative differential resistance section of the IV-curve. One of the recent advancements in this field is a spiking neuron with frequency adaptation [1]. Its drawbacks, however, involve separating the memristive and locally active elements physically, resulting in higher energy consumption and decreased integration quality. In [2], models of memristive neurons with minimal complexity are introduced, which incorporate the Leaky Integrate-and-Fire principle. However, the circuits presented require the application of negative voltage pulses to a DC battery to reset the memristor to its initial high-resistance state. This limitation restricts its sphere of application in neuromorphic systems. This paper proposes a model of a neuron that overcomes these limitations by using the negative differential resistance of the memristor to generate spikes, along with integrating supplementary circuit components to sustain the resistive switching cycles of the memristor. The neuron model under consideration is implemented using the NI Multisim 14.2 SPICE environment and has been verified in the NI LabVIEW 2022 tool environment. The equations of the modified model of the generalized mean metastable switch of the memristor with self-directed channel [3] represent the current in the memristor branch of the neuron equivalent circuit. The simplicity of the equivalent circuitry of the neuron is attained by merging all the nonlinear features necessary for spike generation into one memristor model. The experimental phase of the study employed obtainable memristors from Knowm Corporation and the laboratory prototyping platform NI ELVIS III. The investigation of the proposed neuron model was accomplished through the application of sinusoidal and rectangular input signals. The refractory time of the neuron model was calculated. The chosen stack of computer simulation and semi-natural modeling technologies is applied within the research-driven design concept of electronic devices. This approach considers the importance of refining the properties and identification of the design object or its components during the development cycle.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://genescells.ru/2313-1829/article/download/623428/pdf",
    "openalex_id": "https://openalex.org/W4396662103",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "1721312584468575949",
    "title": "Consumer document analytical accelerator hardware",
    "authors": [
      "A Radhakrishnan",
      "D Mahapatra",
      "A James"
    ],
    "first_author_last": "Radhakrishnan",
    "year": 2023,
    "venue": "IEEE Access",
    "link": "https://ieeexplore.ieee.org/abstract/document/10018187/",
    "doi": "10.1109/access.2023.3237463",
    "cited_by": 3,
    "snippet": "… The circuit is designed with a 180nm CMOS process, Knowm Multi-Stable Switch memristor model, and WOx device parameters. We compared its performance with that of a standard …",
    "pdf_url": "https://ieeexplore.ieee.org/iel7/6287639/6514899/10018187.pdf",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "Document scanning devices are used for visual character recognition, followed by text analytics in the software. Often such character extraction is insecure, and any third party can manipulate the information. On the other hand, near-edge processing devices are restrained by limited resources and connectivity issues. The primary factors that lead to exploring independent hardware devices with natural language processing (NLP) capabilities are latency during cloud processing and computing costs. This paper introduces a hardware accelerator for information retrieval using memristive TF-IDF implementation. In this system, each sentence is represented using a memristive crossbar layer, with each column containing a single word. The number of matching scores for the TF and IDF values was implemented using operational amplifier-based comparator accumulator circuits. The circuit is designed with a 180nm CMOS process, Knowm Multi-Stable Switch memristor model, and WOx device parameters. We compared its performance with that of a standard benchmark dataset. Variability and device-to-device related issues were also taken into consideration in the analysis. This paper concludes with implementing TF-IDF score calculation for applications such as information retrieval and text summarization.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://ieeexplore.ieee.org/ielx7/6287639/10005208/10018187.pdf",
    "openalex_id": "https://openalex.org/W4316660947",
    "relevance": "cites",
    "review_screen": "unclear",
    "review_reason": "no strong cues",
    "pdf_knowm": "cites",
    "knowm_role": "cites"
  },
  {
    "cluster_id": "14263967767689272252",
    "title": "RevI-Ve: A comprehensive software interface for easy ReRAM device characterization",
    "authors": [
      "J Riquelme",
      "M Melivilu",
      "I Vourkas"
    ],
    "first_author_last": "Riquelme",
    "year": 2023,
    "venue": "12th International …",
    "link": "https://ieeexplore.ieee.org/abstract/document/10176900/",
    "doi": "10.1109/mocast57943.2023.10176900",
    "cited_by": 3,
    "snippet": "… software app and a circuit board which plugs into the Digilent Analog Discovery 2 (AD2) [10], … On the other hand, the memristor discovery educational kit [11] by Knowm Inc., shown in Fig…",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": true,
    "devices": [],
    "abstract": "Introducing the uninitiated students & researchers to ReRAM technology and its applications via true device characterization and practical laboratory work, will certainly motivate them further to implement and test their application ideas in hardware. However, the lack of knowledge of the necessary experiments and strategies to follow for the adequate treatment of such devices, is a limiting factor in this direction. This work bridges the gap introducing RevI-Ve, a comprehensive characterization software interface developed for laboratory work on ReRAM devices. RevI-Ve is compatible with the Digilent Analog Discovery instrument series and is suitable both for educational and for research purposes. RevIVe supports different voltage-/current-based circuit topologies to access the ReRAM devices and enables the quick realization of a variety of complex, yet fully-customizable, experiments. We present the principal advantages offered by the current version of this tool, a brief summary of the experiments it facilitates, and show some results with data collected from measurements on commercial Self-Directed-Channel devices sold by Knowm Inc.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4384517552",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "named-in-abstract"
  },
  {
    "cluster_id": "7994848014989009239",
    "title": "Memristor's characteristics: From non-ideal to ideal",
    "authors": [
      "F Sun",
      "J Su",
      "J Li",
      "S Duan",
      "X Hu"
    ],
    "first_author_last": "Sun",
    "year": 2022,
    "venue": "Chinese Physics B",
    "link": "https://iopscience.iop.org/article/10.1088/1674-1056/ac7548/meta",
    "doi": "10.1088/1674-1056/ac7548/meta",
    "cited_by": 4,
    "snippet": "… The memristors used in this paper are generated and manufactured by Knowm, which is a self-directed type of memristors. [21] The voltage pulses generated by the analog-to-digital …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "Memristor has been widely studied in the field of neuromorphic computing and is considered to be a strong candidate to break the von Neumann bottleneck. However, the non-ideal characteristics of memristor seriously limit its practical application. There are two sides to everything, and memristors are no exception. The non-ideal characteristics of memristors may become ideal in some applications. Genetic algorithm (GA) is a method to search for the optimal solution by simulating the process of biological evolution. It is widely used in the fields of machine learning, combinatorial optimization, and signal processing. In this paper, we simulate the biological evolutionary behavior in GA by using the non-ideal characteristics of memristors, based on which we design peripheral circuits and path planning algorithms based on memristor networks. The experimental results show that the non-ideal characteristics of memristor can well simulate the biological evolution behavior in GA.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://doi.org/10.1088/1674-1056/ac7548",
    "openalex_id": "https://openalex.org/W4281934016",
    "relevance": "excluded",
    "review_screen": "unclear",
    "review_reason": "weak use cues: experimental, experiment",
    "llm_verdict": "not-knowm",
    "llm_confidence": "medium",
    "pdf_knowm": null,
    "knowm_role": null
  },
  {
    "cluster_id": "jyVqqZAeFpgJ",
    "title": "Restoring Sanity: The Memristor Test",
    "authors": [
      "M Di Ventra",
      "YV Pershin"
    ],
    "first_author_last": "Ventra",
    "year": 2023,
    "venue": "SpringerBriefs in physics",
    "link": "https://link.springer.com/chapter/10.1007/978-3-031-25625-7_4",
    "doi": "10.1007/978-3-031-25625-7_4",
    "cited_by": 0,
    "snippet": "… a memristor or not, Footnote 3 we provide a few experimental demonstrations of the test for systems that were claimed to be memristors (… (BS-AF-W and M+SDC Cr devices) (Knowm Inc. …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": true,
    "devices": [],
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4317939360",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "uses-knowm-device",
    "human_verdict": "uses-knowm-device",
    "human_reason": "YES (user): thesis shows 'single memristor (Knowm Inc.)'"
  },
  {
    "cluster_id": "369466383016930243",
    "title": "A balanced Memristor-CMOS ternary logic family and its application",
    "authors": [
      "XY Wang",
      "JW Zhou",
      "CT Dong",
      "XH Chen"
    ],
    "first_author_last": "Wang",
    "year": 2023,
    "venue": "arXiv preprint arXiv …",
    "link": "https://arxiv.org/abs/2309.01615",
    "doi": null,
    "cited_by": 1,
    "snippet": "… Abstract: The design of balanced ternary digital logic circuits based on memristors and … results for all 9 possible inputs for TMIN and TMAX using the KNOWM memristor model…",
    "pdf_url": "https://arxiv.org/pdf/2309.01615",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "The design of balanced ternary digital logic circuits based on memristors and conventional CMOS devices is proposed. First, balanced ternary minimum gate TMIN, maximum gate TMAX and ternary inverters are systematically designed and verified by simulation, and then logic circuits such as ternary encoders, decoders and multiplexers are designed on this basis. Two different schemes are then used to realize the design of functional combinational logic circuits such as a balanced ternary half adder, multiplier, and numerical comparator. Finally, we report a series of comparisons and analyses of the two design schemes, which provide a reference for subsequent research and development of three-valued logic circuits.",
    "abstract_source": "semanticscholar",
    "oa_pdf_url": null,
    "openalex_id": null,
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-model",
    "knowm_role": "uses-model"
  },
  {
    "cluster_id": "3094473610665772135",
    "title": "Активационные процессы при работе ионного мемристора Ag/SnSe/Ge2Se3/W с самоформирующимся токопроводящим каналом",
    "authors": [
      "АН Алёшин",
      "ОА Рубан"
    ],
    "first_author_last": "Алёшин",
    "year": 2023,
    "venue": "Известия высших учебных заведений …",
    "link": "https://met.misis.ru/jour/article/view/550",
    "doi": null,
    "cited_by": 0,
    "snippet": "… of an Ag/SnSe/Ge2Se3/W ion memristor with a self-directed current-conducting channel … of a current-conducting channel, typical of an Ag/SnSe/Ge2Se3/W memristor, and the “standard” …",
    "pdf_url": "https://met.misis.ru/jour/article/download/550/442",
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": true,
    "devices": [],
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": null,
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "406036263756302132",
    "title": "A microcontroller-controlled optocoupler-based memristor emulator and its usage in a low-pass filter",
    "authors": [
      "M Arapi",
      "E Karakulak",
      "R Mutlu"
    ],
    "first_author_last": "Arapi",
    "year": 2024,
    "venue": "Iranian Journal of Science and Technology Transactions of Electrical Engineering",
    "link": "https://link.springer.com/article/10.1007/s40998-023-00694-7",
    "doi": "10.1007/s40998-023-00694-7",
    "cited_by": 5,
    "snippet": "… ideal memristor has not been found yet (Vongehr and Meng 2015; Ventra and Pershin 2023). There are Knowm memristors … do not possess them (Knowm Memristors 2023). That’s why …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4391227563",
    "relevance": "excluded",
    "review_screen": "no-abstract",
    "review_reason": "no abstract — manual check",
    "pdf_knowm": null,
    "knowm_role": null,
    "human_verdict": "not-knowm",
    "human_reason": "NO (user)"
  },
  {
    "cluster_id": "6286353265874924719",
    "title": "Investigation of Commercial Off-The-Shelf ReRAM Modules for Use as Runtime-Accessible TRNG",
    "authors": [
      "T Arul",
      "N Mexis",
      "AE George",
      "F Frank"
    ],
    "first_author_last": "Arul",
    "year": 2024,
    "venue": "27th Euromicro …",
    "link": "https://ieeexplore.ieee.org/abstract/document/10741638/",
    "doi": "10.1109/dsd64264.2024.00014",
    "cited_by": 2,
    "snippet": "… In particular, [32] and [33] used discrete Self-Directed-Channel (SDC) memristors [34] as a … of the memristors. These works used discrete memristors having a W/Ag/SnSe/W+Ge2Se3/W …",
    "pdf_url": "https://www.researchgate.net/profile/Nico_Mexis/publication/385602761_Investigation_of_Commercial_Off-The-Shelf_ReRAM_Modules_for_Use_as_Runtime-Accessible_TRNG/links/6731275f5852dd723cb5747e/Investigation-of-Commercial-Off-The-Shelf-ReRAM-Modules-for-Use-as-Runtime-Accessible-TRNG.pdf",
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": true,
    "devices": [],
    "abstract": "In this work, we analyse Commercial Off-The-Shelf (COTS) Resistive Random Access Memory (ReRAM) modules for their suitability to implement a novel runtime-accessible True Random Number Generator (TRNG). For this purpose, modules from two different manufacturers (Adesto Technologies and Fujitsu) were tested, which exhibited distinct characteristics under different conditions. If suitable parameters are selected, the proposed TRNG can successfully pass all the tests of both the NIST SP800-22 Statistical Test Suite and the NIST SP800-90B Entropy Source Test Suite at a wide range of temperatures. At the same time, the TRNG achieves a throughput of at least 28 bits per second under adverse temperature conditions and approximately 51 bits per second at room temperature, in the worst case. Therefore, the performance of the TRNG is sufficient for many practical applications such as security protocols for the Internet of Things (IoT) and in-vehicle networks [1], [2].",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4404101872",
    "relevance": "excluded",
    "review_screen": "unclear",
    "review_reason": "weak use cues: off-the-shelf",
    "llm_verdict": "not-knowm",
    "llm_confidence": "high",
    "pdf_knowm": null,
    "knowm_role": null
  },
  {
    "cluster_id": "10874394382074158234",
    "title": "Measurement and modeling of self-directed channel (SDC) memristors: An extensive study",
    "authors": [
      "K Bednarz",
      "B Garda"
    ],
    "first_author_last": "Bednarz",
    "year": 2024,
    "venue": "Energies",
    "link": "https://www.mdpi.com/1996-1073/17/21/5400",
    "doi": "10.3390/en17215400",
    "cited_by": 4,
    "snippet": "… memristors, a generalized model of metastable memristor … a metastable switch, which probabilistically switches between … The switching probability between the HRS (High-Resistance …",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": true,
    "is_mss": true,
    "devices": [
      "C",
      "Cr",
      "Sn",
      "W"
    ],
    "abstract": "This study systematically addresses the challenge of accurately modeling memristors, focusing on four distinct types doped with tungsten, tin, chromium, and carbon, fabricated by Knowm Inc. A comprehensive characterization is performed by subjecting the devices to sinusoidal excitations with varying frequencies and amplitudes, followed by data averaging and high-frequency filtering. The resulting measurements are fitted using three prominent memristor models: VTEAM, MMS, and Yakopcic. Additional bespoke modifications are assessed. These models, typically formulated as coupled algebraic differential equations integrating electrical quantities (voltage and current) with internal state variables governing device dynamics, are optimized using two robust approaches: (1) interior-point optimization with gradient-based search, and (2) Nelder–Mead gradient-free optimization, both with box constraints applied. A thorough comparison and discussion of the optimized model parameters ensue, accompanied by an examination of the sensitivity to diverse frequency and amplitude ranges. The findings inform conclusions and provide a foundation for future refinements, underscoring the importance of multi-model evaluation and advanced optimization strategies in precise memristor modeling. The presented methodology offers a valuable framework for elucidating optimal modeling paradigms tailored to specific memristor architectures and operating regimes, ultimately enhancing their integration in emerging neuromorphic and computational applications.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://www.mdpi.com/1996-1073/17/21/5400/pdf?version=1730279078",
    "openalex_id": "https://openalex.org/W4403893679",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "named-in-abstract"
  },
  {
    "cluster_id": "HG07rQBjlQ0J",
    "title": "Measurement and Modeling of SDC Memristors: Extensive Study",
    "authors": [
      "KS Bednarz",
      "B Garda"
    ],
    "first_author_last": "Bednarz",
    "year": 2024,
    "venue": "Preprints.org",
    "link": "https://www.preprints.org/frontend/manuscript/978d83c3a878f6a6cafbf9bdcc01b95e/download_pub",
    "doi": "10.20944/preprints202408.1855.v1",
    "cited_by": 0,
    "snippet": "… addresses the challenge of accurately modeling memristors, focusing on four distinct types doped with tungsten, tin, chromium, and carbon, fabricated by Known Inc. A comprehensive …",
    "pdf_url": "https://www.preprints.org/frontend/manuscript/978d83c3a878f6a6cafbf9bdcc01b95e/download_pub",
    "is_knowm": false,
    "is_sdc": true,
    "is_mss": false,
    "devices": [
      "C",
      "Cr",
      "Sn",
      "W"
    ],
    "abstract": "This study systematically addresses the challenge of accurately modeling memristors, focusing on four distinct types doped with tungsten, tin, chromium, and carbon, fabricated by Known Inc. A comprehensive characterization was performed by subjecting the devices to sinusoidal excitations with varying frequencies and amplitudes, followed by data averaging and high-frequency filtering. The resulting measurements were fitted using three prominent memristor models: VTEAM, MMS, and Yakopcic, with additional bespoke modifications assessed. These models, typically formulated as coupled algebraic-differential equations integrating electrical quantities (voltage and current) with internal state variables governing device dynamics, were optimized using two robust approaches: (1) interior-point optimization with gradient-based search, and (2) Nelder-Mead gradient-free optimization, both with box constraints applied. A thorough comparison and discussion of the optimized model parameters ensued, accompanied by an examination of sensitivity to diverse frequency and amplitude ranges. The findings inform conclusions and provide a foundation for future refinements, underscoring the importance of multi-model evaluation and advanced optimization strategies in precise memristor modeling. The presented methodology offers a valuable framework for elucidating optimal modeling paradigms tailored to specific memristor architectures and operating regimes, ultimately enhancing their integration in emerging neuromorphic and computational applications.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://www.preprints.org/manuscript/202408.1855/v1/download",
    "openalex_id": "https://openalex.org/W4401971544",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "named-in-abstract"
  },
  {
    "cluster_id": "mb3f9NLyCuMJ",
    "title": "Measurement and Modeling of SDC Memristors: Extensive Study",
    "authors": [
      "KS ł aw Bednarz",
      "B ł omiej Garda"
    ],
    "first_author_last": "Bednarz",
    "year": 2024,
    "venue": "Preprints.org",
    "link": "https://www.preprints.org/manuscript/202408.1855/download/final_file",
    "doi": "10.20944/preprints202408.1855.v1",
    "cited_by": 0,
    "snippet": "… addresses the challenge of accurately modeling memristors, focusing on four distinct types doped with tungsten, tin, chromium, and carbon, fabricated by Known Inc. A comprehensive …",
    "pdf_url": "https://www.preprints.org/manuscript/202408.1855/download/final_file",
    "is_knowm": false,
    "is_sdc": true,
    "is_mss": false,
    "devices": [
      "C",
      "Cr",
      "Sn",
      "W"
    ],
    "abstract": "This study systematically addresses the challenge of accurately modeling memristors, focusing on four distinct types doped with tungsten, tin, chromium, and carbon, fabricated by Known Inc. A comprehensive characterization was performed by subjecting the devices to sinusoidal excitations with varying frequencies and amplitudes, followed by data averaging and high-frequency filtering. The resulting measurements were fitted using three prominent memristor models: VTEAM, MMS, and Yakopcic, with additional bespoke modifications assessed. These models, typically formulated as coupled algebraic-differential equations integrating electrical quantities (voltage and current) with internal state variables governing device dynamics, were optimized using two robust approaches: (1) interior-point optimization with gradient-based search, and (2) Nelder-Mead gradient-free optimization, both with box constraints applied. A thorough comparison and discussion of the optimized model parameters ensued, accompanied by an examination of sensitivity to diverse frequency and amplitude ranges. The findings inform conclusions and provide a foundation for future refinements, underscoring the importance of multi-model evaluation and advanced optimization strategies in precise memristor modeling. The presented methodology offers a valuable framework for elucidating optimal modeling paradigms tailored to specific memristor architectures and operating regimes, ultimately enhancing their integration in emerging neuromorphic and computational applications.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://www.preprints.org/manuscript/202408.1855/v1/download",
    "openalex_id": "https://openalex.org/W4401971544",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "named-in-abstract"
  },
  {
    "cluster_id": "dUeTbpmAvqEJ",
    "title": "Implementation of Floating Charged Memristor Emulator utilizing DVCCTA",
    "authors": [
      "N Bhuwal",
      "MK Majumder"
    ],
    "first_author_last": "Bhuwal",
    "year": 2024,
    "venue": "IEEE International …",
    "link": "https://ieeexplore.ieee.org/abstract/document/10558254/",
    "doi": "10.1109/iscas58744.2024.10558254",
    "cited_by": 0,
    "snippet": "… implementation of a memristor, but due to fabrication complexity, the real memristors are still … Here, it is to note that the solid-state memristor is commercialized by KNOWM Inc.[8] and the …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "The primary objective of this work is to develop the charged-type memristor emulator for a higher frequency of operation. Here, an active current mode block DVCCTA (Differential Voltage Current Conveyor Transconductance Amplifier) is utilized along with two resistors and one capacitor to build a floating charged type memristor emulator. A straightforward switch can enable circuit operation in both Incremental and Decremental modes. The resilience of the suggested circuit is confirmed through Monte Carlo simulations to ensure its stability and performance under varying conditions. PSPICE simulation is executed for diverse frequencies and capacitors using 180nm TSMC technology. The simulation outcome supports the conclusions drawn from this literature's conceptual and frequency response analysis. To study the memory attributes of a memristor, a retention test has been carried out for both incremental and decremental modes. Finally, the proposed design is employed in the Schmitt trigger circuit to check its performance.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4400231330",
    "relevance": "excluded",
    "review_screen": "likely-cite-only",
    "review_reason": "cite/other-device cues: emulator, spice, simulation",
    "pdf_knowm": null,
    "knowm_role": null,
    "human_verdict": "not-knowm",
    "human_reason": "NO (user)"
  },
  {
    "cluster_id": "663955174247410649",
    "title": "Incremental mutators for transforming between extended higher-order elements",
    "authors": [
      "D Biolek",
      "V Biolková",
      "Z Kolka"
    ],
    "first_author_last": "Biolek",
    "year": 2024,
    "venue": "IEEE Transactions on Circuits & Systems II Express Briefs",
    "link": "https://ieeexplore.ieee.org/abstract/document/10508594/",
    "doi": "10.1109/tcsii.2024.3393471",
    "cited_by": 3,
    "snippet": "… that mimic the nonlinear behavior of the Knowm memristor. … a series combination of the Knowm memristor and a 51 k … The series combination behaves again as an extended memristor, …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "Extended Higher-Order Elements (EHOEs) have been recently introduced as a generalization of the extended memristors, memcapacitors and meminductors. This brief proposes incremental mutators for mutual transformation between EHOEs from generalized Chua’s table. It enables emulating arbitrary EHOE with nonlinear dynamics, which reflects the behavior of real-world devices. This brief demonstrates the emulation of extended memory devices that mimic the nonlinear behavior of the Knowm memristor.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4395479393",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "named-in-abstract"
  },
  {
    "cluster_id": "1486860391810751768",
    "title": "Exploring neuromorphic potentials of silver-based self-directed-channel memristors for artificial synapses in neural network circuits",
    "authors": [
      "D Biswas",
      "T Venkatesan"
    ],
    "first_author_last": "Biswas",
    "year": 2024,
    "venue": "… , and Bioreplication XIV",
    "link": "https://www.spiedigitallibrary.org/conference-proceedings-of-spie/12944/129440F/Exploring-neuromorphic-potentials-of-silver-based-self-directed-channel-memristors/10.1117/12.3008779.short",
    "doi": "10.1117/12.3008779.short",
    "cited_by": 1,
    "snippet": "… Using Knowm’s memristors, we observed a linear conductance Pulse number Dependence (PnD) curve as depicted in Figure 2(a). This curve exhibited good symmetry, indicating that …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "This paper examines the capabilities of Silver-based Self-Directed-Channel (S-SDC) memristors as artificial synapses in energy-efficient and biologically-inspired computing systems. These memristors stand out for their programmable resistance modulation, which is crucial for neural network circuits and addresses key challenges in AI hardware, such as the von Neumann bottleneck. The research focuses on the conductivity manipulation in S-SDC memristors through silver cation migration, exploring various conducting states and their temporal fluctuations. This analysis uncovers a spectrum of conductance states unique to S-SDC memristors, with enhanced programmability particularly evident in lower conductivity states, facilitating precise resistance adjustments. Additionally, the study assesses the influence of migration-induced fluctuations on the overall reliability of these devices. The paper advocates for integrating S-SDC memristors into neuromorphic computing architectures, highlighting their ability to balance computational efficiency with energy sustainability. The memristors' distinct features, including controllable conductivity, adaptability in programming, and stability, are underscored as key contributors to the evolution of neuromorphic computing.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4396781460",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "named-in-abstract"
  },
  {
    "cluster_id": "656160995764526371",
    "title": "… Biologically-inspired AI Hardware Accelerators: Unveiling the Potential of Metal Self-Directed Channel (M-SDC) Memristors in Neuromorphic Computing",
    "authors": [
      "D Biswas",
      "T Venkatesan",
      "S Sharif"
    ],
    "first_author_last": "Biswas",
    "year": 2024,
    "venue": "APS March Meeting …",
    "link": "https://ui.adsabs.harvard.edu/abs/2024APS..MARCC06009/abstract",
    "doi": null,
    "cited_by": 0,
    "snippet": "… Memristors, the fourth electronic component, offer potential despite challenges. Metal Self-Directed Channel (M-SDC) Memristors, … Our study delves into M-SDC Memristors, revealing …",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": true,
    "is_mss": false,
    "devices": [],
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": null,
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "named-in-abstract"
  },
  {
    "cluster_id": "2769986644667900635",
    "title": "Exploring thickness-dependent Cu/TiOx:Cu/Ti memristor and chaotic dynamics in a real fifth-order memristive circuit",
    "authors": [
      "Y Deng",
      "S Li",
      "P Zhang",
      "F Yuan",
      "Y Li"
    ],
    "first_author_last": "Deng",
    "year": 2023,
    "venue": "Nonlinear Dynamics",
    "link": "https://link.springer.com/article/10.1007/s11071-023-09032-2",
    "doi": "10.1007/s11071-023-09032-2",
    "cited_by": 4,
    "snippet": "… The core of the work is to illustrate the application of chaotic nanoscale memristors in computational hardware accelerators to Hopfield networks. Furthermore, memristors from KNOWM …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4389517365",
    "relevance": "excluded",
    "review_screen": "no-abstract",
    "review_reason": "no abstract — manual check",
    "pdf_knowm": null,
    "knowm_role": null,
    "human_verdict": "not-knowm",
    "human_reason": "NO (user): Cu/TiOx device"
  },
  {
    "cluster_id": "3621331566837034935",
    "title": "Operant conditioning neuromorphic circuit with addictiveness and time memory for automatic learning",
    "authors": [
      "G Dou",
      "W Guo",
      "L Kong",
      "J Sun",
      "M Guo"
    ],
    "first_author_last": "Dou",
    "year": 2024,
    "venue": "IEEE Transactions on Biomedical Circuits and Systems",
    "link": "https://ieeexplore.ieee.org/abstract/document/10500750/",
    "doi": "10.1109/tbcas.2024.3388673",
    "cited_by": 29,
    "snippet": "… memristor, , many memristor models/emulators were developed by researchers to deal with its fabrication difficulties. In [16], the function of memristors … parts sold by Knowm Inc. (Santa …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "Most operant conditioning circuits predominantly focus on simple feedback process, few studies consider the intricacies of feedback outcomes and the uncertainty of feedback time. This paper proposes a neuromorphic circuit based on operant conditioning with addictiveness and time memory for automatic learning. The circuit is mainly composed of hunger output module, neuron module, excitement output module, memristor-based decision module, and memory and feedback generation module. In the circuit, the process of output excitement and addiction in stochastic feedback is achieved. The memory of interval between the two rewards is formed. The circuit can adapt to complex scenarios with these functions. In addition, hunger and satiety are introduced to realize the interaction between biological behavior and exploration desire, which enables the circuit to continuously reshape its memories and actions. The process of operant conditioning theory for automatic learning is accomplished. The study of operant conditioning can serve as a reference for more intelligent brain-inspired neural systems.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4394805075",
    "relevance": "excluded",
    "review_screen": "unclear",
    "review_reason": "no strong cues",
    "llm_verdict": "not-knowm",
    "llm_confidence": "medium",
    "pdf_knowm": null,
    "knowm_role": null
  },
  {
    "cluster_id": "quKxLiFSrNUJ",
    "title": "Characterization and Modeling of Long-Term Device Performance in Resistive Random Access Memories",
    "authors": [
      "AH Dutt"
    ],
    "first_author_last": "Dutt",
    "year": 2024,
    "venue": "",
    "link": "https://search.proquest.com/openview/ccb5944f84930175aa33e6112b36c1e0/1?pq-origsite=gscholar&cbl=18750&diss=y",
    "doi": null,
    "cited_by": 0,
    "snippet": "… and SDC devices utilize chalcogenide materials (Ge2Se3) as … self-directed channel (SDC) memristors. I also present the crossbar array circuitry design based on the VTEAM memristor …",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": true,
    "is_mss": true,
    "devices": [],
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": null,
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "uses-knowm-device",
    "human_verdict": "uses-knowm-device",
    "human_reason": "YES (user)"
  },
  {
    "cluster_id": "7674720477832166308",
    "title": "Hardware Implementation of Memristor-Based in-Memory Computing for Classification Tasks",
    "authors": [
      "MR Eslami",
      "S Takhtardeshir",
      "S Sharif"
    ],
    "first_author_last": "Eslami",
    "year": 2024,
    "venue": "IEEE 67th …",
    "link": "https://ieeexplore.ieee.org/abstract/document/10658943/",
    "doi": "10.1109/mwscas60917.2024.10658943",
    "cited_by": 0,
    "snippet": "… To achieve the real performance of memristor-based hardware in neural network architecture, we procured and tested 16 memristors manufactured by Knowm company [19]. Fig. 1A …",
    "pdf_url": "https://www.researchgate.net/profile/Mohammadreza-Eslami-2/publication/384232119_Hardware_Implementation_of_Memristor-based_In-_Memory_Computing_for_Classification_Tasks/links/66ef26d419c9496b1fb51f21/Hardware-Implementation-of-Memristor-based-In-Memory-Computing-for-Classification-Tasks.pdf",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "Recent advancements in neuromorphic computing hardware have primarily centered around the development of integrated circuits, along with the analysis and simulation of analog circuits using the SPICE program. However, a critical shortfall of SPICE is its incapacity to accommodate algorithms and circuits based on microcontrollers, posing challenges for implementing on-chip training necessary for in-memory computing. To bridge this gap, our paper explores the implementation of SPICE-compatible circuit designs in the Proteus circuit simulator. We integrate a memristor component and a neuron model featuring a sigmoid activation function into Proteus. Subsequently, we construct a neuromorphic accelerator comprising 30 memristors and 4 neurons to demonstrate on-chip training and inference processes using an Arduino microcontroller. Additionally, our study introduces an optimal learning algorithm tailored for training memristors and adjusting synaptic weights during the training phase. The designed peripheral circuits govern all memristors throughout both training and inferencing and formulate an algorithm to apply test data for evaluating network accuracy.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4402753651",
    "relevance": "excluded",
    "review_screen": "likely-cite-only",
    "review_reason": "cite/other-device cues: spice, simulation",
    "pdf_knowm": null,
    "knowm_role": null,
    "human_verdict": "not-knowm",
    "human_reason": "NO (user)"
  },
  {
    "cluster_id": "15505208397941755930",
    "title": "Comprehensive Study of SDC Memristors for Resistive RAM Applications",
    "authors": [
      "B Garda",
      "K Bednarz"
    ],
    "first_author_last": "Garda",
    "year": 2024,
    "venue": "Energies",
    "link": "https://www.mdpi.com/1996-1073/17/2/467",
    "doi": "10.3390/en17020467",
    "cited_by": 8,
    "snippet": "… doped memristors and 50 µA for C doping [21], the memristor … and its known resistance, which allows the memristor current to … other hand the chromium doped memristor where the STD …",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": true,
    "is_mss": false,
    "devices": [],
    "abstract": "Memristors have garnered considerable attention within the scientific community as devices for emerging construction of Very Large Scale Integration (VLSI) systems. Owing to their inherent properties, they appear to be promising candidates for pivotal components in computational architectures, offering alternatives to the conventional von Neumann architectures. This work has focused on exploring potential applications of Self-Directed Channel (SDC) memristors as novel RRAM memory cells. The introductory section of the study is dedicated to evaluating the repeatability of the tested memristors. Subsequently, a detailed account of the binary programming testing process for memristors is provided, along with illustrative characteristics depicting the impact of programming pulses on a memory cell constructed from a memristor. A comprehensive data analysis was then conducted, comparing memristors with varying types of doping. The results revealed that SDC memristors exhibit a high level of switching, certainty between the Low Resistance State (LRS) and High Resistance State (HRS), suggesting their capability to facilitate the storage of multiple bits within a single memory cell.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://www.mdpi.com/1996-1073/17/2/467/pdf?version=1705560416",
    "openalex_id": "https://openalex.org/W4390973608",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "14283391954880210505",
    "title": "Implementing brain-like fear generalization and emotional arousal associated with memory",
    "authors": [
      "M Guo",
      "D Zhang",
      "W Guo",
      "G Dou"
    ],
    "first_author_last": "Guo",
    "year": 2024,
    "venue": "IEEE Transactions on Cognitive and Developmental Systems",
    "link": "https://ieeexplore.ieee.org/abstract/document/10595993/",
    "doi": "10.1109/tcds.2024.3425845",
    "cited_by": 16,
    "snippet": "… Section II describes the adaptive voltage threshold memristive (AVTM) model fitted by Knowm memristor. Section III describes the neural circuitry involved in fear generalization and …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "Emotion plays an important role in human life. In recent years, memristor-based emotion circuits have been proposed extensively, but few circuits simulate the neural circuity that generates specific emotions in the limbic system. In this article, a memristor-based circuit of brain-like fear generalization is proposed. It is described from two dimensions of perception and higher cognition, respectively, both of which are realized by simulating the limbic system of human brain. The main difference between these two dimensions lies in the circuit design of the hippocampus module. Moreover, the memory enhancement effect caused by fear is one of the reasons for the phenomenon of fear generalization. That is, high arousal of fear leads to enhanced memory. Herein, the memristor-based circuit associated with different emotional arousal and memory is designed. The simulation results in SPICE show that the circuit is able to implement the brain-like fear generalization and the emotional memory under different arousal. The circuit design of these neural networks may provide some references for the field of brain-like robots.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4400525289",
    "relevance": "excluded",
    "review_screen": "likely-cite-only",
    "review_reason": "cite/other-device cues: spice, simulation",
    "pdf_knowm": null,
    "knowm_role": null,
    "human_verdict": "not-knowm",
    "human_reason": "NO (user)"
  },
  {
    "cluster_id": "11597097397738438840",
    "title": "Memristors based Computation and Synthesis",
    "authors": [
      "P Gupta",
      "P Jennifer"
    ],
    "first_author_last": "Gupta",
    "year": 2024,
    "venue": "arXiv preprint arXiv:2409.03227",
    "link": "https://arxiv.org/abs/2409.03227",
    "doi": null,
    "cited_by": 0,
    "snippet": "… of Memristor and then using that to construct a 32-bit full adder. The paper later compares the Memristor … It would also be interesting to evaluate memristors fabricated by Knowm Inc., to …",
    "pdf_url": "https://arxiv.org/pdf/2409.03227",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "Memristor has been identified as the fourth fundamental circuit element by Dr. Leon Chua in 1971 and since then it has gathered a lot of interest because of its non-volatility and are considered as a viable solution to the beyond CMOS era computation. Recently, memristor have been used to perform basic logic operations like AND, OR, NAND, NOR, XOR etc. and are also used in applications like Dot Product Engine, Convolution Neural Networks etc. This paper presents a new behavioural model of memristor then using it to build a 32-bit ripple carry adder. The paper later compares the area, power and time delay of the 32 bit Ripple Carry Adder using memristor with the 45nm CMOS technology and highlights its advantages and pitfalls.",
    "abstract_source": "arxiv",
    "oa_pdf_url": null,
    "openalex_id": null,
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "4884806036428376516",
    "title": "An overview memristor based hardware accelerators for deep neural network",
    "authors": [
      "B Gökgöz",
      "F Gül",
      "T Aydın"
    ],
    "first_author_last": "Gökgöz",
    "year": 2024,
    "venue": "Concurrency and Computation Practice and Experience",
    "link": "https://onlinelibrary.wiley.com/doi/abs/10.1002/cpe.7997",
    "doi": "10.1002/cpe.7997",
    "cited_by": 15,
    "snippet": "… Bayat et al. conducted a study of a classifier equipped with a memristor detector. The Knowm 12 company has released a categorizer goods that uses both anti-Hebbian and Hebbian …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "Abstract The prevalence of artificial intelligence applications using artificial neural network architectures for functions such as natural language processing, text prediction, object detection, speech, and image recognition has significantly increased in today's world. The computational functions performed by artificial neural networks in classical applications require intensive and large‐scale data movement between memory and processing units. Various software and hardware efforts are being made to perform these operations more efficiently. Despite these efforts, latency in data traffic and the substantial amount of energy consumed in data processing emerge as bottleneck disadvantages of the Von Neumann architecture. To overcome this bottleneck problem, it is necessary to develop hardware units specific to artificial intelligence applications. For this purpose, neuro‐inspired computing chips are believed to provide an effective approach by designing and integrating a set of features inspired by neurobiological systems at the hardware level to address the problems arising in artificial intelligence applications. The most notable among these approaches is memristor‐based neuromorphic computing systems. Memristors are seen as promising devices for hardware‐level improvement in terms of speed and energy because they possess non‐volatile memory and exhibit analog behavior. They enable effective storage and processing of synaptic weights, offering solutions for hardware‐level development. Taking into account these advantages of memristors, this study examines the research conducted on artificial neural networks and hardware that can directly perform deep learning functions and mimic the biological brain, which is different from classical systems in today's context.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://onlinelibrary.wiley.com/doi/pdfdirect/10.1002/cpe.7997",
    "openalex_id": "https://openalex.org/W4390600268",
    "relevance": "excluded",
    "review_screen": "unclear",
    "review_reason": "no strong cues",
    "llm_verdict": "not-knowm",
    "llm_confidence": "medium",
    "pdf_knowm": null,
    "knowm_role": null
  },
  {
    "cluster_id": "10753912265096361625",
    "title": "Spatiotemporal chaos in a sine map lattice with discrete memristor coupling",
    "authors": [
      "S He",
      "B Yan",
      "X Wu",
      "H Wang",
      "M Wang"
    ],
    "first_author_last": "He",
    "year": 2024,
    "venue": "IEEE Transactions on Circuits and Systems I Regular Papers",
    "link": "https://ieeexplore.ieee.org/abstract/document/10418047/",
    "doi": "10.1109/tcsi.2023.3347411",
    "cited_by": 31,
    "snippet": "… of the two illustrative examples and an Knowm memristor based example are designed to … Knowm memristor to the discrete chaotic system, we need to discretize the Knowm memristor …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "At present, design of discrete memristor based chaotic maps starts to attract the attention of the scientists, but it is still in its incipient stage. In this paper, spatiotemporal chaos in the Sine map lattice with discrete memristor coupling is investigated. Firstly, the <inline-formula xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\"> <tex-math notation=\"LaTeX\">$3\\times m$ </tex-math></inline-formula> higher dimensional chaotic map is proposed, where there are <inline-formula xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\"> <tex-math notation=\"LaTeX\">$m$ </tex-math></inline-formula> discrete memristors and <inline-formula xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\"> <tex-math notation=\"LaTeX\">$m$ </tex-math></inline-formula> state variable difference items as the inputs of the discrete memristors. Since it is a spatiotemporal chaotic system, thus it can generate massive chaotic sequences according to the system dimension. Secondly, dynamical characteristics of the system is carried out theoretically and numerically. It shows that there are <inline-formula xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\"> <tex-math notation=\"LaTeX\">$m$ </tex-math></inline-formula> positive Lyapunov exponents with high complexity. The two examples with one memristor and two memristors are analyzed, and it indicates that the system has rich dynamics including hyperchaos and multistability. Finally, analogue circuit and DSP digital circuit of the two illustrative examples and an Knowm memristor based example are designed to verify the physical realizability of the proposed discrete memristor chaotic maps.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4391407172",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "named-in-abstract"
  },
  {
    "cluster_id": "10127527311880612169",
    "title": "The significance of a window function in the modeling of HP TiO2 memristor: Pros and Cons",
    "authors": [
      "A Isah",
      "FA Umar",
      "JM Bilbault"
    ],
    "first_author_last": "Isah",
    "year": 2024,
    "venue": "Journal of Sustainable Engineering and …",
    "link": "https://joset.com.ng/index.php/home/article/view/47",
    "doi": null,
    "cited_by": 1,
    "snippet": "… and many proposed applications by HP lab, there are no memristor chips to buy from HP… memristor chip from KNOWM.org but it is too expensive [7] [8]. This is the reason why memristor …",
    "pdf_url": "https://joset.com.ng/index.php/home/article/download/47/14",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": null,
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "5949760233327817438",
    "title": "Effects of Group IVA Elements on the Electrical Response of a Ge2Se3-Based Optically Gated Transistor",
    "authors": [
      "MF Kabir",
      "KA Campbell"
    ],
    "first_author_last": "Kabir",
    "year": 2024,
    "venue": "Micromachines",
    "link": "https://www.mdpi.com/2072-666X/15/8/1000",
    "doi": "10.3390/mi15081000",
    "cited_by": 2,
    "snippet": "… The ability to use light intensity to program memristor devices … memristor devices that are based on a-Ge 2 Se 3 material, which operate under a Self-Directed Channel (SDC) memristor …",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": true,
    "is_mss": true,
    "devices": [],
    "abstract": "The optically gated transistor (OGT) has been previously demonstrated as a viable selector device for memristor devices, and may enable optical addressing within cross-point arrays. The OGT current–voltage response is similar to a MOSFET device, with light activating the gate instead of voltage. The OGT also provides a naturally built-in compliance current for a series resistive memory element, determined by the incident light intensity on the gate, thus keeping the integrated periphery circuitry size and complexity to a minimum for a memory array. The OGT gate comprises an amorphous Ge2Se3 material that can readily be doped with other elements to alter the transistor’s electrical properties. In this work, we explore the operation of the OGT when the Ge2Se3 gate material is doped with the Group IVA elements C, Si, Sn, and Pb. The dopant atoms provide changes to the optical and electrical properties that allow key electrical properties such as the dark current, photocurrent, switching speed, and threshold voltage to be tuned.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://www.mdpi.com/2072-666X/15/8/1000/pdf?version=1722498814",
    "openalex_id": "https://openalex.org/W4401212947",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "named-in-abstract"
  },
  {
    "cluster_id": "7261730539840149803",
    "title": "Sawtooth Signal Generator Using a Carbon-Based Memristor",
    "authors": [
      "E Karakulak",
      "R Mutlu"
    ],
    "first_author_last": "Karakulak",
    "year": 2024,
    "venue": "GAZI UNIVERSITY JOURNAL OF SCIENCE",
    "link": "https://dergipark.org.tr/en/download/article-file/2587841",
    "doi": "10.35378/gujs.1159917",
    "cited_by": 2,
    "snippet": "… A Knowm memristor is used to demonstrate chaos experimentally [34]. To the best of our knowledge, a Carbon-based Knowm memristor … a carbon-based memristor produced by Knowm …",
    "pdf_url": "https://dergipark.org.tr/en/download/article-file/2587841",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [
      "C"
    ],
    "abstract": "It is possible to use the new electronic circuit element memristor in analog applications. Memristors or memristor emulators have already been applied in analog applications such as amplifiers, filters, oscillators, and chaotic circuits. In literature, it has been recently demonstrated that a memristor-based sawtooth signal generator can be built utilizing a memristor emulator and simulations with various memristor models. Such a sawtooth signal generator needs experimental verification with a memristor. Self-Directed Channel (SDC) Carbon-based Memristors are in the market now. Once, the memristor technology is mature enough, its applications may also follow soon. Any memristor application should be realized with a memristor, not an emulator. Knowm memristor has not been used to design a sawtooth signal generator in the literature previously. The aim of the study is to show that a sawtooth signal generator can be made using a Self-Directed Channel (SDC) Carbon-based Memristor and to examine it experimentally. The performance of this sawtooth signal generator is evaluated. The waveforms of the proposed circuit are also examined by varying its operating frequency. The simulation and experimental results are compared. It has been found that its waveforms can be predicted well up to 350 kHz and its high-frequency behavior is not predicted well above 350 kHz by the memristor model used.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://dergipark.org.tr/en/download/article-file/2587841",
    "openalex_id": "https://openalex.org/W4391226138",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "12554872187981887680",
    "title": "A simple LTSPICE memristor neuron with a modified transfer function",
    "authors": [
      "S Kirilov",
      "V Mladenov"
    ],
    "first_author_last": "Kirilov",
    "year": 2024,
    "venue": "13th International Conference on …",
    "link": "https://ieeexplore.ieee.org/abstract/document/10615915/",
    "doi": "10.1109/mocast61810.2024.10615915",
    "cited_by": 4,
    "snippet": "… The offered model is adjusted in MATLAB, using experimental voltage-current relations of self-directed channel memristors [10]. Low error between the characteristics is derived. Time …",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": true,
    "is_mss": false,
    "devices": [],
    "abstract": "Memristors are state-of-the-art nano-scale electronic components characterized by excellent switching and memorizing capabilities, small energy usage and a good compatibility to CMOS integrated circuits. They are potentially applicable in neural nets, memory crossbars, and different electronic schemes. This paper suggests a plain LTSPICE model of a modified transfer function and a neuron, based on memristors. In neurons’ implementation, synapses are realized with single memristors, leading to a significantly reduced circuit complexity. The scaling and summing circuits are built on utilization of memristors and op-amps. The offered modified tangent-sigmoidal transfer function is realized with memristors and MOS transistors. For the analyses, a simple and high-speed memristor model is proposed. The offered memristor-based neuron is analyzed in LTSPICE and MATLAB. A comparison of the obtained results approves the proper action of the suggested neuron. The realized memristor neuron is an essential step towards engineering of complex neural nets and implementation in ultra-high-density integrated neural chips.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4401362148",
    "relevance": "excluded",
    "review_screen": "likely-cite-only",
    "review_reason": "cite/other-device cues: spice model, ltspice, spice",
    "pdf_knowm": null,
    "knowm_role": null,
    "human_verdict": "not-knowm",
    "human_reason": "NO (user)"
  },
  {
    "cluster_id": "7515343414304274030",
    "title": "A memristor emulation in 180-nm CMOS process for spiking signal generation and chaos application",
    "authors": [
      "P Kumar",
      "RK Ranjan",
      "SM Kang"
    ],
    "first_author_last": "Kumar",
    "year": 2024,
    "venue": "IEEE Transactions on Circuits and Systems I Regular Papers",
    "link": "https://ieeexplore.ieee.org/abstract/document/10387460/",
    "doi": "10.1109/tcsi.2023.3348695",
    "cited_by": 32,
    "snippet": "… On the contrary, the Knowm memristor device requires initial … device unlike that of our memristor emulator counterpart. The high … memristor emulator outperforms the Knowm memristor. …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "We present a new CMOS circuit and its successful fabrication of an operational transconductance amplifier (OTA)-CMOS inverter-based memristor emulator and investigate its switching behavior from 5 MHz to 50 MHz. It could be considered the first memristor emulator based on a current mode circuit and an inverter. Primarily, the transconductance of the inverter stage transforms the bias-voltage-dependent transconductance of the OTA into an overall flux-dependent memductance of the memristor. We also demonstrate how performance measures such as frequency response, noise, post-layout simulation, and process corners impact the memristive behavior of the design. The power consumption of the proposed memristor emulator is 2.25 mW. The aforementioned power figure is based on a 1.8 V power supply and calculated on a UMC 180-nm CMOS technology node. Further, using this memristor emulator, we implement a CMOS circuit for spiking signal generation called the Memristive Integrate-and-Fire (MIF) neuron circuit that mimics a biological neuron. As far as we know, a spiking signal generation using a memristor emulator remains unreported. Later on, we went on to realize a MIF neuron based object detection application to bring out the practical significance of the MIF neuron circuit. We have fabricated a chip of the proposed memristor emulator design with the die size of L= <inline-formula xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\"> <tex-math notation=\"LaTeX\">$1499.96~\\mu \\text{m}$ </tex-math></inline-formula> , W= <inline-formula xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\"> <tex-math notation=\"LaTeX\">$1499.96~\\mu \\text{m}$ </tex-math></inline-formula> , and included its fabrication result to validate the theoretical derivations in the work. At last, we perform an experimental realization of a chaos circuit application with the help of the fabricated chip.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4390691144",
    "relevance": "excluded",
    "review_screen": "likely-cite-only",
    "review_reason": "cite/other-device cues: emulator, proposed memristor, simulation",
    "pdf_knowm": null,
    "knowm_role": null,
    "human_verdict": "not-knowm",
    "human_reason": "NO (user)"
  },
  {
    "cluster_id": "5792581722457889932",
    "title": "A compact memristor model based on physics-informed neural networks",
    "authors": [
      "Y Lee",
      "K Kim",
      "J Lee"
    ],
    "first_author_last": "Lee",
    "year": 2024,
    "venue": "Micromachines",
    "link": "https://www.mdpi.com/2072-666X/15/2/253",
    "doi": "10.3390/mi15020253",
    "cited_by": 10,
    "snippet": "… to develop a unified memristor model. The types of models are given using the generalized mean metastable switching memristor (GMMS) model [21,22] and the memristor model of …",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": true,
    "devices": [],
    "abstract": "Memristor devices have diverse physical models depending on their structure. In addition, the physical properties of memristors are described using complex differential equations. Therefore, it is necessary to integrate the various models of memristor into an unified physics-based model. In this paper, we propose a physics-informed neural network (PINN)-based compact memristor model. PINNs can solve complex differential equations intuitively and with ease. This methodology is used to conduct memristor physical analysis. The weight and bias extracted from the PINN are implemented in a Verilog-A circuit simulator to predict memristor device characteristics. The accuracy of the proposed model is verified using two memristor devices. The results show that PINNs can be used to extensively integrate memristor device models.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://www.mdpi.com/2072-666X/15/2/253/pdf?version=1707383064",
    "openalex_id": "https://openalex.org/W4391654540",
    "relevance": "excluded",
    "review_screen": "unclear",
    "review_reason": "no strong cues",
    "llm_verdict": "not-knowm",
    "llm_confidence": "medium",
    "pdf_knowm": null,
    "knowm_role": null
  },
  {
    "cluster_id": "7012239526426774437",
    "title": "Conditional and Multi-Level WRITE Operations on Current-Controlled Memristive Devices for Neuromorphic Applications",
    "authors": [
      "M Melivilu",
      "I Vourkas",
      "PA Vila"
    ],
    "first_author_last": "Melivilu",
    "year": 2024,
    "venue": "IEEE 24th …",
    "link": "https://ieeexplore.ieee.org/abstract/document/10628600/",
    "doi": "10.1109/nano61778.2024.10628600",
    "cited_by": 1,
    "snippet": "… 8 Experimental results from SDC Knowm Inc. memristors [14]. Conditional SET response tested when (a) RP = ROFF and (b) RP = RON. In both plots, red curve represents the applied …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "The analog response of memristive devices makes them suitable for various applications, such as multilevel memory and neuromorphic computing. When the devices are voltage-driven, resistive switching is associated with voltage thresholds, representing the minimum required voltage to trigger a SET or RESET. Most simulation models correspond to voltage-controlled memristive devices, and multilevel tuning in such cases can be achieved via a controlled voltage-driven SET process. However, when current drivers are used instead of voltage drivers, a proper assessment of device performance should also consider models of current-controlled devices whose response adheres to current thresholds. To this end, here we provide both the voltage- and the current-controlled version of a behavioral model of memristive devices in a readily available netlist for simulation in LTSpice. We present simulation results using both model versions and show that, to achieve multilevel tuning of current-controlled devices when current-driven, a current divider circuit can enable a controlled RESET process. Finally, we provide experimental results for the controlled switching response of Self-Directed Channel (SDC) bipolar memristive devices by Knowm Inc. Overall, we demonstrate the feasibility of conditional and multilevel switching of current-controlled memristive devices, towards the design of current-based multilevel drivers and in-memory logic based on the conditional switching response triggered via current stimuli.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4401753343",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "named-in-abstract"
  },
  {
    "cluster_id": "8879743243460703568",
    "title": "A Simple Memristor Model for Memory Crossbars",
    "authors": [
      "VM Mladenov",
      "SM Kirilov"
    ],
    "first_author_last": "Mladenov",
    "year": 2024,
    "venue": "12th International Scientific …",
    "link": "https://ieeexplore.ieee.org/abstract/document/10778508/",
    "doi": "10.1109/comsci63166.2024.10778508",
    "cited_by": 1,
    "snippet": "… it might be summarized that the improved memristor models B6 and Bmod have a little bit lesser precision than the standard Laiho-Lehtonen and Knowm memristor models, but they are …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "Memristors are favorable circuit components with very good commutating and memory properties. They are with small power usage, nano-sizes, and good compatibility to CMOS high-density integrated circuits. Memristors are relevant for creating neural nets, memory arrays, and various electric schemes. The design, analysis and simulations of memristor elements and electronic schemes, based on memristors by software simulators are significant tasks. This paper offers analysis of memristor arrays in GNU Octave and LTSPICE by some numerical methods. The considered modified memristor model is an appropriate one, because it is with a high-rate operation, very good switching features and includes activation threshold, which permits reading and writing processes. A comparison with several other regularly used standard and modified memristor models and analysis of their behavior are conducted. Analyses are made in LTSPICE and Octave, and comparison of obtained results approves model’s accurate operation. The suggested work could be suitable for both educational and scientific utilizations.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4405271604",
    "relevance": "excluded",
    "review_screen": "likely-cite-only",
    "review_reason": "cite/other-device cues: ltspice, spice, simulation",
    "pdf_knowm": null,
    "knowm_role": null,
    "human_verdict": "not-knowm",
    "human_reason": "NO (user)"
  },
  {
    "cluster_id": "6307012033162411922",
    "title": "A memristor neural network based on simple logarithmic-sigmoidal transfer function with MOS transistors",
    "authors": [
      "V Mladenov",
      "S Kirilov"
    ],
    "first_author_last": "Mladenov",
    "year": 2024,
    "venue": "Preprints.org",
    "link": "https://www.mdpi.com/2079-9292/13/5/893",
    "doi": "10.20944/preprints202401.1245.v1",
    "cited_by": 4,
    "snippet": "… In this work, it is adjusted in accordance with current–voltage dependencies, derived by experimental data of Knowm self-directed channel memristors [36]. A technique for altering the …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": true,
    "is_mss": false,
    "devices": [],
    "abstract": "Memristors are state-of-the-art, nano-sized, two-terminal, passive electronic elements with very good switching and memory characteristics. Owing to their very low power usage and a good compatibility to the existing CMOS ultra-high-density integrated circuits and chips, they are po-tentially applicable in artificial and spiking neural networks, memory arrays, and many other de-vices and circuits for artificial intelligence. In this paper, a complete electronic realization of ana-log circuit model of modified neural net with memristor-based synapses and transfer function with memristors and MOS transistors in LTSPICE is offered. Each synaptic weight is realized by only one memristor, providing enormously reduced circuit complexity. The summing and scaling implementation is founded on op-amps and memristors. The logarithmic-sigmoidal activation function is based on a simple scheme with MOS transistors and memristors. The functioning of the suggested memristor-based neural network for pulse input signals is evaluated both analytically in MATLAB-SIMULINK and in LTSPICE environment. The obtained results are compared one to another and are successfully verified. The realized memristor-based neural network is an im-portant step towards the forthcoming design of complex memristor-based neural networks for ar-tificial intelligence, for implementation in very high-density integrated circuits and chips.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://www.preprints.org/frontend/manuscript/149bef8d18e8a158822ad1ce7e3f017a/download_pub",
    "openalex_id": "https://openalex.org/W4390953149",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "uses-knowm-model",
    "human_verdict": "uses-knowm-model",
    "human_reason": "YES (user): fit to experimental data of Knowm SDC memristors"
  },
  {
    "cluster_id": "10121569642651356524",
    "title": "Empirical mathematical model based on optimized parameter extraction from captured electrohydrodynamic inkjet memristor device with LTspice model",
    "authors": [
      "E Omar",
      "HH Aly",
      "OE Hassan",
      "M Fedawy"
    ],
    "first_author_last": "Omar",
    "year": 2024,
    "venue": "Journal of Computational Electronics",
    "link": "https://link.springer.com/article/10.1007/s10825-024-02223-z",
    "doi": "10.1007/s10825-024-02223-z",
    "cited_by": 2,
    "snippet": "… a new memristor known as W dopant type similar to HP memristor and is based on the redox phenomena. However, KNOWM devices … Figure 4 shows KNOWM memristor structure [8]. …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4402929303",
    "relevance": "excluded",
    "review_screen": "no-abstract",
    "review_reason": "no abstract — manual check",
    "pdf_knowm": null,
    "knowm_role": null,
    "human_verdict": "not-knowm",
    "human_reason": "NO (user)"
  },
  {
    "cluster_id": "3912465671348161384",
    "title": "Hybrid CMOS Memristor Based Frequency Divider Using D Flip Flop",
    "authors": [
      "S Panda",
      "CS Dash"
    ],
    "first_author_last": "Panda",
    "year": 2024,
    "venue": "Parul International Conference on …",
    "link": "https://ieeexplore.ieee.org/abstract/document/10716182/",
    "doi": "10.1109/picet60765.2024.10716182",
    "cited_by": 1,
    "snippet": "… Knowm Inc.'s generalized memristor. Knowm Inc. … switching components with dynamical development across discrete time intervals can be used to model a metastable switch memristor. …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": true,
    "devices": [],
    "abstract": "Memristors' ease of integration with contemporary CMOS technology has led to their widespread use in the design of logic circuits in recent years. Consequently, the development of hybrid memristor CMOS logic circuits has led to a reduction in the power consumption, device area requirements, and additional latency of logic circuits. In this study, a hybrid memristor CMOS logic frequency divider is created as a basic clock divider to split the frequency of another signal. By importing its SPICE model and TSMC 180nm model files into LTSPICE, the Knowm memristor is used to build and simulate the critical blocks, which are the NOR gate-based D Flip-Flops. Moreover, the recommended designs use fewer components, resulting in greater space efficiency and potential for complex circuit design and execution.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4403598975",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "named-in-abstract"
  },
  {
    "cluster_id": "604964108281200068",
    "title": "Hybrid CMOS Memristor-Based Data Compressor Using Shannon Fano Encoder",
    "authors": [
      "S Panda",
      "CS Dash"
    ],
    "first_author_last": "Panda",
    "year": 2024,
    "venue": "1st International Conference on …",
    "link": "https://ieeexplore.ieee.org/abstract/document/10530752/",
    "doi": "10.1109/ic-cgu58078.2024.10530752",
    "cited_by": 2,
    "snippet": "… this work is done using the generalized memristor proposed by Knowm Inc. [6]. Discrete memristors are currently available for purchase from Knowm Inc., and various devices are being …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "Recently, memristors have been widely employed for building logic circuits as they can be easily integrated with the existing CMOS technology, paving the way for Hybrid Memristor CMOS logic circuits, which mainly decreases the power consumption, die area requirements and further delay associated with the logic circuits. In this work, a Shannon-Fano encoder is designed using Hybrid Memristor CMOS logic, which is widely employed for data compression applications. The key blocks viz. Source Encoder, Decoder, and Priority encoder are built and simulated using Knowm memristor by invoking its SPICE model and TSMC 180nm model files into LT SPICE. Further, the proposed design is found to consume low die area as fewer numbers of transistors were used.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4398225240",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "named-in-abstract"
  },
  {
    "cluster_id": "13452872765698078902",
    "title": "A new operational amplifier model using a memristor emulator circuit and application to a phase-shifted oscillator circuit Memristör taklit devresi kullanılarak yeni bir …",
    "authors": [
      "I Parlar",
      "M Almalı"
    ],
    "first_author_last": "Parlar",
    "year": 2024,
    "venue": "Journal of the Faculty of Engineering and …",
    "link": "https://avesis.yyu.edu.tr/yayin/4ca1d6ab-1d72-41b8-b3c1-edee01990a12/a-new-operational-amplifier-model-using-a-memristor-emulator-circuit-and-application-to-a-phase-shifted-oscillator-circuit-memristor-taklit-devresi-kullanilarak-yeni-bir-islemsel-yukseltec-modeli-ve-faz-kaydirmali-osilator-devresine-uygulanmasi",
    "doi": null,
    "cited_by": 4,
    "snippet": "… Uygulamada, çoğunlukla emülatör devreleri ile yapılan çalışmalar çoğunluktadır ve Knowm adlı bir şirket memristor çipini üretmiş ve pazarlamıştır [5]. Ancak, memristor çipli analog …",
    "pdf_url": "https://avesis.yyu.edu.tr/yayin/4ca1d6ab-1d72-41b8-b3c1-edee01990a12/a-new-operational-amplifier-model-using-a-memristor-emulator-circuit-and-application-to-a-phase-shifted-oscillator-circuit-memristor-taklit-devresi-kullanilarak-yeni-bir-islemsel-yukseltec-modeli-ve-faz-kaydirmali-osilator-devresine-uygulanmasi/document.pdf",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": null,
    "relevance": "cites",
    "review_screen": "no-abstract",
    "review_reason": "no abstract — manual check",
    "pdf_knowm": "cites",
    "knowm_role": "cites"
  },
  {
    "cluster_id": "16979937383317666968",
    "title": "IMPLY-based approximate full adders for efficient arithmetic operations in image processing and machine learning",
    "authors": [
      "M Qiu",
      "C Fan",
      "S Shakibhamedan",
      "F Seiler"
    ],
    "first_author_last": "Qiu",
    "year": 2024,
    "venue": "arXiv preprint arXiv …",
    "link": "https://arxiv.org/abs/2412.15888",
    "doi": null,
    "cited_by": 1,
    "snippet": "… For this, we sequentially implicate the content of the A-memristor and the B-memristor to the … (VTEAM) model implemented in SPICE [33] with the parameters fitted to a discrete Knowm …",
    "pdf_url": "https://arxiv.org/pdf/2412.15888?",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "To overcome the performance limitations in modern computing, such as the power wall, emerging computing paradigms are gaining increasing importance. Approximate computing offers a promising solution by substantially enhancing energy efficiency and reducing latency, albeit with a trade-off in accuracy. Another emerging method is memristor-based In-Memory Computing (IMC) which has the potential to overcome the Von Neumann bottleneck. In this work, we combine these two approaches and propose two Serial APProximate IMPLY-based full adders (SAPPI). When embedded in a Ripple Carry Adder (RCA), our designs reduce the number of steps by 39%-41% and the energy consumption by 39%-42% compared to the exact algorithm. We evaluated our approach at the circuit level and compared it with State-of-the-Art (SoA) approximations where our adders improved the speed by up to 10% and the energy efficiency by up to 13%. We applied our designs in three common image processing applications where we achieved acceptable image quality with up to half of the RCA approximated. We performed a case study to demonstrate the applicability of our approximations in Machine Learning (ML) underscoring the potential gains in more complex scenarios. The proposed approach demonstrates energy savings of up to 296 mJ (21%) and a reduction of 1.3 billion (20%) computational steps when applied to Convolutional Neural Networks (CNNs) trained on the MNIST dataset while maintaining accuracy.",
    "abstract_source": "arxiv",
    "oa_pdf_url": null,
    "openalex_id": null,
    "relevance": "core",
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    "review_reason": null,
    "pdf_knowm": "uses-device",
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  },
  {
    "cluster_id": "10234904956616176270",
    "title": "An Advanced Memory WRITE Algorithm to Mitigate the Effects of ReRAM Cell Variability",
    "authors": [
      "V Ramirez",
      "J Cayo",
      "I Vourkas"
    ],
    "first_author_last": "Ramirez",
    "year": 2024,
    "venue": "13th International …",
    "link": "https://ieeexplore.ieee.org/abstract/document/10615523/",
    "doi": "10.1109/mocast61810.2024.10615523",
    "cited_by": 2,
    "snippet": "… We present experimental results from the characterization of Self-Directed Channel (SDC) bipolar devices by Knowm Inc. [12]. All measurements were carried out at room temperature …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": true,
    "is_mss": false,
    "devices": [],
    "abstract": "ReRAM cells store digital information in form of resistance using low and high resistance states, whose precise distributions are attributed to the inherent switching variability of the devices. Once the SET & RESET threshold values are known, the WRITE pulse amplitudes are selected only slightly larger, avoiding high amplitudes that could impact the device endurance. However, after several cycles such small pulses frequently cause incomplete transitions in WRITE attempts. We exemplify this with experimental measurements on commercial Self-Directed Channel (SDC) memristive devices. To overcome state transition errors, more comprehensive WRITE schemes are required. In this direction, here we discuss the development of an advanced ReRAM WRITE algorithm, as a first approach towards the design of memory control units for ReRAM modules. The proposed driving scheme contemplates gradual and verified WRITE operations, and can successfully cope with the effects of variability. Its effectiveness was validated via high-level simulations in Python, using a behavioral model of memristive devices, which was significantly enriched to support nonideal performance features. The results demonstrate that advanced ReRAM WRITE schemes could mitigate the effects of variability and improve the performance of memory cells.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4401361860",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "named-in-abstract"
  },
  {
    "cluster_id": "dumSAmtBG5oJ",
    "title": "Design and physical implementation of memristive logic and computation units",
    "authors": [
      "R Rashidi"
    ],
    "first_author_last": "Rashidi",
    "year": 2024,
    "venue": "",
    "link": "https://repositum.tuwien.at/handle/20.500.12708/193743",
    "doi": null,
    "cited_by": 0,
    "snippet": "… of a Knowm memristor at TU Vienna in the BELIEVER model persuaded us to adopt this model, conducting further measurements on various memristors to … of the Knowm memristors are …",
    "pdf_url": "https://repositum.tuwien.at/bitstream/20.500.12708/193743/1/Rashidi%20Reza%20-%202024%20-%20Design%20and%20physical%20implementation%20of%20memristive%20logic%20and...pdf",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": null,
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-knowm-device",
    "human_verdict": "uses-knowm-device",
    "human_reason": "YES (user): PDF on disk (TU Wien)"
  },
  {
    "cluster_id": "12152327897628360660",
    "title": "Review of memristor based neuromorphic computation: opportunities, challenges and applications",
    "authors": [
      "V Ravi"
    ],
    "first_author_last": "Ravi",
    "year": 2024,
    "venue": "Engineering Research Express",
    "link": "https://iopscience.iop.org/article/10.1088/2631-8695/ad6662/meta",
    "doi": "10.1088/2631-8695/ad6662/meta",
    "cited_by": 15,
    "snippet": "… Nevertheless, utilizing various components, researchers have created memristor … of memristors. There is still room for more research in this field even though the Knowm memristor [38, …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "Abstract The memristor is regarded as one of the promising possibilities for next-generation computing systems due to its small size, easy construction, and low power consumption. Memristor-based novel computing architectures have demonstrated considerable promise for replacing or enhancing traditional computing platforms that encounter difficulties in the big-data era. Additionally, the striking resemblance between the mechanisms governing the programming of memristance and the manipulation of synaptic weight at biological synapses may be used to create unique neuromorphic circuits that function according to biological principles. Nevertheless, getting memristor-based computing into practice presents many technological challenges. This paper reviews the potential for memristor research at the device, circuit, and system levels, mainly using memristors to demonstrate neuromorphic computation. Here, the common issues obstructing the development and widespread use of memristor-based computing systems are also carefully investigated. This study speculates on the prospective applications of memristors, which can potentially transform the field of electronics altogether.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4400870940",
    "relevance": "excluded",
    "review_screen": "unclear",
    "review_reason": "no strong cues",
    "llm_verdict": "not-knowm",
    "llm_confidence": "medium",
    "pdf_knowm": null,
    "knowm_role": null
  },
  {
    "cluster_id": "11965797077951646754",
    "title": "Accelerated image processing through imply-based nocarry approximated adders",
    "authors": [
      "F Seiler",
      "N TaheriNejad"
    ],
    "first_author_last": "Seiler",
    "year": 2024,
    "venue": "IEEE Transactions on Circuits and Systems I Regular Papers",
    "link": "https://ieeexplore.ieee.org/abstract/document/10603404/",
    "doi": "10.1109/tcsi.2024.3426926",
    "cited_by": 20,
    "snippet": "… memristors via switches. We will denote the rows with the a-memristors and the b-memristors … to Table X, which were derived by fitting the model to a real discrete Knowm memristor [49]…",
    "pdf_url": "https://ieeexplore.ieee.org/iel8/8919/4358591/10603404.pdf",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "As the demand for computational power increases drastically, traditional solutions to address those needs struggle to keep up. Consequently, there has been a proliferation of alternative computing paradigms aimed at tackling this disparity. Approximate Computing (AxC) has emerged as a modern way of improving speed, area efficiency, and energy consumption in error-resilient applications such as image processing or machine learning. The trade-off for these enhancements is the loss in accuracy. From a technology point of view, memristors have garnered significant attention due to their low power consumption and inherent non-volatility that makes them suitable for In-Memory Computation (IMC). Another computing paradigm that has risen to tackle the aforementioned disparity between the demand growth and performance improvement. In this work, we leverage a memristive stateful in-memory logic, namely Material Implication (IMPLY). We investigate advanced adder topologies within the context of AxC, aiming to combine the strengths of both of these novel computing paradigms. We present two approximated algorithms for each IMPLY based adder topology. When embedded in an Ripple Carry Adder (RCA), they reduce the number of steps by <inline-formula xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\"> <tex-math notation=\"LaTeX\">$6\\%-54\\%$</tex-math> </inline-formula> and the energy consumption by <inline-formula xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\"> <tex-math notation=\"LaTeX\">$7\\%-54\\%$</tex-math> </inline-formula> compared to the corresponding exact full adders. We compare our work to State-of-the-Art (SoA) approximations at circuit-level, which improves the speed and energy efficiency by up to <inline-formula xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\"> <tex-math notation=\"LaTeX\">$72\\%$</tex-math> </inline-formula> and <inline-formula xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\"> <tex-math notation=\"LaTeX\">$34\\%$</tex-math> </inline-formula> , while lowering the Normalized Median Error Distance (NMED) by up to <inline-formula xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\"> <tex-math notation=\"LaTeX\">$81\\%$</tex-math> </inline-formula> . We evaluate our adders in four common image processing applications, for which we introduce two new test datasets as well. When applied to image processing, our proposed adders can reduce the number of steps by up to <inline-formula xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\"> <tex-math notation=\"LaTeX\">$60\\%$</tex-math> </inline-formula> and the energy consumption by up to <inline-formula xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\"> <tex-math notation=\"LaTeX\">$57\\%$</tex-math> </inline-formula> , while also improving the quality metrics over the SoA in most cases.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://doi.org/10.1109/tcsi.2024.3426926",
    "openalex_id": "https://openalex.org/W4400770655",
    "relevance": "excluded",
    "review_screen": "unclear",
    "review_reason": "no strong cues",
    "llm_verdict": "not-knowm",
    "llm_confidence": "medium",
    "pdf_knowm": null,
    "knowm_role": null
  },
  {
    "cluster_id": "8190491082843136386",
    "title": "Approximated 2-Bit Adders for Parallel In-Memristor Computing With a Novel Sum-of-Product Architecture",
    "authors": [
      "C Simonides",
      "D Gausepohl",
      "PM Hinkel"
    ],
    "first_author_last": "Simonides",
    "year": 2024,
    "venue": "IEEE Journal on Exploratory Solid-State Computational Devices and Circuits",
    "link": "https://ieeexplore.ieee.org/abstract/document/10752571/",
    "doi": "10.1109/jxcdc.2024.3497720",
    "cited_by": 3,
    "snippet": "… data in a nonvolatile fashion, memristors are an increasingly popular … 3,1 as they are fit to a real discrete Knowm memristor [28] … CMOS devices, discrete memristors have higher energy …",
    "pdf_url": "https://ieeexplore.ieee.org/iel8/6570653/7076742/10752571.pdf",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "Conventional computing methods struggle with the exponentially increasing demand for computational power, caused by applications including image processing and machine learning (ML). Novel computing paradigms such as in-memory computing (IMC) and approximate computing (AxC) provide promising solutions to this problem. Due to their low energy consumption and inherent ability to store data in a nonvolatile fashion, memristors are an increasingly popular choice in these fields. There is a wide range of logic forms compatible with memristive IMC, each offering different advantages. We present a novel mixed-logic solution that utilizes properties of the sum-of-product (SOP) representation and propose a full-adder circuit that works efficiently in 2-bit units. To further improve the speed, area usage, and energy consumption, we propose two additional approximate (Ax) 2-bit adders that exhibit inherent parallelization capabilities. We apply the proposed adders in selected image processing applications, where our Ax approach reduces the energy consumption by <inline-formula xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\"> <tex-math notation=\"LaTeX\">$\\mathrm {31~\\!\\%}$ </tex-math></inline-formula>–<inline-formula xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\"> <tex-math notation=\"LaTeX\">$\\mathrm {40~\\!\\%}$ </tex-math></inline-formula> and improves the speed by <inline-formula xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\"> <tex-math notation=\"LaTeX\">$\\mathrm {50~\\!\\%}$ </tex-math></inline-formula>. To demonstrate the potential gains of our approximations in more complex applications, we applied them in ML. Our experiments indicate that with up to <inline-formula xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\"> <tex-math notation=\"LaTeX\">$6/16$ </tex-math></inline-formula> Ax adders, there is no accuracy degradation when applied in a convolutional neural network (CNN) that is evaluated on MNIST. Our approach can save up to 125.6 mJ of energy and 505 million steps compared to our exact approach.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://doi.org/10.1109/jxcdc.2024.3497720",
    "openalex_id": "https://openalex.org/W4404307310",
    "relevance": "excluded",
    "review_screen": "unclear",
    "review_reason": "weak use cues: experiment",
    "llm_verdict": "not-knowm",
    "llm_confidence": "medium",
    "pdf_knowm": null,
    "knowm_role": null
  },
  {
    "cluster_id": "8081620395638804932",
    "title": "Neuromorphic circuit simulation with memristors: Design and evaluation using memtorch for mnist and cifar",
    "authors": [
      "J Souto",
      "G Botella",
      "D García",
      "R Murillo"
    ],
    "first_author_last": "Souto",
    "year": 2024,
    "venue": "arXiv preprint arXiv …",
    "link": "https://arxiv.org/abs/2407.13410",
    "doi": null,
    "cited_by": 8,
    "snippet": "… Commercial Ag/Ge2Se3/SnSe/Ge2Se3 memristors have been characterized experimentally … Characterization and modeling of variability in commercial self-directed channel memristors…",
    "pdf_url": "https://arxiv.org/pdf/2407.13410",
    "is_knowm": false,
    "is_sdc": true,
    "is_mss": true,
    "devices": [],
    "abstract": "Memristors offer significant advantages as in-memory computing devices due to their non-volatility, low power consumption, and history-dependent conductivity. These attributes are particularly valuable in the realm of neuromorphic circuits for neural networks, which currently face limitations imposed by the Von Neumann architecture and high energy demands. This study evaluates the feasibility of using memristors for in-memory processing by constructing and training three digital convolutional neural networks with the datasets MNIST, CIFAR10 and CIFAR100. Subsequent conversion of these networks into memristive systems was performed using Memtorch. The simulations, conducted under ideal conditions, revealed minimal precision losses of nearly 1% during inference. Additionally, the study analyzed the impact of tile size and memristor-specific non-idealities on performance, highlighting the practical implications of integrating memristors in neuromorphic computing systems. This exploration into memristive neural network applications underscores the potential of Memtorch in advancing neuromorphic architectures.",
    "abstract_source": "arxiv",
    "oa_pdf_url": null,
    "openalex_id": null,
    "relevance": "core",
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    "pdf_knowm": "uses-device",
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  },
  {
    "cluster_id": "16563239952849098349",
    "title": "Guest Editorial: Memristive electronic circuits, neural networks and neuromorphic computing",
    "authors": [
      "Y Sun",
      "S Kvatinsky",
      "GC Sirakoulis",
      "J Sun",
      "A Ascoli"
    ],
    "first_author_last": "Sun",
    "year": 2024,
    "venue": "Electronics Letters",
    "link": "https://digital-library.theiet.org/doi/pdf/10.1049/ell2.70092",
    "doi": "10.1049/ell2.70092",
    "cited_by": 0,
    "snippet": "… the Knowm memristor. The authors analyse equilibrium points and stability of the Knowm memristor … The designed Knowm memristor chaotic circuit is implemented and tested with the …",
    "pdf_url": "https://digital-library.theiet.org/doi/pdf/10.1049/ell2.70092",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "The theoretical concept of memristor was first proposed as the fourth basic circuit element by Chua in 1971. It defines the relationship between electric charge and magnetic flux. The first physical implementation of memristor was realised by HP Labs in 2008. It was fabricated in advanced nano technology. Intensive research has since been conducted on the development of memristors across the whole world and wide applications of memristors have also been explored. Since they are smaller nano device, consume less power, and have both memory and processing functions, memristors have been widely recognised to be the future of electronics, computing and AI. For example, they will play a key role in emerging edge computing and brain-like computing. The aim of the Special Issue is to follow the state of the arts of memristor-based circuits and systems, with particular focus on memristive electronic circuits, neural networks and neuromorphic computing, publish original technical papers reflecting the most recent research and application results, and identify new challenges and ways forward for future research and applications in this emerging fast-growing field. A good number of submissions have been received. After rigorous review, six papers have been selected for publication in the Special Issue. These papers cover a wide range of topics in memristive electronic circuits, neural networks and neuromorphic computing. The paper entitled Drift of Invariant Manifolds and Transient Chaos in Memristor Chua's Circuit by Di Marco et al. studies non-linear dynamics of Chua's circuit with a memristor. Transient chaos phenomena are observed in a generalized memristor Chua's circuit where a non-linear resistor is connected in parallel with the memristor to better model a real memristor behaviour. Through the flux-charge analysis method the authors find that the origin of transient chaos is due to the drift of the index of the memristor circuit invariant manifolds caused by the charge flowing into the non-linear resistor. The paper Design of Chaotic Circuit based on Knowm Memristor by Wang et al. presents the model and the corresponding parameter identification of the Knowm memristor and designs a non-linear chaotic circuit based on the Knowm memristor. The authors analyse equilibrium points and stability of the Knowm memristor chaotic circuit and present nonlinear dynamic behaviour by using the bifurcation diagram and Lyapunov exponents. The designed Knowm memristor chaotic circuit is implemented and tested with the experimental results confirming the theoretical predictions. In the paper entitled Dynamic Symmetrization in a Memristive HR Neuron, Huang et al. introduce a memristor as a synapse in the HR neuron to form a memristive HR neuron. The constructed memristive HR neuron with the aid of the absolute value and signum function exhibits attractor doubling and complex coexisting symmetrical firing patterns. The process of attractor doubling or symmetric firing can effectively simulate the discharge phenomena of neuronal polarization and hyperpolarization, providing a useful approach for future research into the diversity of the brain. In the paper entitled Initial State-Dependent Implementation of Logic Gates with Memristive Neurons, Rajki et al. introduce a novel and simple Memristor Cellular Neural Network (M-CNN), consisting of a suitable connection between just two analogue electronics cells, which, exploiting the rich and unique non-linear dynamics of a pair of non-volatile memristors, described through the highly-reliable and predictive physics-based TaOx model from Strachan et al., is capable to carry out the AND, OR, and XOR Boolean logic operations between two binary inputs. The work provides evidence for the add-on functionalities, which memristors endow traditional cellular neural networks (CNNs) with. In fact, while a standard CNN should be re-programmed for each computing task, it were supposed to fulfil, the proposed M-CNN may switch operating mode depending solely upon the resistance states preliminarily written into the respective memristors. Machine learning algorithms are employed to optimize the circuit parameters of the proposed M-CNN so as to turn it into an adaptable logic gate, in which the initial conditions for its memristors determine which Boolean operation from a triplet of options it eventually executes. Taking into account that memristors may also be used to store the intermediate or final results of a computation, besides contributing significantly to the data processing operations, as demonstrated in this work, where they allow multi-tasking in an otherwise single-purpose two-cell array, their use in novel CNN designs promises to pave the way toward the realization of in-memory-computing platforms, which, co-integrated with matrices of sensor elements, form light-weight, low-power and high-spatial resolution visual microprocessors for Edge Computing applications. In the paper 256-Level Honey Memristor Based In-Memory Neuromorphic System by Uppaluru et al., a 256-level honey memristor-based neuromorphic system is proposed and experimentally evaluated for image recognition. The honey memristor-based system is built, and its non-linearity and variation are investigated. Experimental results indicate that the inference accuracy of the system is greater than 88% and 87% without and with cycle-to-cycle variation respectively for different optimization algorithms. The energy and latency performances of optimization algorithms with and without variation are also compared, with the momentum algorithm consistently outperforming the other algorithms. In the paper Nanoscale Ni/Mo/MoO3/Ni Memristor for Synaptic Applications, Praveen et al. propose a physics-based modelling of a nanoscale Ni/Mo/MoO3/Ni memristor. The proposed memristor has stable hysteresis I–V characteristics as well as a significant reduction in forming voltage to 0.75 V. The simulated resistive switching responses show a consistently low coefficient of variability with 14.31% and 14.85% for SET and RESET, respectively during cycle-to-cycle variations along with a low compliance current of 193 µA. In addition to observing synaptic plasticity, how ramprates impact ‘Potentiation’ and ‘Depression’ is also examined as memristor conductance closely relates to synaptic weights. As one of the most important enabling technologies, memristive electronic circuits, neural networks and neuromorphic computing will play a crucial role in the development of future electronics, computing and AI and receive continued focus of research from world-wide academia and industry. We hope that this special issue will stimulate further interest and be useful for those readers who may want to pursue further research in this exciting and fasting growing area. We are grateful to all authors of the papers for their contribution to the special issue. We would also like to thank all reviewers of the papers for their careful and valuable comments. Assistance from the editorial staff at the IET and Wiley is much appreciated. Finally, support from the Editors of IET Electronics Letters and Andrew Harvey, Managing Editor of IET Journals is highly acknowledged. Yichuang Sun received the B.Sc. and M.Sc. degrees from Dalian Maritime University, Dalian, China, in 1982 and 1985, respectively, and the Ph.D. degree from the University of York, York, U.K., in 1996, all in communications and electronics engineering. Dr. Sun is currently a Professor of Communications and Electronics and the Head of Electrical and Electronic Engineering in the School of Physics, Engineering and Computer Science of the University of Hertfordshire, UK. He has published some 450 papers and contributed 10 chapters in edited books. He has also published four text and research books: Continuous-time Active Filter Design (CRC Press, USA, 1999), Design of High-frequency Integrated Analogue Filters (IEE Press, UK, 2002), Wireless Communication Circuits and Systems (IET Press, 2004), and Test and Diagnosis of Analogue, Mixed-Signal and RF Integrated Circuits - The Systems on Chip Approach (IET Press, 2008). His research interests are in the areas of wireless and mobile communications, microelectronic circuits and systems, machine learning and neuromorphic computing. Professor Sun was a series editor of IEE Circuits, Devices and Systems Book Series (2003–2008). He was Associate Editor of IEEE Transactions on Circuits and Systems I: Regular Papers (2010–2011, 2016–2017, 2018–2019). He has also been editor for several other journals, including ETRI Journal, Journal of Sensor and Actuator Networks, Frontiers in Communications and Networks, etc. He was sole or lead Guest Editor of 10 IEEE, IEE/IET and other journal special issues/topics: High-frequency Integrated Analogue Filters in IEE Proc. Circuits, Devices and Systems (2000), RF Circuits and Systems for Wireless Communications in IEE Proc. Circuits, Devices and Systems (2002), Analogue and Mixed-Signal Test for Systems on Chip in IEE Proc. Circuits, Devices and Systems (2004), MIMO Wireless and Mobile Communications in IEE Proc. Communications (2006), Advanced Signal Processing for Wireless and Mobile Communications in IET Signal Processing (2009), Cooperative Wireless and Mobile Communications in IET Communications (2013), Software-Defined Radio Transceivers and Circuits for 5G Wireless Communications in IEEE Transactions on Circuits and Systems-II (2016), Cognitive and AI-enabled Wireless and Mobile Communications in IET Communications (2020), Machine Learning in Communication Systems and Networks in MDPI journals of Applied Sciences, Sensors, Electronics, Photonics, JSAN, and Telecom (2022-24), and Memristive Electronic Circuits, Neural Networks and Neuromorphic Computing in IET Electronics Letters (2023-24). He has also been widely involved in various IEEE Communications and Circuits and System Society technical committee and international conference activities. Professor Sun has been among the World's Top 2% Scientists named by Stanford University in both single year and career lists every year since beginning. Shahar Kvatinsky is a full professor at the Andrew and Erna Viterbi Faculty of Electrical and Computer Engineering, Technion—Israel Institute of Technology and a visiting professor at the Edward S. Rogers Sr. Department of Electrical & Computer Engineering, University of Toronto. Shahar received the B.Sc. degree in Computer Engineering and Applied Physics and an MBA degree in 2009 and 2010, respectively, both from the Hebrew University of Jerusalem, and the Ph.D. degree in Electrical Engineering from the Technion—Israel Institute of Technology in 2014. From 2006 to 2009, he worked as a circuit designer at Intel. From 2014 to 2015, he was a post-doctoral research fellow at Stanford University. Kvatinsky is a member of the Israel Young Academy. He is the head of the Architecture and Circuits Research Center at the Technion, chair of the IEEE Circuits and Systems in Israel, and an editor of Microelectronics Journal and Array. Kvatinsky has been the recipient of numerous awards: the 2023 Uzi & Michal Halevy Award for Innovative Applied Engineering, the 2021 Norman Seiden Prize for Academic Excellence, the 2020 MDPI Electronics Young Investigator Award, the 2019 Wolf Foundation's Krill Prize for Excellence in Scientific Research, the 2015 IEEE Guillemin-Cauer Best Paper Award, the 2015 Best Paper of Computer Architecture Letters, Viterbi Fellowship, Jacobs Fellowship, an ERC starting grant, the 2017 Pazy Memorial Award, 2014, 2017 and 2021 Hershel Rich Technion Innovation Awards, the 2013 Sanford Kaplan Prize for Creative Management in High Tech, 2010 Benin prize, and seven Technion excellence teaching awards. His current research is focused on circuits and architectures with emerging memory technologies and the design of energy-efficient architectures. Georgios Ch. Sirakoulis received the M.Eng. and the Ph.D. degrees in electrical and computer engineering from the Department of Electrical and Computer Engineering, Democritus University of Thrace, Thrace, Greece, in 1996 and 2001, respectively. Since 2018, he has been a professor with the Department of Electrical and Computer Engineering, where he is also serving as head of department from 2020. He has also been a visiting researcher/professor with UWE, U.K., since 2014. Prior to his academic appointment, he was with private sector as a co-founder and research associate of Ulysses Ltd. (1999–2002). He is the author or co-author of more than 160 peer reviewed articles in prestigious international scientific journals and more than 190 peer-reviewed articles in proceedings of international scientific conferences. He has coauthored and co-edited thirteen scientific books (twelve international and one national book) and is the author of 36 chapters in international scientific books. He is an associate editor for well-known magazines in the field of circuits and systems, such as the IEEE Transactions on Nanotechnology (senior editor), IEEE Nanotechnology Magazine, IEEE Trans. On Agrifood Electronics, and in the past IEEE TCAS II, and the IEEE Transactions on Computer, as well as other publishing houses (including Springer Nature, Elsevier, World Scientific, Taylor & Francis, Old House Publishing) and an elected Member of many international and national scientific associations. He has supervised and is supervising 18 doctoral dissertations, 34 postgraduate master theses, and 105 diploma theses, while some of the above dissertations and theses have been awarded by the department, as well as by domestic and international bodies. He was a Coordinator, Principal Investigator, or Scientific Officer/Researcher for more than 35 research projects funded by GSRT, European Union, HFRI, and also by institutions and private companies in Greece and abroad, in research topics related to nanoelectronics, future and emergent electronic-nanoelectronic devices, circuits and architecture, novel computational architecture, applications of complex and intelligent electronic systems in robotics, energy, building evacuation, etc. He has organized many international conferences and workshops, such as IEEE CAFÉ 2024, CNNA 2023, NANOARCH 2019, NANOARCH 2018, PACET 2017, etc. and has delivered invited talks at more than 45 international conferences, workshops, and universities abroad over the last five years. His research interests include future and emergent electronic devices, circuits, models, and architectures including memristors and quantum cellular automata, beyond CMOS computing devices and circuits and non von Neumann computing architectures, unconventional and bioinspired computation/biocomputation, and cellular automata. He is the Vice Chair of the IEEE Task Force on Unconventional Computing, Chair of the IEEE CAS Nano-Giga TC, and Secretary of IEEE CAS CNNAC TC as well VP for Publications for IEEE NTC and IEEE Greece Section Treasurer. Jingru Sun received the B.Sc. degree in Computer Science and Technology from the Department of Computer Science of Changchun University, China, in 2000, the M.Sc. degree in Computer Software and Theory from the Department of Computer Science of Northeastern University, China, in 2004, and the Ph.D. degree in Computer Science and Technology from the College of Computer Science and Electronic Engineering, Hunan University, China, in 2014. Since 2004 she has been with the College of Computer Science and Electronic Engineering, Hunan University, China and is currently an associate professor and a Ph.D. supervisor. From March 2016 to March 2017, she was a visiting scholar in the School of Engineering and Technology at the University of Hertfordshire in the UK. Her research interests include memristive neural networks, brain-like computing, image encryption, and intelligent transportation systems. She has led a team of some ten researchers conducting active research in these areas. Her research projects have been funded by various funding bodies in China including the project on memristor crossbar array based high efficiency in-memory computing logic circuits funded by the National Science Foundation of China. She has published more than 30 papers (two papers are highly cited) in conferences such as IEEE International Symposium on Circuits and Systems and journals including the prestigious IEEE Transactions on Circuits and Systems–I: Regular Papers, IEEE Transactions on Industrial Informatics, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Consumer Electronics, and IEEE Internet of Things Journal. She is a member of the IEEE, the Chinese Computer Society, the Chinese Electronics Society, an executive director of the Hunan Electronics Society in China, and the secretary of the Chaos and Nonlinear Circuit Special Committee of the Chinese Electronics Society. Alon Ascoli (Senior Member, IEEE) received the Italian Habilitation as full professor in Electrical Circuit Theory from the Italian Ministry of Education in 2023, the German Habilitation as full professor in Nonlinear Circuit Theory from Technische Unversität Dresden, Dresden, Germany, in 2022, the Italian Habilitation as Associate Professor in Electrical Circuit Theory from the Italian Ministry of Education in 2017, a Ph.D. degree in Electronic Engineering from University College Dublin, Dublin, Ireland, in 2006, and a Master of Science Degree (First Class Honours) in Electronic Engineering from Universita’ degli Studi Roma Tre, Rome, Italy, in 2001. He was a Visiting Research Scholar at the University of California Santa Cruz, Santa Cruz, California, USA, in 2019. Since December 2023 he is an Associate Professor at the Department of Electronics and Telecommunications of Politecnico di Torino, Turin, Italy. He was affiliated with Technische Universität Dresden from December 2012 to November 2023, where he held a lifelong position since 2018. He develops theoretical concepts enabling to harness disruptive nanotechnologies to overcome traditional circuits’ limitations for applications of interest to the more-than-Moore electronics era as well as to improve our understanding of the complex behaviours of biological systems, including the mechanisms underlying emergent phenomena in neuronal cells. In 2007, Prof. Ascoli was honoured with the International Journal of Circuit Theory and Applications (IJCTA) Best Paper Award for the manuscript the dynamics of In 2020 he was the Best Paper Award on Electronics at the International on Circuits and Systems for the manuscript cellular with and analogue dynamic model for an switching In 2023, he was awarded the Best Paper Award from IEEE Transactions on Circuits and Systems for the manuscript to a Memristive for Signal He was the Chair of the Memristor and Memristive held in Italy, in He was one of the at NANOARCH He has organized Special on Theory and Applications of Memristor Circuits, and Systems in IEEE 2018, 2019, 2022, and 2023, in IEEE 2019, 2022, and 2023, in 2017, and in 2022, 2023, and 2024, in IEEE 2022, and in IEEE 2023 and He has as for the IEEE Circuits and Systems Society School on in Memristive & Computing from to the 2022, he as a for the IEEE Circuits and Systems Society School on in Integrated and Memristive He as the of the IEEE CAS Cellular Nanoscale Networks and Computing TC from 2019 to He was the of the IEEE Circuits and Systems Society Cellular Nanoscale Networks and Memristor Computing Committee from 2021 to He has been a member of the Chua Memristor Center since Since he has been a member of the IEEE and Systems Committee Since 2023 he is a member of the Italian Society for Chaos and with which he was affiliated from 2013 to He has been an associate editor for IEEE since March Since 2024, he is a member of the IEEE Nonlinear Circuits and Systems new data or the theoretical Drift of Invariant Manifolds and Transient Chaos in Memristor Chua's Di and Design of Chaotic Circuit based on Knowm Wang and Wang Dynamic Symmetrization in a Memristive HR and Initial State-Dependent Implementation of Logic Gates with Memristive Alon and 256-level Honey Memristor Based In-Memory Neuromorphic and Wang Nanoscale Ni/Mo/MoO3/Ni Memristor for Synaptic and",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://onlinelibrary.wiley.com/doi/pdfdirect/10.1049/ell2.70092",
    "openalex_id": "https://openalex.org/W4404363361",
    "relevance": "cites",
    "review_screen": null,
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    "pdf_knowm": "cites",
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  },
  {
    "cluster_id": "2wkLYe7E6VEJ",
    "title": "Several trigger circuit designs based on memristors",
    "authors": [
      "J WU",
      "W JIANG",
      "Y ZHONG",
      "Y DIAO"
    ],
    "first_author_last": "WU",
    "year": 2024,
    "venue": "Experimental Technology and …",
    "link": "https://www.sciopen.com/article/10.16791/j.cnki.sjg.2024.07.003",
    "doi": "10.16791/j.cnki.sjg.2024.07.003",
    "cited_by": 0,
    "snippet": "… on the mean metastable switch memristor model (Knowm), specifically SR, D, T, and JK triggers. By fully leveraging the unique characteristics of memristors, such as resistance state …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": true,
    "devices": [],
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": null,
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
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    "knowm_role": "uses-knowm-device",
    "human_verdict": "uses-knowm-device",
    "human_reason": "YES (user)"
  },
  {
    "cluster_id": "7199414328623125484",
    "title": "Ultrafast vision perception by neuromorphic optical flow",
    "authors": [
      "S Wang",
      "S Gao",
      "T Pu",
      "L Zhao",
      "A Nathan"
    ],
    "first_author_last": "Wang",
    "year": 2024,
    "venue": "Authorea Preprints",
    "link": "https://www.techrxiv.org/doi/full/10.36227/techrxiv.172668496.67162401",
    "doi": "10.36227/techrxiv.172668496.67162401",
    "cited_by": 0,
    "snippet": "… self-directed channel (SDC) memristor (KNOWM Inc.) is selected for constructing motion pattern processing circuit. In the initial operation, Ge2Se3/Ag/Ge2Se3 … a self-directed channel is …",
    "pdf_url": "https://www.techrxiv.org/doi/pdf/10.36227/techrxiv.172668496.67162401",
    "is_knowm": true,
    "is_sdc": true,
    "is_mss": true,
    "devices": [],
    "abstract": "Optical flow is crucial for robotic visual perception, yet current methods primarily operate in a 2D format, capturing movement velocities only in horizontal and vertical dimensions. This limitation results in incomplete motion cues, such as missing regions of interest or detailed motion analysis of different regions, leading to delays in processing high-volume visual data in real-world settings. Here, we report a 3D neuromorphic optical flow method that leverages the time-domain processing capability of memristors to embed external motion features directly into hardware, thereby completing motion cues and dramatically accelerating the computation of movement velocities and subsequent task-specific algorithms. In our demonstration, this approach reduces visual data processing time by an average of 0.3 seconds while maintaining or improving the accuracy of motion prediction, object tracking, and object segmentation. Interframe visual processing is achieved for the first time in UAV scenarios. Furthermore, the neuromorphic optical flow algorithm's flexibility allows seamless integration with existing algorithms, ensuring broad applicability. These advancements open unprecedented avenues for robotic perception, without the trade-off between accuracy and efficiency.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://www.techrxiv.org/doi/pdf/10.36227/techrxiv.172668496.67162401",
    "openalex_id": "https://openalex.org/W4402592147",
    "relevance": "cites",
    "review_screen": "unclear",
    "review_reason": "no strong cues",
    "llm_verdict": "not-knowm",
    "llm_confidence": "medium",
    "pdf_knowm": "cites",
    "knowm_role": "cites"
  },
  {
    "cluster_id": "4632694548747360129",
    "title": "Design of chaotic circuit based on Knowm memristor",
    "authors": [
      "F Wang",
      "F Wang"
    ],
    "first_author_last": "Wang",
    "year": 2024,
    "venue": "Electronics Letters",
    "link": "https://ietresearch.onlinelibrary.wiley.com/doi/abs/10.1049/ell2.13294",
    "doi": "10.1049/ell2.13294",
    "cited_by": 6,
    "snippet": "… the structure of Knowm memristor in [15]. In [16], Knowm memristors doping with carbon or … parameters of Knowm memristor are obtained through optimization and comparison. In [17], …",
    "pdf_url": "https://ietresearch.onlinelibrary.wiley.com/doi/pdf/10.1049/ell2.13294",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "Abstract Most previous works in the field of nonlinear memristive chaotic systems mainly focus on non‐material memristor while seldom on material memristor. In this letter, the model and the corresponding parameter identification of the Knowm memristor is presented. The chaotic circuit based on the Knowm memristor is designed. Equilibrium points and stability of this Knowm‐memristor‐based chaotic system is analyzed. Nonlinear dynamic behavior is presented by the bifurcation diagram and Lyapunov exponents. Finally, the hardware circuit of this Knowm‐memristor‐based chaotic system is designed and the experimental results are presented for confirmation.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://onlinelibrary.wiley.com/doi/pdfdirect/10.1049/ell2.13294",
    "openalex_id": "https://openalex.org/W4401194598",
    "relevance": "cites",
    "review_screen": "unclear",
    "review_reason": "weak use cues: experimental, experiment",
    "pdf_knowm": "cites",
    "knowm_role": "cites"
  },
  {
    "cluster_id": "EjXrbQTAfxgJ",
    "title": "Preassigned-Time Stabilization of Memristive Chaotic Circuit via Switching Control",
    "authors": [
      "Q Wang",
      "L Wang",
      "W Qin"
    ],
    "first_author_last": "Wang",
    "year": 2024,
    "venue": "International Conference on …",
    "link": "https://ieeexplore.ieee.org/abstract/document/10987761/",
    "doi": "10.1109/icnc64304.2024.10987761",
    "cited_by": 0,
    "snippet": "… 1) This paper considers the KNOWM memristor model to make the memristive chaotic circuit more realistic. 2) A switching controller is designed to achieve preassigned-time stability of …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "In this paper, we propose a 3D memristive chaotic circuit, in which both its dynamical behaviors and the preassigned-time stability are analyzed. First, we design a chaotic circuit utilizing the KNOWM memristor model, and confirm the presence of chaos through phase portrait. Subsequently, we develop a switching controller, which successfully achieves the preassigned-time stability of the memristive chaotic circuit. Ultimately, the validity of our theoretical findings is substantiated through rigorous numerical simulations.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4410492707",
    "relevance": "cites",
    "review_screen": "unclear",
    "review_reason": "no strong cues",
    "pdf_knowm": "cites",
    "knowm_role": "cites"
  },
  {
    "cluster_id": "2959098378488021442",
    "title": "Crossbar array based on tri-valued memristors: its design and application.",
    "authors": [
      "X Wang",
      "X Bao",
      "X Li",
      "X Chen",
      "G Liu"
    ],
    "first_author_last": "Wang",
    "year": 2024,
    "venue": "Nonlinear Dynamics",
    "link": "https://openurl.ebsco.com/contentitem/gcd:179690635?sid=ebsco:plink:crawler-gcd&id=ebsco:gcd:179690635&crl=c&jrnl=0924090X",
    "doi": "10.1007/s11071-024-10126-8",
    "cited_by": 8,
    "snippet": "… a tri-valued memristor with two binary memristors. Trivalued-memristor-based crossbar … The designed circuits are verified by LTSpice simulation using the Knowm memristor model. …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": "https://link.springer.com/content/pdf/10.1007/s11071-024-10126-8.pdf",
    "openalex_id": "https://openalex.org/W4401510175",
    "relevance": "cites",
    "review_screen": "no-abstract",
    "review_reason": "no abstract — manual check",
    "pdf_knowm": "cites",
    "knowm_role": "cites"
  },
  {
    "cluster_id": "9847136610487983692",
    "title": "Design method for unbalanced ternary logic family based on binary memristors",
    "authors": [
      "X Wang",
      "Y Sun",
      "J Zhou",
      "X Chen",
      "SM Kang",
      "HHC Iu"
    ],
    "first_author_last": "Wang",
    "year": 2024,
    "venue": "Nonlinear Dynamics",
    "link": "https://link.springer.com/article/10.1007/s11071-024-09402-4",
    "doi": "10.1007/s11071-024-09402-4",
    "cited_by": 7,
    "snippet": "… The memristor models used in this paper are the Knowm … PMOS transistors with corresponding threshold voltages and Knowm memristor models. The resulting waveforms are shown in …",
    "pdf_url": "https://www.researchsquare.com/article/rs-3593161/latest.pdf",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "This paper proposes a design method for unbalanced ternary logic family based on hybrid design of binary memristors and CMOS transistors, building on the foundational positive ternary logic circuits. By using the symmetry of negative and positive ternary logics, negative ternary TAND, TOR, TI, 1-3 decoder and 2-9 decoder are derived from the previously designed positive ternary basic logic gate circuits. Furthermore, negative ternary XOR, XNOR, 3-1 encoder and 9-2 encoder are design-improved. For the first time, unbalanced ternary priority encoders are proposed, including a 3-1 priority encoder and a 9-2 priority encoder, of which the former is implemented with only seven memristors. The functionalities of these circuits are demonstrated through LTSpice simulations. Finally, hardware experiments were performed on a stable 20 ×\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$\\times $$\\end{document} 20 ZnO-based resistive switch array. Subsequent design of more complex digital logic circuits can benefit from this work.",
    "abstract_source": "semanticscholar",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4392818364",
    "relevance": "cites",
    "review_screen": "likely-cite-only",
    "review_reason": "cite/other-device cues: ltspice, spice, simulation",
    "pdf_knowm": "cites",
    "knowm_role": "cites"
  },
  {
    "cluster_id": "13428637361142687735",
    "title": "Memristor-based adaptive neuromorphic perception in unstructured environments",
    "authors": [
      "S Wang",
      "S Gao",
      "C Tang",
      "E Occhipinti",
      "C Li"
    ],
    "first_author_last": "Wang",
    "year": 2024,
    "venue": "Nature Communications",
    "link": "https://www.nature.com/articles/s41467-024-48908-8",
    "doi": "10.1038/s41467-024-48908-8",
    "cited_by": 59,
    "snippet": "… S1) is assembled for receiving pressure amplitudes, and a self-directed channel effect-based multilayered nonvolatile memristor (KNOWM Inc.) is selected for differential neuromorphic …",
    "pdf_url": "https://www.nature.com/articles/s41467-024-48908-8.pdf",
    "is_knowm": true,
    "is_sdc": true,
    "is_mss": false,
    "devices": [],
    "abstract": "Efficient operation of control systems in robotics or autonomous driving targeting real-world navigation scenarios requires perception methods that allow them to understand and adapt to unstructured environments with good accuracy, adaptation, and generality, similar to humans. To address this need, we present a memristor-based differential neuromorphic computing, perceptual signal processing, and online adaptation method providing neuromorphic style adaptation to external sensory stimuli. The adaptation ability and generality of this method are confirmed in two application scenarios: object grasping and autonomous driving. In the former, a robot hand realizes safe and stable grasping through fast ( ~ 1 ms) adaptation based on the tactile object features with a single memristor. In the latter, decision-making information of 10 unstructured environments in autonomous driving is extracted with an accuracy of 94% with a 40×25 memristor array. By mimicking human low-level perception mechanisms, the electronic neuromorphic circuit-based method achieves real-time adaptation and high-level reactions to unstructured environments.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://www.nature.com/articles/s41467-024-48908-8.pdf",
    "openalex_id": "https://openalex.org/W4399203358",
    "relevance": "cites",
    "review_screen": "unclear",
    "review_reason": "no strong cues",
    "llm_verdict": "not-knowm",
    "llm_confidence": "medium",
    "pdf_knowm": "cites",
    "knowm_role": "cites"
  },
  {
    "cluster_id": "8659057012884912419",
    "title": "A balanced CMOS compatible ternary memristor-NMOS logic family and its application",
    "authors": [
      "X Wang",
      "X Chen",
      "J Zhou",
      "G Liu"
    ],
    "first_author_last": "Wang",
    "year": 2024,
    "venue": "IEEE Transactions on Circuits and Systems I Regular Papers",
    "link": "https://ieeexplore.ieee.org/abstract/document/10638758/",
    "doi": "10.1109/tcsi.2024.3441852",
    "cited_by": 17,
    "snippet": "… possible inputs for TMIN and TMAX using the KNOWM memristor model [36]… memristors. For example, for three-input TMIN and TMAX, we can simply increase the number of memristors …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "Balanced ternary digital logic circuits based on memristors and MOSFET devices are introduced. First, balanced ternary minimum gate TMIN, maximum gate TMAX and ternary inverters are designed and verified by simulation. Next, logic circuits such as ternary encoders, decoders and multiplexers are designed using these three basic gates. For further validation, a ternary 3–1 encoder was hardware-implemented successfully using in-house fabricated memristors and MOS transistors. Two different design approaches, namely the decoder-based method and the multiplexer-based method are introduced and applied to realize combinational logic circuits such as balanced ternary half-adder, multiplier, and numerical comparator. We simulate the circuits using 50nm CMOS technology parameters and BSIM models and present comparisons and analyses of the two design methods in view of the power consumption and component device counts, which can guide subsequent research and development of integrated multi-valued logic circuits. The decoder-based method has advantages both in terms of component numbers and power consumption, but the multiplexer-based method has the advantages of being based on a simple operating principle and ease of implementation.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4401691896",
    "relevance": "cites",
    "review_screen": "unclear",
    "review_reason": "weak use cues: i-v",
    "llm_verdict": "not-knowm",
    "llm_confidence": "high",
    "pdf_knowm": "cites",
    "knowm_role": "cites"
  },
  {
    "cluster_id": "12946162128328366917",
    "title": "Elementary cellular automata realized by stateful three-memristor logic operations",
    "authors": [
      "H Wang",
      "J Wang",
      "S Yan",
      "R Pan",
      "M Sun",
      "Q Yu"
    ],
    "first_author_last": "Wang",
    "year": 2024,
    "venue": "Scientific Reports",
    "link": "https://www.nature.com/articles/s41598-024-53125-w",
    "doi": "10.1038/s41598-024-53125-w",
    "cited_by": 2,
    "snippet": "… of the memristor model employed in this … memristor model proposed by Knowm Inc 23 and closely resemble the switching behaviors of a memristor like the Au/\\(\\rm HfO_2\\)/Ni memristor …",
    "pdf_url": "https://www.nature.com/articles/s41598-024-53125-w.pdf",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "Cellular automata (CA) are computational systems that exhibit complex global behavior arising from simple local rules, making them a fascinating candidate for various research areas. However, challenges such as limited flexibility and efficiency on conventional hardware platforms still exist. In this study, we propose a memristor-based circuit for implementing elementary cellular automata (ECA) by extending the stateful three-memristor logic operations derived from material implication (IMP) logic gates. By leveraging the inherent physical properties of memristors, this approach offers simplicity, minimal operational steps, and high flexibility in implementing ECA rules by adjusting the circuit parameters. The mathematical principles governing circuit parameters are analyzed, and the evolution of multiple ECA rules is successfully demonstrated, showcasing the robustness in handling the stochastic nature of memristors. This approach provides a hardware solution for ECA implementation and opens up new research opportunities in the hardware implementation of CA.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://www.nature.com/articles/s41598-024-53125-w.pdf",
    "openalex_id": "https://openalex.org/W4391435713",
    "relevance": "cites",
    "review_screen": "likely-cite-only",
    "review_reason": "cite/other-device cues: we propose a memristor",
    "pdf_knowm": "cites",
    "knowm_role": "cites"
  },
  {
    "cluster_id": "12272229883818237608",
    "title": "Self-reconfigurable multifunctional memristive nociceptor for intelligent robotics",
    "authors": [
      "S Wang",
      "M Fang",
      "L Song",
      "C Li",
      "J Zhang"
    ],
    "first_author_last": "Wang",
    "year": 2024,
    "venue": "Neuromorphic Computing and Engineering",
    "link": "https://iopscience.iop.org/article/10.1088/2634-4386/ad93f8/meta",
    "doi": "10.1088/2634-4386/ad93f8/meta",
    "cited_by": 2,
    "snippet": "… , for the first time, a self-directed channel memristor-based self-reconfigurable nociceptor, … for the memristor. The maximum difference ratio of the response of memristors at different …",
    "pdf_url": "https://iopscience.iop.org/article/10.1088/2634-4386/ad93f8/pdf",
    "is_knowm": false,
    "is_sdc": true,
    "is_mss": false,
    "devices": [],
    "abstract": "Abstract Artificial nociceptors, mimicking human-like stimuli perception, are of significance for intelligent robotics to work in hazardous and dynamic scenarios. One of the most essential characteristics of the human nociceptor is its self-adjustable attribute, which indicates that the threshold of determination of a potentially hazardous stimulus relies on environmental knowledge. This critical attribute has been currently omitted, but it is highly desired for artificial nociceptors. Inspired by these shortcomings, this article presents, for the first time, a self-directed channel memristor-based self-reconfigurable nociceptor, capable of perceiving hazardous pressure stimuli under different temperatures and demonstrates key features of tactile nociceptors, including ‘threshold,’ ‘no-adaptation,’ and ‘sensitization.’ The maximum amplification of hazardous external stimuli is 1000%, and its response characteristics dynamically adapt to current temperature conditions by automatically altering the generated modulation schemes for the memristor. The maximum difference ratio of the response of memristors at different temperatures is 500%, and this adaptability closely mimics the functions of biological tactile nociceptors, resulting in accurate danger perception in various conditions. Beyond temperature adaptation, this memristor-based nociceptor has the potential to integrate different sensory modalities by applying various sensors, thereby achieving human-like perception capabilities in real-world environments.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://doi.org/10.1088/2634-4386/ad93f8",
    "openalex_id": "https://openalex.org/W4404471039",
    "relevance": "cites",
    "review_screen": "likely-use",
    "review_reason": "use cues: self-directed",
    "pdf_knowm": "cites",
    "knowm_role": "cites"
  },
  {
    "cluster_id": "11280494591409778658",
    "title": "An Analytical Study of the Impact of Data Flow on Electromagnetic Compatibility",
    "authors": [
      "S Yadav",
      "R Tiwari",
      "AK Marandi"
    ],
    "first_author_last": "Yadav",
    "year": 2024,
    "venue": "2nd International …",
    "link": "https://ieeexplore.ieee.org/abstract/document/10531575/",
    "doi": "10.1109/aimla59606.2024.10531575",
    "cited_by": 0,
    "snippet": "… The Knowm SDC Memristor The Knowm SDC Memristor consists of a number of additives that paint collectively to permit data to float among extraordinary components. A skinny film …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": true,
    "is_mss": false,
    "devices": [],
    "abstract": "This paper offers an analytical examine of the effect of facts waft on electromagnetic compatibility (EMC). The analysis is primarily based on a 3-dimensional (3D) version of a single hyperlink between two nodes in a circuit within an electronic machine. The link consists of coupled transmission lines connected to two nodes characterized by an electromagnetic area. The version considers the presence of information transmitted at a certain frequency and section along the hyperlink. By way of reading the interplay between the electromagnetic field and the records that go with the flow, the impact of the information drift at the EMC is quantified. The results of the a look display the dynamic conduct of the link whilst subjected to distinct statistics transfer frequencies and depth ranges. It’s far tested that the statistics waft affects the propagation of the electromagnetic waves and, therefore, the EMC of the hyperlink. The implications of the effects on the layout of sign flow for EMC’s overall performance are likewise mentioned.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4398164450",
    "relevance": "excluded",
    "review_screen": "unclear",
    "review_reason": "weak use cues: characteriz",
    "llm_verdict": "not-knowm",
    "llm_confidence": "high",
    "pdf_knowm": null,
    "knowm_role": null
  },
  {
    "cluster_id": "2585134133898979105",
    "title": "A lightweight cnn based on memristive stochastic computing for electronic nose",
    "authors": [
      "B Yang",
      "T Chen",
      "A Chen",
      "S Duan"
    ],
    "first_author_last": "Yang",
    "year": 2024,
    "venue": "International Journal of Bifurcation and Chaos",
    "link": "https://www.worldscientific.com/doi/abs/10.1142/S0218127424500275",
    "doi": "10.1142/S0218127424500275",
    "cited_by": 2,
    "snippet": "… In this paper, we use the Knowm memristor, which is a self-directed channel memristor [… 1 is shown by feeding a 1.8V, 500ms wide pulse into a Knowm memristor. It can be seen …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": true,
    "is_mss": false,
    "devices": [],
    "abstract": "Gas detection plays different roles in different environments. Traditional algorithms implemented on electronic nose for gas detection and recognition have high complexity and cannot resist device drift. In response to the above issues, we propose a convolutional neural network based on memristive Stochastic Computing (SC), which combines the characteristics of small devices and low power consumption of memristor devices, as well as the fast and fault-tolerant random calculation speed. It can effectively utilize hardware advantages, recognizing gases by electronic nose. The experimental results show that for two different gas sensor array datasets, the accuracy of the proposed method can achieve the level of 99%. When using memristive SC for deduction, the accuracy decreases by less than 1%, but in drift data, the accuracy can be improved by about 3%. Finally, the improvement in area, power, and energy compared to inference in GPU (NVIDIA Geforce RTX 3060 Laptop) is 1104X, 48X, and 9X, respectively.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4392558612",
    "relevance": "excluded",
    "review_screen": "unclear",
    "review_reason": "weak use cues: experimental, experiment",
    "llm_verdict": "not-knowm",
    "llm_confidence": "medium",
    "pdf_knowm": null,
    "knowm_role": null
  },
  {
    "cluster_id": "0YEhpDpLERAJ",
    "title": "Simulation and Analysis of Basic Characteristics of Several Memristor Mathematical Models",
    "authors": [
      "X Yuan",
      "T Li",
      "Z Li",
      "K Su",
      "C Wang"
    ],
    "first_author_last": "Yuan",
    "year": 2024,
    "venue": "9th International …",
    "link": "https://ieeexplore.ieee.org/abstract/document/10593720/",
    "doi": "10.1109/icetis61828.2024.10593720",
    "cited_by": 0,
    "snippet": "… , and emulators of memristor to its applications in … memristor chips are available on the market. In 2015, the American company Knowm designed the world's first real Knowm memristor, …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "The memristor is fundamental electrical element predicated by Chua in 1971 and fabricated by HP Labs in 2008. However, there are few physical memristors can be used as commercial components so far. In this case, mathematical models and emulators which can imitate the features of the memristor are meaningful for further research. This article simulates the basic I-V characteristics of several common memristor mathematical models to verify three fingerprints of memristors and analyzes the local activity.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4400946933",
    "relevance": "excluded",
    "review_screen": "likely-cite-only",
    "review_reason": "cite/other-device cues: emulator, mathematical model",
    "pdf_knowm": null,
    "knowm_role": null,
    "human_verdict": "not-knowm",
    "human_reason": "NO (user)"
  },
  {
    "cluster_id": "12470817603630122341",
    "title": "Twin-T Network Oscillator Based on Knowm Memristors",
    "authors": [
      "L Zhang",
      "X Xiao"
    ],
    "first_author_last": "Zhang",
    "year": 2024,
    "venue": "6th International Conference on …",
    "link": "https://ieeexplore.ieee.org/abstract/document/10704244/",
    "doi": "10.1109/ecnct63103.2024.10704244",
    "cited_by": 1,
    "snippet": "… real memristors is still relatively small. This paper uses real memristors from Knowm Inc. … network sine wave generator based on memristors was implemented. The research results …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "As a new type of nonlinear circuit element, the memristor has a wide range of applications, but the research using real memristors is still relatively small. This paper uses real memristors from Knowm Inc. Through theoretical simulation and hardware experimentation, a Twin-T network sine wave generator based on memristors was implemented. The research results indicate that the Twin-T network oscillator based on Knowm memristors can change the output signal frequency in a simple and stable manner. Addressing the original circuit's difficulty in adjusting output frequency.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4403278555",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "named-in-abstract"
  },
  {
    "cluster_id": "16405143714183502874",
    "title": "A memristor-based Liénard Oscillator design",
    "authors": [
      "K Çakır",
      "R Mutlu",
      "E Karakulak"
    ],
    "first_author_last": "Çakır",
    "year": 2024,
    "venue": "… of the Faculty of Engineering and …",
    "link": "https://www.researchgate.net/profile/Kuebra_Cakir5/publication/387550173_Memristor_tabanli_bir_Lienard_Osilatoru_tasarimi/links/67751664fb9aff6eaafc27a8/Memristoer-tabanli-bir-Lienard-Osilatoerue-tasarimi.pdf",
    "doi": null,
    "cited_by": 3,
    "snippet": "… by using two Carbon Knowm memristors connected in antiparallel … The carbon memristor-based Lienard oscillator simulation … in this study, Karbon Knowm memristors connected to the …",
    "pdf_url": "https://www.researchgate.net/profile/Kuebra_Cakir5/publication/387550173_Memristor_tabanli_bir_Lienard_Osilatoru_tasarimi/links/67751664fb9aff6eaafc27a8/Memristoer-tabanli-bir-Lienard-Osilatoerue-tasarimi.pdf",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": null,
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "11757718950766421587",
    "title": "Memristör tabanlı bir Liénard Osilatörü tasarımı",
    "authors": [
      "K Çakır",
      "R Mutlu",
      "E Karakulak"
    ],
    "first_author_last": "Çakır",
    "year": 2024,
    "venue": "Gazi Üniversitesi Mühendislik-Mimarlık Fakültesi Dergisi",
    "link": "https://dergipark.org.tr/en/pub/gazimmfd/article/1273399?issue_id=87996",
    "doi": "10.17341/gazimmfd.1273399",
    "cited_by": 4,
    "snippet": "… by using two Carbon Knowm memristors connected in antiparallel … The carbon memristor-based Lienard oscillator simulation … in this study, Karbon Knowm memristors connected to the …",
    "pdf_url": "https://dergipark.org.tr/en/download/article-file/3045131",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "Yeni devre elemanı memristör sensör yapımında, hücresel sinir ağları, kaotik sistemler, programlanabilir analog devreler, kalıcı bellek cihazları gibi devre uygulamalarında kullanılabilmektedir. 1928’de salınımlı devrelerin modellenmesi için Alfred-Marie Liénard tarafından Liénard denklemleri önerilmiştir. İlk Liénard Osilatörü yapıldığında yarı iletken teknolojisi mevcut değildi ancak günümüzde çeşitli yarı iletken devre elemanları yeni tür Liénard Osilatörlerinin yapımında kullanılmaktadır. Günümüzde Knowm firmasının ürettiği ve piyasada satılan Karbon tabanlı memristörler mevcuttur. Yapılan literatür çalışmasına göre, henüz yapılmış Karbon Knowm memristör tabanlı bir Liénard Osilatörü bulunmamaktadır. Bu çalışmanın amacı iki adet Karbon tabanlı Knowm memristör kullanarak literatüre yeni bir Liénard Osilatör çeşidi kazandırmaktır. Bu çalışmada önce memristör tabanlı bir Liénard Osilatörü devre topolojisi önerilmiş, devreyi tanımlayan denklemler verilmiş, ardından Karbon tabanlı bir memristör entegresi kullanılarak devre kurulmuş ve kurulan osilatör üzerinde gerçekleştirilen deneyler sayesinde literatürde bir ilk olarak iki tane ters-paralel bağlı Karbon Knowm memristör kullanarak bir Liénard Osilatörü yapılabileceği gösterilmiştir.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://dergipark.org.tr/tr/download/article-file/3045131",
    "openalex_id": "https://openalex.org/W4405913035",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "Sr0M-6RNS3QJ",
    "title": "Advancing AI Hardware with SDC Memristors: A Review of Multibit Storage, Thermal Resilience, and Dynamic Simulation Strategies",
    "authors": [
      "KA Athina",
      "S Meenakshi",
      "GK Bharathi"
    ],
    "first_author_last": "Athina",
    "year": 2025,
    "venue": "10th …",
    "link": "https://ieeexplore.ieee.org/abstract/document/11336321/",
    "doi": "10.1109/icces67310.2025.11336321",
    "cited_by": 0,
    "snippet": "… for 2D material-based memristors, are examined, alongside … time memristor simulation, proposing AI-assisted modeling frameworks, and highlighting the potential of SDC memristors for …",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": true,
    "is_mss": false,
    "devices": [],
    "abstract": "This work investigates the modeling and simulation of Self-Directed Channel (SDC) memristors to address limitations of traditional CMOS scaling and enhance next-generation memory systems for edge-AI and neuromorphic computing. The research objective is to explore advanced simulation techniques for accurately capturing SDC memristor behavior under dynamic, real-time conditions. The methodology includes a comprehensive review of memristor modeling approaches, ranging from conventional Verilog-A and SPICEbased methods to AI-driven adaptive simulation frameworks such as Physics-Informed Neural Networks (PINNs), pulsedriven resistance control, and noise modeling. Advanced simulation techniques, including TCAD, kinetic Monte Carlo, and sub-nanosecond transient modeling for 2D material-based memristors, are examined, alongside hardware-software cosimulation concepts. Key findings show that AI-enhanced models and dynamic control via smart memory controllers significantly improve predictive accuracy and real-time adaptability, while current digital proof environments lack integrated pulseadaptive simulation capabilities. The primary contributions of this work include identifying research gaps in real-time memristor simulation, proposing AI-assisted modeling frameworks, and highlighting the potential of SDC memristors for reliable multibit storage, dynamic resistance tuning, and analog computing in compute-in-memory architectures.",
    "abstract_source": "semanticscholar",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W7125531346",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "named-in-abstract"
  },
  {
    "cluster_id": "5100824743948883879",
    "title": "A SPICE model calibration framework for egg albumin memristors",
    "authors": [
      "H Choudhury",
      "RV Gautam",
      "R Goswami"
    ],
    "first_author_last": "Choudhury",
    "year": 2025,
    "venue": "Physica Scripta",
    "link": "https://iopscience.iop.org/article/10.1088/1402-4896/adbd84/meta",
    "doi": "10.1088/1402-4896/adbd84/meta",
    "cited_by": 0,
    "snippet": "… • This article uses the Knowm memristor model for SPICE level … Knowm Memristor model equations … constant is an important parameter in tuning the Knowm memristor model. …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "Abstract Memristors which emulate synaptic behaviour are key components in neuromorphic computing; yet, incorporating biological materials into their design presents challenges. Despite progress, a full understanding of bio-memristor electrical characteristics remains unexplored, prompting further analysis through SPICE modelling. This article proposes a calibrated SPICE-level framework for fabricated egg albumin memristors, with its parameters tuned to match experimental data, enabling replication of the device’s current–voltage behaviour. This work provides experimental insights, guidelines for calibration, and examines how variation in the SPICE model parameters influence device characteristics.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4408177727",
    "relevance": "excluded",
    "review_screen": "likely-cite-only",
    "review_reason": "cite/other-device cues: spice model, spice",
    "pdf_knowm": null,
    "knowm_role": null,
    "human_verdict": "not-knowm",
    "human_reason": "NO (user)"
  },
  {
    "cluster_id": "14461227431430844450",
    "title": "A Multi-Mode Configurable Physical Unclonable Function Based on RRAM With Adjustable Programmable Voltage",
    "authors": [
      "Y Cui",
      "J Li",
      "C Gu",
      "C Wang",
      "W Liu"
    ],
    "first_author_last": "Cui",
    "year": 2025,
    "venue": "IEEE Transactions on Nanotechnology",
    "link": "https://ieeexplore.ieee.org/abstract/document/10930800/",
    "doi": "10.1109/tnano.2025.3552433",
    "cited_by": 4,
    "snippet": "… top metal electrodes, the self-directed channel (SDC) based … to a chemically engineered channel structure, with changes in … temperature model of self-directed channel memristor,” in …",
    "pdf_url": "https://pure.qub.ac.uk/files/636894914/A_Multi-Mode_Configurable_Physical_Unclonable_Function_Based_on_RRAM_With_Adjustable_Programmable_Voltage.pdf",
    "is_knowm": false,
    "is_sdc": true,
    "is_mss": false,
    "devices": [],
    "abstract": "Resistive random access memory (RRAM) presents a promising solution for energy-efficient logic-in-memory (LiM) systems. This paper introduces a Multi-mode Configurable Physical Unclonable Function (MC-PUF) tailored for secure RRAM-based LiM applications, utilizing a conventional one-transistor-one-RRAM (1T1R) array. The MC-PUF operates in multiple modes by modifying the programming voltages of the RRAM, which captures the distinct variations of each RRAM under varying conditions. In weak write mode, the MC-PUF exploits the inherent variations of RRAM by setting the programming voltages to achieve a 50% switching probability, thereby randomly assigning ‘0’ or ‘1’ states. In parallel competition mode, it generates responses by selecting two parallel RRAMs, with one remaining in a high resistance state (HRS) and the other switching to a low resistance state (LRS). This configuration allows the MC-PUF to generate more challenge-response pairs (CRPs) compared to conventional designs, thus enhancing security through increased entropy. The design was validated through simulations using a compact Spice model and the UMC 55 nm CMOS library, as well as on an experimental hardware platform with commercial RRAM chips. Results from both simulations and hardware implementations indicate that the proposed MC-PUF exhibits high reliability, excellent uniqueness, and superior configurability.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://pure.qub.ac.uk/en/publications/9d62e1af-5e88-41d6-abea-8209fe117a3c",
    "openalex_id": "https://openalex.org/W4408564081",
    "relevance": "excluded",
    "review_screen": "likely-cite-only",
    "review_reason": "cite/other-device cues: spice model, spice, simulation",
    "pdf_knowm": null,
    "knowm_role": null,
    "human_verdict": "not-knowm",
    "human_reason": "NO (user)"
  },
  {
    "cluster_id": "10137002194340834174",
    "title": "High-Speed and Low-Cost In-Array Memristive Multipliers using SIXOR and TMSL Logics",
    "authors": [
      "RR Disfani",
      "M Valinataj"
    ],
    "first_author_last": "Disfani",
    "year": 2025,
    "venue": "IEEE Transactions on Nanotechnology",
    "link": "https://ieeexplore.ieee.org/abstract/document/10981683/",
    "doi": "10.1109/tnano.2025.3566272",
    "cited_by": 1,
    "snippet": "… It should be noted that these parameters are obtained by fitting the VTEAM model to our measurements [39] of Knowm “BSAF-W” discrete memristors [40]. In addition, the considered …",
    "pdf_url": "https://eclectx.org/Publications/J39.pdf",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": true,
    "devices": [],
    "abstract": "Memristive systems have many promising features, making them suitable for both storage and computation. Memristors can perform logical operations and they can be used as the basic structures in digital circuits such as adders and multipliers. In this paper, at first, a new fast and low-cost Full- Adder (FA) is proposed using Single-cycle In-memristor XOR (SIXOR) and Three Memristors Stateful Logic (TMSL) gates that benefits from the advantages of both logics. Then, the proposed FA is used as one of the basic units inside two new array multipliers. The first proposed multiplier is designed in such a way that it has the lowest computational steps (delay) among the existing designs. This design has on average around 70% lower delay compared to the existing designs. The second proposed multiplier, as the low-cost design, requires a very low number of memristors thanks to reusing the existing resources more efficiently, while still having a low delay. This multiplier achieves on average around 36% memristor reduction compared to the state-of-the-art multipliers. Based on the analysis, both proposed array multipliers have notable efficiency advantages compared to the state-of-the-art designs based on different Figures of Merit (FoMs). For example, based on the balanced FoM, in which the number of computational steps and the number of required memristors have equal weight, the first and the second proposed multipliers achieve up to 4.6× and 14.9× improvements, respectively, compared to the existing designs in 64-bit multiplication.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4409991074",
    "relevance": "cites",
    "review_screen": "unclear",
    "review_reason": "no strong cues",
    "llm_verdict": "not-knowm",
    "llm_confidence": "medium",
    "pdf_knowm": "cites",
    "knowm_role": "cites"
  },
  {
    "cluster_id": "15029989142440597758",
    "title": "Event-based simulation of stochastic memristive devices for neuromorphic computing",
    "authors": [
      "W El-Geresy",
      "C Papavassiliou"
    ],
    "first_author_last": "El-Geresy",
    "year": 2025,
    "venue": "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems",
    "link": "https://ieeexplore.ieee.org/abstract/document/11154857/",
    "doi": "10.1109/tcad.2025.3607670",
    "cited_by": 2,
    "snippet": "… memristors - the Generalised Metastable Switch Model (GMSM… One general memristor model that includes stochasticity as a … the memristor as a number of parallel metastable switches, …",
    "pdf_url": "https://arxiv.org/pdf/2407.04718",
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": true,
    "devices": [],
    "abstract": "In this paper, we build a general modelling framework for memristors, suitable for the simulation of event-based systems such as hardware spiking neural networks, and more generally, neuromorphic computing systems composed of three independent components: i) an event-based modelling approach, extending and generalising an existing general model of memristors - the Generalised Metastable Switch Model (GMSM) [1] - eliminating errors associated with discrete time approximation, as well as offering potential improvements in terms of suitability for neuromorphic memristive system simulations; ii) a volatility state variable to allow for the unified understanding of disparate non-linear and volatile phenomena, including state relaxation, structural disruption, Joule heating, and non-linear drift in different memristive devices; and iii) a readout equation that separates the latent state variable evolution from explicit variables of interest such as an instantaneous resistance. We exhibit an illustrative implementation of this framework, fit to a resistive drift dataset for titanium dioxide memristors, based on a proposed linear conductance model for resistive drift in the devices. Finally, we highlight the application of the model to neuromorphic computing, through demonstrating the contribution of the volatility state variable to switching dynamics, resulting in frequency-dependent switching (for stable memristors acting as programmable synaptic weights) and the generation of action potentials (for unstable memristors, acting as spike-generators).",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4414166005",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-model",
    "knowm_role": "uses-model"
  },
  {
    "cluster_id": "462350266604007755",
    "title": "Energy-Information Trade-Off in Self-Directed Channel Memristors",
    "authors": [
      "W El–Geresy",
      "D Hajtó",
      "G Cserey"
    ],
    "first_author_last": "El–Geresy",
    "year": 2025,
    "venue": "IEEE 35th …",
    "link": "https://ieeexplore.ieee.org/abstract/document/11204291/",
    "doi": "10.1109/mlsp62443.2025.11204291",
    "cited_by": 0,
    "snippet": "… on Self-Directed Channel (SDC) memristors, which are one of the few types of memristors … a tungsten doped device, with a thin-layer structure, including a Ge2Se3 active layer [12]. …",
    "pdf_url": "https://arxiv.org/pdf/2508.16236",
    "is_knowm": false,
    "is_sdc": true,
    "is_mss": true,
    "devices": [],
    "abstract": "Understanding the nature of information storage on memristors is vital to enable their use in novel data storage and neuromorphic applications. One key consideration in information storage is the energy cost of storage and what impact the available energy has on the information capacity of the devices. In this paper, we propose and study an energyinformation trade-off for a particular kind of memristive device - Self-Directed Channel (SDC) memristors. We perform experiments to model the energy required to set the devices into various states, as well as assessing the stability of these states over time. Based on these results, we employ a generative modelling approach, using a conditional Generative Adversarial Network (cGAN) to characterise the storage conditional distribution, allowing us to estimate energyinformation curves for a range of storage delays, showing the graceful trade-off between energy consumed and the effective capacity of the devices.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://arxiv.org/pdf/2508.16236",
    "openalex_id": "https://openalex.org/W4415524254",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "12834392771986641657",
    "title": "Testing the SDC memristors in three phase systems",
    "authors": [
      "B Garda",
      "K Bednarz"
    ],
    "first_author_last": "Garda",
    "year": 2025,
    "venue": "PRZEGLĄD ELEKTROTECHNICZNY",
    "link": "https://yadda.icm.edu.pl/baztech/element/bwmeta1.element.baztech-5b8f0238-7270-49d8-9f82-974a55ca40e1",
    "doi": "10.15199/48.2025.02.13",
    "cited_by": 0,
    "snippet": "… known as SDC memristors, described in [8, 9]. Memristor SDCs can be doped with various metals, and in this work tungsten-doped memristors were used. To reduce the current, all …",
    "pdf_url": "https://yadda.icm.edu.pl/baztech/element/bwmeta1.element.baztech-5b8f0238-7270-49d8-9f82-974a55ca40e1/c/13_garda_testing_2_2025.pdf",
    "is_knowm": false,
    "is_sdc": true,
    "is_mss": false,
    "devices": [],
    "abstract": "Wydawnictwo SIGMA-NOT wydaje czasopisma fachowe informujące swoich czytelników o najnowszych osiągnięciach naukowych i nowoczesnych rozwiązaniach technicznych w Polsce i na świecie, popularyzuje problemy techniczne oraz poszerza wiedzę i kulturę techniczną.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4407920737",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "named-in-abstract"
  },
  {
    "cluster_id": "1893359412270228032",
    "title": "Realistic behavioral model for ReRAMs capturing non-idealities",
    "authors": [
      "G Gulafshan",
      "H Hu",
      "D Raber-Radakovits"
    ],
    "first_author_last": "Gulafshan",
    "year": 2025,
    "venue": "Communications Materials",
    "link": "https://www.nature.com/articles/s43246-025-00807-1",
    "doi": "10.1038/s43246-025-00807-1",
    "cited_by": 4,
    "snippet": "… data collected from two memristor types: vacuum-processed self-directed channel (SDC) memristors and inkjet-printed electrochemical metallization (ECM) memristors. The simulated …",
    "pdf_url": "https://www.nature.com/articles/s43246-025-00807-1.pdf",
    "is_knowm": false,
    "is_sdc": true,
    "is_mss": false,
    "devices": [],
    "abstract": "Abstract Memristors are a class of emerging electronic devices for in-memory computation systems, which promise to overcome the von Neumann bottleneck in traditional computer architectures. Simulation plays a critical role in designing circuits for memristive in-memory computation systems. Fast and reliable simulations require a behavioral model that accurately emulates device characteristics, accounting for real-world non-idealities. In this work, we present a memristor behavioral model that incorporates key non-idealities, including cycle-to-cycle and device-to-device resistance variations, threshold voltage variations, resistance drift in the absence of external stimulus and variations in switching dynamics. The model has been fitted to experimental data from two types of real devices: vacuum-processed self-directed channel memristors and inkjet-printed electrochemical metallization memristors, showing good agreement with both datasets. This model is used to simulate memristive stateful logic gates. Our study highlights the significance of considering device non-idealities in the practical design of memristive circuits.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://www.nature.com/articles/s43246-025-00807-1.pdf",
    "openalex_id": "https://openalex.org/W4410211689",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "2395968868180259635",
    "title": "State characterisation of self-directed channel memristive devices",
    "authors": [
      "D Hajtó",
      "W El-Geresy",
      "D Gündüz"
    ],
    "first_author_last": "Hajtó",
    "year": 2025,
    "venue": "Engineering Research Express",
    "link": "https://iopscience.iop.org/article/10.1088/2631-8695/ae2421&quot",
    "doi": "10.1088/2631-8695/ae2421&quot",
    "cited_by": 0,
    "snippet": "… term ‘memristor’ to refer to such resistive switching memories … (the number of metastable switches), n the switches in the ON … x · G m which models the Generalised MSS memristive state. …",
    "pdf_url": "https://arxiv.org/pdf/2505.15757",
    "is_knowm": false,
    "is_sdc": true,
    "is_mss": true,
    "devices": [],
    "abstract": "Abstract Understanding how to reliably use memristors as information storage devices is crucial not only to their role as emerging memories, but also for their application in neural network acceleration and as components of novel neuromorphic systems. Understanding how to characterise and measure the state of memristors is important to enable us to use the devices effectively for these applications. To this end, in this paper, we propose a general, physics-inspired modelling approach for characterising the state of self-directed channel (SDC) memristors. Additionally, to enable the identification of the proposed state from device data, we introduce a noise-aware approach to the minimum-variance estimation of the state from voltage and current pairs.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4416659784",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "76Ew_xj3pukJ",
    "title": "Design and Application of Memristor-CMOS Ternary Comparator",
    "authors": [
      "J Huang"
    ],
    "first_author_last": "Huang",
    "year": 2025,
    "venue": "7th International Conference on Electronic …",
    "link": "https://ieeexplore.ieee.org/abstract/document/11334851/",
    "doi": "10.1109/eei67650.2025.11334851",
    "cited_by": 0,
    "snippet": "… Leveraging the Knowm memristor model, this work introduces a compact ternary comparator design where the output directly maps logic levels 0, 1, and 2 to the relations less than, …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "As CMOS scaling nears its physical limitations, binary logic circuits face increasing challenges in meeting the requirements of high-density, low-power, and fast computing. Multi-valued logic (MVL), especially ternary logic, provides superior coding efficiency and device utilization. Leveraging the Knowm memristor model, this work introduces a compact ternary comparator design where the output directly maps logic levels 0,1, and 2 to the relations less than, equal to, and greater than. This direct encoding removes auxiliary modules, thereby reducing circuit complexity and improving performance. A two-digit extension is further demonstrated to validate scalability. LTSpice simulations confirm the proposed design achieves low power, high speed, and CMOS compatibility, offering a promising candidate for next-generation computing architectures.",
    "abstract_source": "semanticscholar",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W7125597023",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "uses-knowm-device",
    "human_verdict": "uses-knowm-device",
    "human_reason": "YES: abstract says Knowm"
  },
  {
    "cluster_id": "3304533650378281151",
    "title": "What are Memelements: Memristor, Memcapacitor and Meminductor?",
    "authors": [
      "A Isah"
    ],
    "first_author_last": "Isah",
    "year": 2025,
    "venue": "Journal of Sustainable Engineering and Technology",
    "link": "https://joset.com.ng/index.php/home/article/view/57",
    "doi": null,
    "cited_by": 1,
    "snippet": "… Self-Directed Channel (SDC) memristor chips are commercially available online by KNOWM Inc. [17]. Unlike the TiO2 memristor, SDC memristors achieve their resistive switching by the …",
    "pdf_url": "https://joset.com.ng/index.php/home/article/download/57/24",
    "is_knowm": true,
    "is_sdc": true,
    "is_mss": false,
    "devices": [],
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": null,
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "11802042596177700644",
    "title": "CMOS-Based Memristor Emulator Circuit for Audio Signal Processing in Hearing Aid Applications",
    "authors": [
      "R Jayachandran",
      "SS Kumar"
    ],
    "first_author_last": "Jayachandran",
    "year": 2025,
    "venue": "Devices for …",
    "link": "https://ieeexplore.ieee.org/abstract/document/11012243/",
    "doi": "10.1109/devic63749.2025.11012243",
    "cited_by": 2,
    "snippet": "… Knowm Inc., a leading company in memristor technology, has developed integrated circuits with arrays of memristors [7… memristor emulator circuits essential for exploring the potential of …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "Hearing aids require efficient a nd a daptive audio signal processing to improve sound quality and intelligibility of speech for users. This paper presents the basic building block of an audio processing system using a CMOS-based memristor emulator circuit designed for hearing aid applications. The proposed emulator implemented using SCL 180 nm technology library replicates the behavior of a memristor. The simulation results demonstrate the effectiveness of the circuit in building spiking voltage generation similar to that of a biological neuron with minimal power consumption. In this work, the memristive integrate and firing n euron ( MIF) c ell i s d emonstrated i n 180 nm technology, 1.8 V supply voltage, operating frequency upto 100 MHz with a power consumption of less than 1 mW is demonstrated in Cadence Virtuoso tool. Including CMOS-based memristor emulators into hearing aids can lead to significant advancements in adaptive sound processing, ultimately improving the auditory experience for users.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4410853228",
    "relevance": "excluded",
    "review_screen": "likely-cite-only",
    "review_reason": "cite/other-device cues: emulator, simulation",
    "pdf_knowm": null,
    "knowm_role": null,
    "human_verdict": "not-knowm",
    "human_reason": "NO (user)"
  },
  {
    "cluster_id": "12555639185189165429",
    "title": "Memristor-Based Logical Gates and Schemes for Artificial Intelligence",
    "authors": [
      "SM Kirilov",
      "VM Mladenov"
    ],
    "first_author_last": "Kirilov",
    "year": 2025,
    "venue": "14th International Conference …",
    "link": "https://ieeexplore.ieee.org/abstract/document/11083900/",
    "doi": "10.1109/mocast65744.2025.11083900",
    "cited_by": 1,
    "snippet": "… This paper offers simple memristor-… memristor model is proposed for the related analyses. It is tuned according experimental iv relations of Self-directed channel Knowm memristors. A …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": true,
    "is_mss": false,
    "devices": [],
    "abstract": "Memristors are innovative elements in the nanorange, having good commutating and memory features, small energy usage, and a compatibility to CMOS technology of integrated circuits. Memory crossbars, neural nets, and many other schemes are some of their potential applications. This paper offers simple memristor-based logical gates for artificial intelligence, analyzed in LTSPICE and MATLAB. A plain and fast-operating modified memristor model is proposed for the related analyses. It is tuned according experimental <tex xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\">$i-v$</tex> relations of Self-directed channel Knowm memristors. A correct operation of considered logic functions is confirmed by the obtained results. During the analyses, several mainly used standard and modified memristor models are applied for comparison of their operation and properties. The suggested memristor-based logic gates are a significant step towards manufacturing of complex logic functions and schemes for artificial intelligence integrated circuits with ultra-high-density.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4412560849",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "15576293287245056857",
    "title": "LTSPICE Memristor Neuron with a Modified Transfer Function Based on Memristor Model with Parasitic Parameters",
    "authors": [
      "S Kirilov",
      "V Mladenov"
    ],
    "first_author_last": "Kirilov",
    "year": 2025,
    "venue": "Electronics",
    "link": "https://www.mdpi.com/2079-9292/14/23/4645",
    "doi": "10.3390/electronics14234645",
    "cited_by": 1,
    "snippet": "… One of the Knowm memristors is randomly selected for the investigations. A … to the memristor element. It is applied for restricting the memristor current and for protection of the memristor …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "Memristors, as novel one-port electronic elements, have very good memory and commutating properties, insignificant power consumption, and a good compatibility to present CMOS integrated chips. They are applicable in neural networks, memory arrays, and various electronic devices. This paper proposes a simple LTSPICE model of an adapted activation function and a neuron built on memristors. In the neuron, synaptic bonds are implemented by single memristors, allowing a decreased circuit complexity. The summing and scaling schemes are based on op-amps and memristors. The applied modified tangent-sigmoidal activation function is implemented with MOS transistors and memristors. Analyses and simulations are conducted using a simple and high-rate operating memristor model with parasitic parameters—resistance, inductance, capacitance, and small-signal DC components. Their influence on the normal operation of the memristors in the neuron is analyzed, paying attention to their usage and adjustment. The proposed memristor-based artificial neuron is analyzed in MATLAB–Simulink and LTSPICE simulators. A comparison between the derived results confirms the correct operation of the proposed memristor neuron. The generation and analyses of the suggested memristor-based neuron is a significant and promising step for the design and engineering of high-complexity neural networks and their realization in ultra-high-density integrated neural circuits and chips.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://doi.org/10.3390/electronics14234645",
    "openalex_id": "https://openalex.org/W4416722050",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-knowm-device",
    "human_verdict": "uses-knowm-device",
    "human_reason": "YES (user): PDF provided"
  },
  {
    "cluster_id": "12358862782916674734",
    "title": "New ternary decoders using hybrid memristor-MOS logic",
    "authors": [
      "R Kumar",
      "BC Nagar"
    ],
    "first_author_last": "Kumar",
    "year": 2025,
    "venue": "International Journal of Electronics and Telecommunications",
    "link": "https://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2025.153596",
    "doi": "10.24425/ijet.2025.153596",
    "cited_by": 1,
    "snippet": "… a hybrid memristor-MOS-based digital circuit [23]. This paper adopts the KNOWM memristor model [… The memristor model specifications used in the literature are given in Table. III. The …",
    "pdf_url": "https://ijet.pl/index.php/ijet/article/download/10.24425-ijet.2025.153596/3009",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "Integrating memristor technology with traditional CMOS has led to innovative designs for ternary logic, significantly enhancing the performance and efficiency of digital integrated circuits. This hybrid approach takes advantage of the unique properties of memristors, including low power consumption, compact size, and non-volatility, to develop ternary logic circuits that outperform conventional binary systems in terms of area and energy efficiency. This article presents two new low-power ternary decoders designed using a hybrid memristor- MOS logic approach. The decoders were simulated and analyzed using SPICE, and their performance was compared with existing circuits. The results indicate that the power-efficient decoder uses 44.44% fewer transistors and dissipates 97.78% less power than previously documented circuits.",
    "abstract_source": "openalex",
    "oa_pdf_url": "http://journals.pan.pl/Content/135273/19_5035_L_Kumar_sk_new.pdf",
    "openalex_id": "https://openalex.org/W4411065492",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-model",
    "knowm_role": "uses-model"
  },
  {
    "cluster_id": "4062554955218595618",
    "title": "A Low-Power and Reliable RRAM-Based Configurable RO PUF With Aging Resilience",
    "authors": [
      "J Li",
      "Y Cui",
      "C Wang",
      "C Gu",
      "W Liu"
    ],
    "first_author_last": "Li",
    "year": 2025,
    "venue": "IEEE Transactions on Nanotechnology",
    "link": "https://ieeexplore.ieee.org/abstract/document/10999056/",
    "doi": "10.1109/tnano.2025.3569071",
    "cited_by": 1,
    "snippet": "… The three-layer Ge2Se3/Ag/Ge2Se3 mix during deposition and … the top electrode, the self-directed channel of SDC RRAM is … [22] KA Campbell, “Self-directed channel memristor for …",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": true,
    "is_mss": true,
    "devices": [],
    "abstract": "Emerging nano-device resistive random access memories (RRAMs) have become a promising primitive for PUF designs due to their non-volatility, high density, and low power, breaking through the physical limitations. A ring oscillator based physical unclonable function (RO PUF) is one of the most widely studied PUF designs due to its resilience against noise impacts and flexibility of implementation, but its reliability is susceptible to environmental variation and device aging. Present solutions to improve RO PUF reliability either require complicated RO selection algorithms or require discarding a large number of unstable challenge-response pairs (CRPs). This paper presents a highly reliable RRAM-based configurable RO PUF (RCRO-PUF). The proposed RCRO-PUF utilizes the intrinsic variations of RRAMs as the randomness source and applies the resistance variations of RRAMs to the frequency difference of current-starved (CS) ROs. By operating CS inverters in the subthreshold region, the RCRO-PUF achieves low power as well as high reliability. In addition, a reliability enhancement scheme is proposed to eliminate the effects of environmental variations and device aging. Based on Monte Carlo simulations of a 65 nm CMOS process, the proposed RCRO-PUF consumes only 16.18% of the hardware overhead for a regular RO PUF and has only 7.43 <inline-formula xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\"><tex-math notation=\"LaTeX\">$\\mu W$</tex-math></inline-formula> per CRP generation. The reliability of the RCRO-PUF is 99.51% over a broad range of temperatures from -50 <inline-formula xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\"><tex-math notation=\"LaTeX\">$^{\\circ }$</tex-math></inline-formula>C to 150 <inline-formula xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\"><tex-math notation=\"LaTeX\">$^{\\circ }$</tex-math></inline-formula>C and <inline-formula xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\"><tex-math notation=\"LaTeX\">$\\pm$</tex-math></inline-formula>20% supply voltage variations. It is also 4.7× more resilient to aging than state-of-the-art aging-resilient RO PUF.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4410294807",
    "relevance": "excluded",
    "review_screen": "unclear",
    "review_reason": "no strong cues",
    "llm_verdict": "not-knowm",
    "llm_confidence": "high",
    "pdf_knowm": null,
    "knowm_role": null
  },
  {
    "cluster_id": "HlYlG_qc4PwJ",
    "title": "Application of a Four-Dimensional Memristive Hopfield Neural Network in Image Encryption",
    "authors": [
      "Y Li",
      "H Gao",
      "J Lin"
    ],
    "first_author_last": "Li",
    "year": 2025,
    "venue": "IEEE 5th International Conference on …",
    "link": "https://ieeexplore.ieee.org/abstract/document/11349920/",
    "doi": "10.1109/icdsca67083.2025.11349920",
    "cited_by": 0,
    "snippet": "… advance the study of physical memristor devices [1,2], such as metal oxide memristors, ferroelectric tunnel … , silver-silicon composite memristors, tantalum oxide memristors, and Knowm …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "An image encryption algorithm based on a four-dimensional memristive Hopfield neural network is designed in this paper. The encrypted and decrypted images are obtained through experiments. Security analyses, including histogram analysis, adjacent pixel correlation analysis, and resistance to noise attacks, are conducted on the encryption algorithm. The results demonstrate the effectiveness and reliability of the proposed image encryption algorithm. The design leverages the intrinsic properties of memristors, which are characterized by memory, resistance, and nonlinearity, and are widely employed in research concerning neural networks, nonlinear systems, and digital circuits. The integration of memristors with chaotic systems is utilized to enhance the complexity and unpredictability of the system, thereby contributing to improved security in data processing. Consequently, the application of this memristor-based chaotic system in image encryption is recognized as a method that not only enriches the diversity of encryption algorithms but also fulfills the demand for randomness and diffusivity in the encryption process. As a result, the security of the algorithm is effectively strengthened, and an efficient encryption and decryption procedure is realized.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W7126064677",
    "relevance": "excluded",
    "review_screen": "unclear",
    "review_reason": "weak use cues: experiment, characteriz",
    "llm_verdict": "not-knowm",
    "llm_confidence": "medium",
    "pdf_knowm": null,
    "knowm_role": null
  },
  {
    "cluster_id": "5748966215750019620",
    "title": "Experimental Evaluation of Memristor-Enhanced Analog Oscillators: Relaxation and Wien-Bridge Cases",
    "authors": [
      "LM Lopez-Jimenez",
      "E Tlelo-Cuautle"
    ],
    "first_author_last": "Lopez-Jimenez",
    "year": 2025,
    "venue": "Dynamics",
    "link": "https://www.mdpi.com/2673-8716/5/4/43",
    "doi": "10.3390/dynamics5040043",
    "cited_by": 6,
    "snippet": "… This study examined how to add a physical memristor from Knowm Inc. to two well-known analog oscillator circuits: the relaxation oscillator and the Wien-bridge oscillator. This process …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "This paper presents two classic analog oscillators: a relaxation oscillator and a Wien bridge one, where a memristor replaces a resistor. The circuits are simulated in TopSPICE 7.12 using a memristor emulation circuit and commercially available components to evaluate the memristor’s impact. In the case of the relaxation oscillator, which includes the memristor, a notable increase in oscillation frequency was observed compared to the classical circuit, with a nearly 10-fold increase from 790 Hz to 7.78 kHz while maintaining a constant amplitude. This confirms the influence of the memristor’s dynamic resistance on the circuit time constant. On the other hand, the Wien-bridge oscillator exhibits variations in specific parameters, such as peak voltage, amplitude, and frequency. In this case, the oscillation frequency decreased from 405 Hz to 146 Hz with the addition of the memristor, a characteristic introduced by the proposed memristive element’s nonlinear interactions. Experimental results confirm the feasibility of incorporating memristors into classical oscillator circuits, enabling frequency changes while maintaining stable oscillations, allowing reconfigurable and adaptable analog designs that leverage the properties of memristive devices.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://www.mdpi.com/2673-8716/5/4/43/pdf?version=1759311164",
    "openalex_id": "https://openalex.org/W4414701085",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-knowm-device",
    "human_verdict": "uses-knowm-device",
    "human_reason": "YES (user): PDF provided"
  },
  {
    "cluster_id": "9553344578783758339",
    "title": "Analog Building Blocks: VDIBA And CDBA Based Energy-Efficient High-Speed Memristor Emulator For Neuromorphic Applications",
    "authors": [
      "G Mandal",
      "M Ghosh",
      "P Mondal"
    ],
    "first_author_last": "Mandal",
    "year": 2025,
    "venue": "IEEE Open Journal of Nanotechnology",
    "link": "https://ieeexplore.ieee.org/abstract/document/11175600/",
    "doi": "10.1109/ojnano.2025.3613007",
    "cited_by": 1,
    "snippet": "… Among them, only the KNOWM memristor [15] is commercially available but has specific operational requirements [16]. Despite advances, physical realization challenges have led to …",
    "pdf_url": "https://ieeexplore.ieee.org/iel8/8782713/9036065/11175600.pdf",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "In the field of neuromorphic computing, there is a growing need for high-frequency memristor emulators, especially for pattern recognition, image classification, and edge detection. A high-frequency memristor-based neural network can enhance synaptic weight updates and accelerate learning. This article presents an innovative memristor emulator circuit using CMOS-based building blocks: the Voltage Differencing Inverting Buffered Amplifier (VDIBA) and the Current Differencing Buffered Amplifier (CDBA). Our design achieves a maximum operating frequency of 60MHz with a power consumption of only 2.25 mW. The memristor emulator is resistorless, electronically tunable, and functions in both grounded and floating configurations, as well as in incremental and decremental modes. We provide an analysis of transient behavior and voltage-current (V-I) characteristics, along with assessments of robustness and adaptability under various conditions. This memristor emulator is tailored for Adaptive Neural Networks (ANN) to mimic biological behavior and for Memristive Integrated-and-Fire (MIF) neuron circuits to replicate biological neurons, all developed using 180nm CMOS technology. The proposed design has also been verified using ICs CA3080, LT1193, and AD844.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://doi.org/10.1109/ojnano.2025.3613007",
    "openalex_id": "https://openalex.org/W7083000878",
    "relevance": "excluded",
    "review_screen": "likely-cite-only",
    "review_reason": "cite/other-device cues: emulator",
    "pdf_knowm": null,
    "knowm_role": null,
    "human_verdict": "not-knowm",
    "human_reason": "NO (user)"
  },
  {
    "cluster_id": "12268368432109133005",
    "title": "Strategies to Finding Optimal Parameters for Plasticity Changes in Memristor-Based Systems for Neuromorphic Data Computing",
    "authors": [
      "T Mazur",
      "G Abdi",
      "A Sławek",
      "E Cechosz",
      "K Szaciłowski"
    ],
    "first_author_last": "Mazur",
    "year": 2025,
    "venue": "BioNanoScience",
    "link": "https://link.springer.com/article/10.1007/s12668-025-02027-w",
    "doi": "10.1007/s12668-025-02027-w",
    "cited_by": 2,
    "snippet": "… Additionally, we employed bipolar triangle pulses in STDP tests on KNOWM memristors, positioning them as suitable processing units for neural-like network systems such as ANNs, …",
    "pdf_url": "https://link.springer.com/content/pdf/10.1007/s12668-025-02027-w.pdf",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "Abstract Current publication highlights exemplary commercially available memristive chips, capable of replicating processing nodes found in artificial neural networks and reservoirs. These hardware components can become foundational elements of neuromorphic computing. To achieve this, several pre-defined node-to-node connection strength modulation effects must be integrated into a potential system-on-a-chip. KNOWM memristors exhibit many of these effects, including potential-dependent potentiation-depression behavior. The results from our preliminary tests, which identify optimal electric parameters for achieving strong and consistent synaptic responses, serve as a basis for research into more complex phenomena, such as spike-rate-dependent plasticity (SRDP) and spike-time-dependent plasticity (STDP). To advance the development of information processing systems that incorporate novel materials, it is essential to establish universal testing and benchmarking protocols. As material-based neural networks are anticipated to play a significant role in future computational tasks, these protocols will ensure consistent and comparable performance assessments across various memristive systems. The proposed methodology offers a cost-effective and accessible approach to benchmarking in this emerging field.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://link.springer.com/content/pdf/10.1007/s12668-025-02027-w.pdf",
    "openalex_id": "https://openalex.org/W4411284126",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "HVumEiUyFtsJ",
    "title": "From simulation to reality: experimental analysis of a quantum entanglement simulation with slime molds (Physarum polycephalum) as bioelectronic components",
    "authors": [
      "E Miranda"
    ],
    "first_author_last": "Miranda",
    "year": 2025,
    "venue": "Frontiers in Soft Matter",
    "link": "https://researchportal.plymouth.ac.uk/en/publications/from-simulation-to-reality-experimental-analysis-of-a-quantum-ent/",
    "doi": "10.3389/frsfm.2025.1588404",
    "cited_by": 0,
    "snippet": "… theoretical memristor models, physical memristors (from Knowm … While the simulation with theoretical memristor models has … Although the physical memristor produced IV diagrams that …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "This study investigates whether it is possible to simulate quantum entanglement with theoretical memristor models, physical memristors (from Knowm Inc.) and slime molds Physarum polycephalum as bioelectric components. While the simulation with theoretical memristor models has been demonstrated in the literature, real-world experiments with electric and bioelectric components had not been done so far. Our analysis focused on identifying hysteresis curves in the voltage-current (I-V) relationship, a characteristic signature of memristive devices. Although the physical memristor produced I-V diagrams that resembled more or less hysteresis curves, the small parasitic capacitance introduced significant problems for the planned entanglement simulation. In case of the slime molds, and unlike what was reported in the literature, the I-V diagrams did not produce a memristive behavior and thus could not be used to simulate quantum entanglement. Finally, we designed replacement circuits for the slime mold and suggested alternative uses of this bioelectric component.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://www.frontiersin.org/journals/soft-matter/articles/10.3389/frsfm.2025.1588404/pdf",
    "openalex_id": "https://openalex.org/W4414925245",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "NmqjOI-WuhkJ",
    "title": "Transmission Delay Analysis Based on Memristor Gate Circuits",
    "authors": [
      "X Pan",
      "X Xiao"
    ],
    "first_author_last": "Pan",
    "year": 2025,
    "venue": "4th International Conference on …",
    "link": "https://ieeexplore.ieee.org/abstract/document/11099812/",
    "doi": "10.1109/eicct65471.2025.11099812",
    "cited_by": 0,
    "snippet": "… This paper is based on the Knowm memristor model, utilizing LTspice simulation software to … physical Knowm memristors, circuits were connected using Dupont wires on a PCB board …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "Memristors, as emerging nonlinear devices, exhibit great potential in implementing digital logic circuits. This paper is based on the Knowm memristor model, utilizing LTspice simulation software to simulate and verify basic logic gates. Physical memristor devices are used for testing, and the results of simulations and experiments are compared and analyzed. Frequency analysis is conducted on the propagation delay of logic gates. The study compares and analyzes differences and their causes through multi-dimensional and multi-faceted approaches. It theoretically elaborates on the frequency characteristics and physical mechanisms of the propagation delay in memristor logic gates, aiding in better utilization of the frequency characteristics of memristors and providing a reference for the design of memristor logic gates in the future.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4413018218",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "named-in-abstract"
  },
  {
    "cluster_id": "4095911885680247727",
    "title": "Latch and Flip-Flop Design Using Memristors and Transmission Gates with Timer Counter Implementation",
    "authors": [
      "A Rayer",
      "M Ganesh",
      "L Tanwar"
    ],
    "first_author_last": "Rayer",
    "year": 2025,
    "venue": "10th International …",
    "link": "https://ieeexplore.ieee.org/abstract/document/10967986/",
    "doi": "10.1109/icsc64553.2025.10967986",
    "cited_by": 1,
    "snippet": "… The paper used another memristor model named Knowm memristor model and TSMC 180nm technology node files to implement the NOR gate and using that gate a D latch using …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "Memristors are a combination of the words Memory and Resistor, it never forgets. It is a passive element which remembers the amount of current that flowed through it and is small in size. All these qualities of a memristor make it highly advantageous and useful in the upcoming times for chip manufacturing and designing. Latches are sequential circuits using them in master-slave configuration a flip flop can be generated which is highly useful in applications such as counters, registers, etc. In this paper we implement a Modified version of D-latch and flip flop using memristors and Transmission gates to improve the switching speed and to obtain full voltage swing. Further we show a comparative analysis of proposed modified D-latch and flip-flop with an earlier method along with a timer counter as an application of the D-flip flop circuit. Paper also explains the challenges of using MRL gates in complex circuits. TEAM model of memristor and 180nm technology node files are used in simulation of all the circuits using Cadence Virtuoso.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4409763350",
    "relevance": "excluded",
    "review_screen": "unclear",
    "review_reason": "no strong cues",
    "llm_verdict": "not-knowm",
    "llm_confidence": "high",
    "pdf_knowm": null,
    "knowm_role": null
  },
  {
    "cluster_id": "16529607701329319555",
    "title": "OpenMENA: An Open-Source Memristor Interfacing and Compute Board for Neuromorphic Edge-AI Applications",
    "authors": [
      "A Safa",
      "F Mohsen",
      "Z Ali",
      "B Wang",
      "A Bermak"
    ],
    "first_author_last": "Safa",
    "year": 2025,
    "venue": "arXiv preprint arXiv …",
    "link": "https://arxiv.org/abs/2511.03747",
    "doi": null,
    "cited_by": 1,
    "snippet": "… The proposed OpenMENA system for memristor crossbar control and interfacing. The … an Arduino Due board for general purpose digital control. An 8-by-8 knowm memristor crossbar is …",
    "pdf_url": "https://arxiv.org/pdf/2511.03747",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "Memristive crossbars enable in-memory multiply-accumulate and local plasticity learning, offering a path to energy-efficient edge AI. To this end, we present Open-MENA (Open Memristor-in-Memory Accelerator), which, to our knowledge, is the first fully open memristor interfacing system integrating (i) a reproducible hardware interface for memristor crossbars with mixed-signal read-program-verify loops; (ii) a firmware-software stack with high-level APIs for inference and on-device learning; and (iii) a Voltage-Incremental Proportional-Integral (VIPI) method to program pre-trained weights into analog conductances, followed by chip-in-the-loop fine-tuning to mitigate device non-idealities. OpenMENA is validated on digit recognition, demonstrating the flow from weight transfer to on-device adaptation, and on a real-world robot obstacle-avoidance task, where the memristor-based model learns to map localization inputs to motor commands. OpenMENA is released as open source to democratize memristor-enabled edge-AI research.",
    "abstract_source": "arxiv",
    "oa_pdf_url": null,
    "openalex_id": null,
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "17404307296723194161",
    "title": "From simulation to reality: experimental analysis of a quantum entanglement simulation with slime molds (Physarum polycephalum) as bioelectronic components",
    "authors": [
      "M Schmidt",
      "G Seyfried",
      "U Reutina",
      "Z Seskir"
    ],
    "first_author_last": "Schmidt",
    "year": 2025,
    "venue": "Frontiers in Soft Matter",
    "link": "https://www.frontiersin.org/journals/soft-matter/articles/10.3389/frsfm.2025.1588404/full",
    "doi": "10.3389/frsfm.2025.1588404/full",
    "cited_by": 0,
    "snippet": "… entanglement with theoretical memristor models, physical memristors (from Knowm Inc.) and … Discovery board we conducted standard experiments provided by the Memristor Discovery …",
    "pdf_url": "https://www.frontiersin.org/journals/soft-matter/articles/10.3389/frsfm.2025.1588404/pdf",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": true,
    "devices": [],
    "abstract": "This study investigates whether it is possible to simulate quantum entanglement with theoretical memristor models, physical memristors (from Knowm Inc.) and slime molds Physarum polycephalum as bioelectric components. While the simulation with theoretical memristor models has been demonstrated in the literature, real-world experiments with electric and bioelectric components had not been done so far. Our analysis focused on identifying hysteresis curves in the voltage-current (I-V) relationship, a characteristic signature of memristive devices. Although the physical memristor produced I-V diagrams that resembled more or less hysteresis curves, the small parasitic capacitance introduced significant problems for the planned entanglement simulation. In case of the slime molds, and unlike what was reported in the literature, the I-V diagrams did not produce a memristive behavior and thus could not be used to simulate quantum entanglement. Finally, we designed replacement circuits for the slime mold and suggested alternative uses of this bioelectric component.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://www.frontiersin.org/journals/soft-matter/articles/10.3389/frsfm.2025.1588404/pdf",
    "openalex_id": "https://openalex.org/W4414925245",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "5127103346123401633",
    "title": "An efficient robust serial imply-based in-memristor adder",
    "authors": [
      "F Seiler",
      "N TaheriNejad"
    ],
    "first_author_last": "Seiler",
    "year": 2025,
    "venue": "Cross-Disciplinary …",
    "link": "https://ieeexplore.ieee.org/abstract/document/11380459/",
    "doi": "10.1109/ccmcc67628.2025.11380459",
    "cited_by": 0,
    "snippet": "… The parameters are set similarly to Table II, which were derived by fitting the model to a real discrete 100µm Knowm memristor [36]. We used this approach to increase our confidence in …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "Memristive systems have emerged as promising candidates for post-CMOS computing due to their compact size, low power consumption, and suitability for In-Memory Computation (IMC) through stateful logic operations. Given the fundamental role of adders in digital systems, optimizing their design and performance within memristive architectures is a critical objective for advancing next-generation computing technologies. In this work, we propose a fast and efficient IMPLY-based adder algorithm designed for a serial topology, offering enhanced robustness against common non-idealities compared to State-of-the-Art (SoA) approaches. The proposed design achieves a 10–22% reduction in latency and up to 14% lower energy consumption relative to already latency-optimized SoA adders. Furthermore, a comprehensive analysis of typical non-ideality parameters demonstrates that the proposed adder exhibits superior resilience to such effects, making it a strong candidate for reliable memristive in-memory computing.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W7129045324",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "llm_verdict": "not-knowm",
    "llm_confidence": "medium",
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "3469083652794601079",
    "title": "An improved serial imply adder algorithm for efficient neural network applications",
    "authors": [
      "F Seiler",
      "N TaheriNejad"
    ],
    "first_author_last": "Seiler",
    "year": 2025,
    "venue": "IEEE 16th Latin America …",
    "link": "https://ieeexplore.ieee.org/abstract/document/10966340/",
    "doi": "10.1109/lascas64004.2025.10966340",
    "cited_by": 3,
    "snippet": "… discrete Knowm memristor [34]. This increases the practical relevance of our simulations … We require 16 memristors as accumulators and 16 memristors that are used to handle the carry-…",
    "pdf_url": "https://eclectx.org/Publications/C59.pdf",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "Memristive systems are one of the most promising candidates for a post-CMOS era. They are small, energy-efficient, and are ideal targets for In-Memory Computation (IMC) via stateful logic. As adders are critical building blocks for any computing systems, improving them is an essential design goal. With the rise of Artificial Intelligence (AI), providing memristive adders that are optimized for Neural Networks (NNs) is extremely important. For this, we propose a Material Implication (IMPLY)-based adder algorithm in the serial topology that can preserve the weights in memory, which was not addressed in the State-of-the-Art (SoA). Our approach is 20% - 23% faster and requires 1% - 12% less energy when the adder is used repeatedly. We propose a flowchart for IMPLY-based algorithms that can represent the state changes of individual memristors and apply it to our adder. We embed our adder in a shift-and-add multiplier and evaluate the potential gains on the 8-bit quantized ResNet18. Our approach is up to 17% more energy-efficient and requires up to 20% fewer cycles for the inference than SoA adder.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4409660427",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "llm_verdict": "not-knowm",
    "llm_confidence": "medium",
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "16460494823717122830",
    "title": "Memristive dynamical spiking neural networks with spatiotemporal heterogeneity",
    "authors": [
      "X Shi",
      "P Zhou",
      "C McTaggart"
    ],
    "first_author_last": "Shi",
    "year": 2025,
    "venue": "… Conference on Machine …",
    "link": "https://ieeexplore.ieee.org/abstract/document/11351539/",
    "doi": "10.1109/mind67540.2025.11351539",
    "cited_by": 0,
    "snippet": "… , the electric field across memristor M2 becomes sufficient to switch … this mechanism using Knowm memristors is detailed in [17]: … the memductance of the Knowm memristor and its series …",
    "pdf_url": "https://pure.qub.ac.uk/files/654150277/MIND2025.pdf",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "We propose a fully memristive spiking neural network (MSNN) that incorporates spatiotemporal heterogeneity to improve temporal representation and fault tolerance. In our proposed work, each neuron possesses a distinct time constant (spatial heterogeneity) that evolves over time in response to input stimuli (temporal heterogeneity), enabling diverse, adaptive, and temporally rich responses. Both synaptic and neuronal behaviors are modeled using SPICE-level analog memristors, and the network is trained end-to-end using backpropagation through time (BPTT) in a differentiable framework. This approach eliminates the need for digital interfacing circuits such as ADCs or explicit comparators, supporting compact and efficient hardware deployment. Evaluations on the MNIST and DVS128 Gesture datasets show competitive accuracy and significantly improved robustness to hardware faults, such as stuck-at errors in RRAM cells. These results demonstrate the effectiveness of spatiotemporally heterogeneous MSNNs for scalable, reliable neuromorphic computing.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://pure.qub.ac.uk/en/publications/5599eaff-7259-4466-8e9e-96da11bfbf5e",
    "openalex_id": "https://openalex.org/W7125678890",
    "relevance": "excluded",
    "review_screen": "unclear",
    "review_reason": "no strong cues",
    "llm_verdict": "not-knowm",
    "llm_confidence": "high",
    "pdf_knowm": null,
    "knowm_role": null
  },
  {
    "cluster_id": "13364503761955844674",
    "title": "Engineering TiO₂ memristors: A material-centric review",
    "authors": [
      "S Shivaram",
      "SKS Babu",
      "DR Paul",
      "A Ashok"
    ],
    "first_author_last": "Shivaram",
    "year": 2025,
    "venue": "Journal of materials research/Pratt's guide to venture capital sources",
    "link": "https://link.springer.com/article/10.1557/s43578-025-01600-z",
    "doi": "10.1557/s43578-025-01600-z",
    "cited_by": 3,
    "snippet": "… to addressing memristor reliability issues and finally the experimental investigation with practical memristors (KNOWM IC) for real world application. Research work on TiO 2 memristors …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "Memristors have emerged as a compact, non-toxic and energy efficient alternative to traditional memory vital for advancing AI-driven fields. Whilst TiO2-based memristors have been extensively researched and reviewed, this study represents a novel approach by deconstructing the material at its core. Through an analytical dissection, the review begins with the fundamental element, TiO2 (powder and thin film forms), and critically investigates its structural, morphological, electrical, and optical properties in relation to its synthesis method, temperature, thickness, bilayers, suboxide phases, electrodes, etc. This aims to critically assess how material properties and processing parameters influence device performance, thereby establishing fundamental guidelines for designing customised memristors. Additionally, the review delves into the latest research on TiO2-based memristors with different hypotheses on switching mechanisms. For the practical realization of tailored memristors, some of the unresolved challenges are identified and outlined to guide future research efforts.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://doi.org/10.1557/s43578-025-01600-z",
    "openalex_id": "https://openalex.org/W4410994258",
    "relevance": "excluded",
    "review_screen": "likely-cite-only",
    "review_reason": "cite/other-device cues: tio2",
    "pdf_knowm": null,
    "knowm_role": null,
    "human_verdict": "not-knowm",
    "human_reason": "NO (user): TiO2 review"
  },
  {
    "cluster_id": "8327087680008084939",
    "title": "Investigation in the influence of the device material layers on the electrical performance of the self-directed channel (SDC) memristor",
    "authors": [
      "AA Taher"
    ],
    "first_author_last": "Taher",
    "year": 2025,
    "venue": "",
    "link": "https://scholarworks.boisestate.edu/td/2353/",
    "doi": "10.18122/td.2353.boisestate",
    "cited_by": 1,
    "snippet": "… The self-directed channel (SDC) memristor consists of layers of Ge 40 Se 60 (active layer), SnSe, and Ag, which operate together to produce a memristive device that is stable at high …",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": true,
    "is_mss": false,
    "devices": [],
    "abstract": "The self-directed channel (SDC) memristor consists of layers of Ge<sub>40</sub>Se<sub>60</sub> (active layer), SnSe, and Ag, which operate together to produce a memristive device that is stable at high operating temperatures, capable of cycling over 1 billion times, has a fast switching, and has low power consumption. This research explored whether altering the device materials could influence the SDC electrical performance. That was investigated by changing the chemical constituents in the individual material layers (chalcogenide atoms O, S, Se, and Te in the Ge-Ch (active layer), chalcogenide stoichiometry in the Ge-Ch (active layer), and finally, the chalcogenide in the Sn-Ch (metal chalcogenide layer), which can be measured by measuring the resulting changes in electrical performance. Also, the effect of altering the device materials on the electrical conduction in amorphous materials, including (Fowler-Nordheim Tunneling, Schottky emission, Mott-Gurney Hopping, Space Charge-Limited, and Poole Frenkel), was explored, and the differences in the electrical behavior for each material change were quantified. Additionally, the investigation included determining the device conductivity within the low resistance state operation mode and calculating the area under the hysteresis loop under the influence of a continuous-wave (CW) input signal.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4414452203",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "named-in-abstract"
  },
  {
    "cluster_id": "12897324781768755958",
    "title": "A Simple Analog Neuron with Memristor Based Synapses and SATLINS Transfer Function",
    "authors": [
      "GT Tsenov",
      "SM Kirilov"
    ],
    "first_author_last": "Tsenov",
    "year": 2025,
    "venue": "14th International …",
    "link": "https://ieeexplore.ieee.org/abstract/document/11083945/",
    "doi": "10.1109/mocast65744.2025.11083945",
    "cited_by": 1,
    "snippet": "… A laboratory equipment – oscilloscope, signal generator and breadboard integrated circuits with Knowm memristors are used for a practical realization and measurements [18]. A …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "Memristors are unique nano-length elements, having sound memorizing and switching features and due to their small energy consumption and a good compatibility with present CMOS high-density integrated chips, they have applications in analog low-power neural nets, memory arrays, and in various electric circuits. In this paper, a simple neuron with memristor synapses is proposed, with only one memristor for each weight utilized. The saturation linear symmetric activation function (satlins) is used for it's good approximation mapping properties. The schematic is implemented in LTSPICE and on a breadboard. A simple model of memristors with activation threshold is utilized. The adder is based on two opamps, one for inputs attached to negative weights and one for positive weights. Each synaptic weight is created by only one memristor, suggesting a strongly decreased circuit complexity. Due to the reduced memristor operational voltage range a scaling is needed and scaling circuits are based on voltage dividers. The applied activation function is implemented with a humble scheme with a single op-amp. The memristor neuron is analyzed in LTSPICE and MATLAB. After a comparison, the obtained outcomes are confirmed. The offered neuron is a significant stage towards engineering of complex memristor neural nets in ultra high-density integrated chips.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4412560590",
    "relevance": "excluded",
    "review_screen": "likely-cite-only",
    "review_reason": "cite/other-device cues: ltspice, spice",
    "pdf_knowm": null,
    "knowm_role": null,
    "human_verdict": "not-knowm",
    "human_reason": "NO (user)"
  },
  {
    "cluster_id": "16368308815961224290",
    "title": "A beginner's guide to developing behavioral models of memristive devices capturing nonideal and dynamic switching response in SPICE",
    "authors": [
      "I Vourkas"
    ],
    "first_author_last": "Vourkas",
    "year": 2025,
    "venue": "International Journal of Parallel Emergent and Distributed Systems",
    "link": "https://www.tandfonline.com/doi/abs/10.1080/17445760.2025.2550709",
    "doi": "10.1080/17445760.2025.2550709",
    "cited_by": 1,
    "snippet": "… Progress in R&D on memristors and memristive devices can … commercially available devices by Knowm Inc, like resistance … from discrete MDs commercialized by Knowm Inc [Citation5] …",
    "pdf_url": "https://www.tandfonline.com/doi/pdf/10.1080/17445760.2025.2550709",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "Progress in R&D on memristors and memristive devices can be boosted by practical and comprehensive device models for circuit simulations. In this context, this paper constitutes a guide for the modular development of behavioral models of memristive devices, tailored to capture nonideal and dynamic switching response. The necessary knowledge is presented step-by-step, along with ready-to-use netlists compatible with the LTSpice software. Finally, a carefully enhanced behavioral model is used to capture quantitatively the important features observed in experimental results from commercially available devices by Knowm Inc, like resistance saturation, amplitude-dependent dynamically evolving limits of resistance, and transition faults (fading memory).",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://www.tandfonline.com/doi/pdf/10.1080/17445760.2025.2550709?needAccess=true",
    "openalex_id": "https://openalex.org/W4414048654",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "5684720922380926609",
    "title": "High-Order Associative Learning Based on Memristive Circuits for Efficient Learning",
    "authors": [
      "S Wang",
      "X Li",
      "J Ding",
      "W Ma",
      "Y Wang"
    ],
    "first_author_last": "Wang",
    "year": 2025,
    "venue": "… on Circuits and …",
    "link": "https://ieeexplore.ieee.org/abstract/document/11044095/",
    "doi": "10.1109/iscas56072.2025.11044095",
    "cited_by": 0,
    "snippet": "… SELF-DIRECTED CHANNEL MEMRISTOR To … self-directed channel (SDC) memristor (KNOWM Inc.) is purchased to build high-order associative learning circuits. The SDC memristor …",
    "pdf_url": "https://arxiv.org/pdf/2410.16734",
    "is_knowm": true,
    "is_sdc": true,
    "is_mss": false,
    "devices": [],
    "abstract": "Memristive associative learning has gained significant attention for its ability to mimic fundamental biological learning mechanisms while maintaining system simplicity. In this work, we introduce a high-order memristive associative learning framework with a biologically realistic structure. By utilizing memristors as synaptic modules and their state information to bridge different orders of associative learning, our design effectively establishes associations between multiple stimuli and replicates the transient nature of high-order associative learning. In Pavlov’s classical conditioning experiments, our design achieves a 230% improvement in learning efficiency compared to previous works, with memristor power consumption in the synaptic modules remaining below 11 μW. In large-scale image recognition tasks, we utilize a 20×20 memristor array to represent images, enabling the system to recognize and label test images with semantic information at 100% accuracy. This scalability across different tasks highlights the framework’s potential for a wide range of applications, offering enhanced learning efficiency for current memristor-based neuromorphic systems.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4411726070",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "human_verdict": "uses-knowm-device",
    "human_reason": "YES: cites Campbell 'Self-directed channel memristor for high temp operation' — Knowm devices",
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-knowm-device"
  },
  {
    "cluster_id": "640230772278792658",
    "title": "A 20-kHz Memristor-based Pulse Width Modulation for Power Converters",
    "authors": [
      "F Wu",
      "Y Liu"
    ],
    "first_author_last": "Wu",
    "year": 2025,
    "venue": "IEEE Energy Conversion Conference …",
    "link": "https://ieeexplore.ieee.org/abstract/document/11259816/",
    "doi": "10.1109/ecce58356.2025.11259816",
    "cited_by": 0,
    "snippet": "… the generalized mean metastable switching (GMMS) memristor … characteristics of the real memristor, offering a more realistic … The switching between these states occurs with varying …",
    "pdf_url": "https://par.nsf.gov/servlets/purl/10653126",
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": true,
    "devices": [],
    "abstract": "Memristors have shown significant potential for energy savings (~ 1000× reduction in power consumption) in areas such as in-memory AI computing. However, due to the lack of PWM function, their use in power electronics remains limited. This paper proposed a 20-kHz memristor-based PWM modulation for the power converter. A key challenge is the lack of a high-frequency memristor-based PWM generator, as existing memristor-based PWM circuits operate at only around 10 Hz, which is too low for most switch-mode power converters. The limited frequency is due to the inherent dynamics of memristors, which restrict the amplitude swing of the carrier signal. Our new design implements the memristor as a programmable resistor, replacing the fixed resistor in a conventional analog PWM circuit. It can achieve a frequency of approximately 20 kHz, which is sufficient for power converter control. The proposed design is analyzed and validated through LTspice simulations, demonstrating its feasibility as a high-frequency PWM generator. Experimental results using KNOWM memristors further confirm the effectiveness of the design.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4416961289",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "88426678372048942",
    "title": "Evaluation of memristor performance in neural networks using an AHaH framework",
    "authors": [
      "X Xu",
      "G Si",
      "M Xu",
      "Y Yang",
      "C Li"
    ],
    "first_author_last": "Xu",
    "year": 2025,
    "venue": "SSRN Electronic Journal",
    "link": "https://www.sciencedirect.com/science/article/pii/S0925231225022787",
    "doi": "10.2139/ssrn.5125992",
    "cited_by": 0,
    "snippet": "… Memristor-based neural networks show significant potential … the performance and reliability of memristor-based neural … for a more accurate depiction of memristor dynamics. Through this …",
    "pdf_url": "https://papers.ssrn.com/sol3/Delivery.cfm?abstractid=5125992",
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": true,
    "devices": [],
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": "https://doi.org/10.2139/ssrn.5125992",
    "openalex_id": "https://openalex.org/W4407170068",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-model",
    "knowm_role": "uses-model"
  },
  {
    "cluster_id": "xHfzlyT3KlYJ",
    "title": "Design Of Three-Valued Logic Gates Based on Knowm Memristors",
    "authors": [
      "K Zhou",
      "Q Fan",
      "D Wang"
    ],
    "first_author_last": "Zhou",
    "year": 2025,
    "venue": "8th Asia Conference on Energy …",
    "link": "https://ieeexplore.ieee.org/abstract/document/11148977/",
    "doi": "10.1109/aceee66257.2025.11148977",
    "cited_by": 0,
    "snippet": "… The emerging memristors are small in size, low in power consumption and compatible with … logic gates based on the SPICE model of Knowm memristors, which provides a new idea for …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "Three-valued logic has significant advantages over traditional two-valued logic in terms of single-channel information-carrying capacity, enhanced data-transmission bandwidth of interconnected lines, and information density of integrated circuits. However, CMOS-based three-valued logic circuits consume large amounts of power and are not easy to integrate on a large scale, so they are less commonly used in practice. The emerging memristors are small in size, low in power consumption and compatible with CMOS process. In this paper, we design three-valued basic logic gates based on the SPICE model of Knowm memristors, which provides a new idea for the design of three-valued digital logic circuits.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4414165872",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "named-in-abstract"
  },
  {
    "cluster_id": "3143581894456229754",
    "title": "Progettazione di circuiti ispirati al cervello ea basso consumo per l'edge computing: dal Logic-in-Memory ai neuroni inferenziali",
    "authors": [
      "L Benatti"
    ],
    "first_author_last": "Benatti",
    "year": 2026,
    "venue": "",
    "link": "https://tesidottorato.depositolegale.it/handle/20.500.14242/362890",
    "doi": null,
    "cited_by": 0,
    "snippet": "… LiM is explored through the development of a novel memristor-… of self-directed channel (SDC) memristors employed in a … (eNVM), come i memristor. Questa tesi esplora e avanza …",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": true,
    "is_mss": false,
    "devices": [],
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": null,
    "relevance": "excluded",
    "review_screen": "no-abstract",
    "review_reason": "no abstract — manual check",
    "pdf_knowm": null,
    "knowm_role": null,
    "human_verdict": "not-knowm",
    "human_reason": "NO (user): not sure from abstract"
  },
  {
    "cluster_id": "_BvfnruYUeMJ",
    "title": "Experimental Demonstration of Temporally Aware Fault‐Tolerant Sensor Fusion Using Memristive Associative Learning",
    "authors": [
      "K Bhardwaj",
      "A Nehal",
      "D Semenov"
    ],
    "first_author_last": "Bhardwaj",
    "year": 2026,
    "venue": "Advanced Electronic Materials",
    "link": "https://advanced.onlinelibrary.wiley.com/doi/abs/10.1002/aelm.202500873",
    "doi": "10.1002/aelm.202500873",
    "cited_by": 0,
    "snippet": "… A summary to highlight the trade-off between KNOWM memristor and the memristor is presented in Table 2. To utilize best of both worlds, future implementations will consider more …",
    "pdf_url": "https://advanced.onlinelibrary.wiley.com/doi/pdfdirect/10.1002/aelm.202500873",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "ABSTRACT Autonomous vehicles rely on fault‐tolerant multi‐sensor fusion for accurate perception and reliable decision‐making in case of sensor dropouts. However, conventional fault‐tolerant mechanisms struggle to fully acknowledge the valid sensor pairs (or a set) associated with individual events, often producing erroneous activations when signals are delayed, misaligned, or partially available. This work presents a mixed‐signal memristive associative learning circuit (ALC) that introduces two key mechanisms, selective sensor pairing and electronically tunable temporal validation, to ensure that only correctly grouped and temporally coherent sensor inputs contribute to learning and output generation. Implemented using a memristor, operational amplifiers, logic gates, and latches, the proposed design consumes less than 300 mW with highly‐scalable integrability in standard CMOS technologies. Simulations show that the circuit reduces erroneous activations from 78.6% to 0% when compared with the traditional associative learning realization. Finally, the proposed proof‐of‐concept is experimentally validated based on a benchtop implementation using commercial memristor IC as well as memristor emulator circuit and results are compared. Additionally, we demonstrate the potential use of ALC output in real‐time scenarios through a servo control, i.e., how the proposed architecture can drive the actuators in real vehicles, showing the efficacy of the idea in dealing with real‐time responses.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://doi.org/10.1002/aelm.202500873",
    "openalex_id": "https://openalex.org/W7162289881",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "uses-knowm-device",
    "human_verdict": "uses-knowm-device",
    "human_reason": "YES (user)"
  },
  {
    "cluster_id": "K6sGj4PNzacJ",
    "title": "Implementation of neural networks on FPGAs with memristors for optimizing data processing in ATLAS()",
    "authors": [
      "D Fiacco"
    ],
    "first_author_last": "Fiacco",
    "year": 2026,
    "venue": "Nuovo Cimento C",
    "link": "https://cds.cern.ch/record/2955095",
    "doi": null,
    "cited_by": 0,
    "snippet": "… Finally, we report experimental results using Knowm self-directed channel memristors (Campbell Kristy A., Microelectron. J., 59 (2017) 10), demonstrating the ability to iteratively pro…",
    "pdf_url": "https://cds.cern.ch/record/2955095/files/document.pdf",
    "is_knowm": true,
    "is_sdc": true,
    "is_mss": false,
    "devices": [],
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": null,
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "6358608941285541132",
    "title": "Integrating physical unclonable functions from novel nanomaterials, circuit elements, and memory technologies into future hardware architectures",
    "authors": [
      "F Frank"
    ],
    "first_author_last": "Frank",
    "year": 2026,
    "venue": "",
    "link": "https://opus4.kobv.de/opus4-uni-passau/files/2010/frank_florian_dissertation.pdf",
    "doi": null,
    "cited_by": 0,
    "snippet": "… a type of memristive device known as self-directed channel memristors [85]. These devices … chalcogenide with tungsten as a dopant (W + Ge2Se3). This layer consists of Ge-rich …",
    "pdf_url": "https://opus4.kobv.de/opus4-uni-passau/files/2010/frank_florian_dissertation.pdf",
    "is_knowm": false,
    "is_sdc": true,
    "is_mss": true,
    "devices": [],
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": null,
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "uses-knowm-device",
    "human_verdict": "uses-knowm-device",
    "human_reason": "YES: dissertation p.22 uses Knowm (frank_florian_dissertation.pdf)"
  },
  {
    "cluster_id": "896907943055125264",
    "title": "An energy-and endurance-aware hybrid CMOS–SDC memristor convolutional spiking neural network for edge intelligence",
    "authors": [
      "JS Go",
      "JT Kim"
    ],
    "first_author_last": "Go",
    "year": 2026,
    "venue": "Electronics",
    "link": "https://www.mdpi.com/2079-9292/15/6/1217",
    "doi": "10.3390/electronics15061217",
    "cited_by": 1,
    "snippet": "",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": true,
    "is_mss": false,
    "devices": [],
    "abstract": "The inherent bottleneck of the von Neumann architecture and the limited power budget of edge devices necessitate energy-efficient hardware solutions for artificial intelligence. Memristor-based In-Memory Computing (IMC) has emerged as a promising candidate; however, the high-power consumption of peripheral circuits, particularly Analog-to-Digital Converters (ADCs), and the reliability issues of memristive devices remain significant challenges. In this paper, we propose a hybrid Convolutional Spiking Neural Network (CSNN) architecture designed for resource-constrained edge computing. Our approach integrates digital Non-Leaky Integrate-and-Fire (NLIF) neurons with Knowm Self-Directed Channel (SDC) memristor-based synapses in a 1T1R crossbar array. To maximize power efficiency, we replace conventional high-resolution ADCs with a streamlined readout circuit utilizing a Current Sense Amplifier (CSA) and a 1-bit comparator. Furthermore, we employ an intensity-to-latency temporal coding scheme to minimize spike activity and mitigate device endurance degradation. We validated the proposed system using the MNIST dataset, achieving a classification accuracy of 97.8%, which is comparable to state-of-the-art floating-point SNNs using supervised learning methods. Power analysis confirms that our 1-bit readout method consumes only 18.4% of the energy required by an 8-bit ADC-based approach while maintaining negligible accuracy loss. Additionally, the deterministic single-spike nature of our temporal coding significantly reduces write stress on memristors compared to rate coding. These results demonstrate that the proposed hybrid CSNN offers a robust and energy-efficient solution for neuromorphic edge intelligence.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://www.mdpi.com/2079-9292/15/6/1217/pdf?version=1773478391",
    "openalex_id": "https://openalex.org/W7136674126",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "named-in-abstract"
  },
  {
    "cluster_id": "_igUiJc-xUsJ",
    "title": "Modeling Techniques and the Dependency of Memelements on the Three Existing Fundamental Circuit Elements",
    "authors": [
      "A Isah"
    ],
    "first_author_last": "Isah",
    "year": 2026,
    "venue": "International Journal of Circuit Theory and Applications",
    "link": "https://onlinelibrary.wiley.com/doi/abs/10.1002/cta.70333",
    "doi": "10.1002/cta.70333",
    "cited_by": 0,
    "snippet": "… Using Knowm memristor chip, Figure 14 shows the setup and the pinched hysteresis loop. At high input frequency, the pinched hysteresis loop became a linear graph. Unfortunately, …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "ABSTRACT Memelements is the short form of memory circuit elements and it includes memory resistor (memristor), memory capacitor (memcapacitor) and memory inductor (meminductor). These are circuit elements with huge potential in many facets of electronics, such as nonvolatile memory applications, neuromorphic and bioinspired systems, chaotic circuits, and so on. Memristor was proclaimed to be a fundamental passive circuit element complementing resistor, capacitor, and inductor. However, this assertion faces strong oppositions, among which is the discovery of memcapacitor and meminductor leading to the general concept of the memelements. Starting from the basic principle, this paper presents a review on the modeling techniques of memelements and then we explore their dependency on the fundamental circuit elements. From the modeling perspective and the circuit point of view, we demonstrate that memelements are not fundamental circuit elements; however, they are an extension of the three existing fundamental circuit elements, thus reflecting their memory effects as manifested by the pinched hysteresis loops in the governing plane of their constitutive variables.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://onlinelibrary.wiley.com/doi/pdfdirect/10.1002/cta.70333",
    "openalex_id": "https://openalex.org/W7126276025",
    "relevance": "excluded",
    "review_screen": "unclear",
    "review_reason": "no strong cues",
    "llm_verdict": "not-knowm",
    "llm_confidence": "high",
    "pdf_knowm": null,
    "knowm_role": null
  },
  {
    "cluster_id": "S13lJ9zgTxoJ",
    "title": "Emerging SDC Memristor Architectures for AI Hardware: Multibit Storage Capabilities, Thermal Effects, and Dynamic Simulation Analysis",
    "authors": [
      "J Jenifer",
      "S Sumathi",
      "P Banupriya"
    ],
    "first_author_last": "Jenifer",
    "year": 2026,
    "venue": "… on Networking and …",
    "link": "https://ieeexplore.ieee.org/abstract/document/11518286/",
    "doi": "10.1109/icnwc68145.2026.11518286",
    "cited_by": 0,
    "snippet": "… transient modeling for 2D materialbased memristors, are examined, … memristor simulation, proposing AI-assisted modeling frameworks, and highlighting the potential of SDC memristors …",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": true,
    "is_mss": false,
    "devices": [],
    "abstract": "This work investigates the modeling and simulation of Self-Directed Channel (SDC) memristors to address limitations of traditional CMOS scaling and enhance next-generation memory systems for edge-AI and neuromorphic computing. The research objective is to explore advanced simulation techniques for accurately capturing SDC memristor behavior under dynamic, real-time conditions. The methodology includes a comprehensive review of memristor modeling approaches, ranging from conventional Verilog-A and SPICEbased methods to AI-driven adaptive simulation frameworks such as Physics-Informed Neural Networks (PINNs), pulsedriven resistance control, and noise modeling. Advanced simulation techniques, including TCAD, kinetic Monte Carlo, and sub-nanosecond transient modeling for 2D materialbased memristors, are examined, alongside hardware-software cosimulation concepts. Key findings show that AI-enhanced models and dynamic control via smart memory controllers significantly improve predictive accuracy and real-time adaptability, while current digital proof environments lack integrated pulseadaptive simulation capabilities. The primary contributions of this work include identifying research gaps in real-time memristor simulation, proposing AI-assisted modeling frameworks, and highlighting the potential of SDC memristors for reliable multibit storage, dynamic resistance tuning, and analog computing in compute-in-memory architectures.",
    "abstract_source": "semanticscholar",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W7161682401",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "named-in-abstract"
  },
  {
    "cluster_id": "11264507074928805190",
    "title": "Bridging Memory and Computation: Reimagining Digital Logics through Memristor Technology",
    "authors": [
      "DS Khwairakpam"
    ],
    "first_author_last": "Khwairakpam",
    "year": 2026,
    "venue": "Microelectronics",
    "link": "https://onlinelibrary.wiley.com/doi/abs/10.1002/9781394336487.ch17",
    "doi": "10.1002/9781394336487.ch17",
    "cited_by": 0,
    "snippet": "… of memristor technology, from its theoretical origins to present-day applications, with a focus on its deployment in digital logic systems. Four categories of memristor-… HP, Knowm Inc., and …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "Memristors, first theorized by Leon Chua in 1971, represent a groundbreaking advancement in the field of electronics and have evolved into one of the most promising components of modern technology. Their potential to revolutionize fields, such as memory storage, neuromorphic computing, and artificial intelligence (AI), has captured significant attention in both academia and industry. This article offers a glimpse into the current state of memristor technology, from its theoretical origins to present-day applications, with a focus on its deployment in digital logic systems. Four categories of memristor-based digital logic systems are explored demonstrating how their in-memory computing paradigm can implement universally complete logic systems. Discussions include binary IMPLY and FALSE, binary MAGIC, ternary MAGIC, and multiple-switching binary decision trees. By leveraging the dynamic reconfigurability of memristor operating conditions, multiple logic functions can be performed within the same device, while circumventing the need for traditional data transfer between memory and processing unit.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://doi.org/10.1002/9781394336487.ch17",
    "openalex_id": "https://openalex.org/W7128819004",
    "relevance": "excluded",
    "review_screen": "unclear",
    "review_reason": "no strong cues",
    "llm_verdict": "not-knowm",
    "llm_confidence": "high",
    "pdf_knowm": null,
    "knowm_role": null
  },
  {
    "cluster_id": "12630605143495517653",
    "title": "Critical Analysis of Energy Consumption in Neuro-Computational Systems",
    "authors": [
      "I Kipelkin",
      "I Kamenko",
      "J Ivošević",
      "A Fedorova"
    ],
    "first_author_last": "Kipelkin",
    "year": 2026,
    "venue": "IEEE Access",
    "link": "https://ieeexplore.ieee.org/abstract/document/11481193/",
    "doi": "10.1109/access.2026.3683791",
    "cited_by": 0,
    "snippet": "… KNOWM memristors belong to the Self Directed Channel class of metal-ion memristors, with … reading pulse of 0.08 V on a single memristor based synapse. Digilent Analog Discovery 3 …",
    "pdf_url": "https://ieeexplore.ieee.org/iel8/6287639/6514899/11481193.pdf",
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "This article presents a unified benchmark of energy consumption per synaptic event across five classes of neuro-computational substrates: graphics processing units, neural processing units, field-programmable gate arrays, digital spiking processors, and in-memory/memristive devices, with biological synapses used as reference bands. The main contribution is methodological as well as empirical. Methodologically, we introduce a common event-level metric that makes heterogeneous systems directly comparable despite major differences in architecture, coding scheme, and learning dynamics. Empirically, we combine measurements obtained by the authors with carefully normalized literature data to map the present energy landscape of artificial and biological neural computation. The results reveal three robust regimes. Dense von Neumann ANN implementations on GPUs, NPUs, and FPGA operate mainly in the <inline-formula xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\"> <tex-math notation=\"LaTeX\">$10^{5}$ </tex-math></inline-formula> to <inline-formula xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\"> <tex-math notation=\"LaTeX\">$10^{8}$ </tex-math></inline-formula> fJ range per synaptic event. Digital spiking processors reduce this requirement to about <inline-formula xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\"> <tex-math notation=\"LaTeX\">$10^{3}$ </tex-math></inline-formula> to <inline-formula xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\"> <tex-math notation=\"LaTeX\">$10^{4}$ </tex-math></inline-formula> fJ per event. Memristive and transistor-based artificial synapses span a much broader interval, from array-level values near <inline-formula xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\"> <tex-math notation=\"LaTeX\">$10^{6}$ </tex-math></inline-formula> fJ down to a few femtojoules in the most efficient device-level realizations. In particular, the best organic PANI memristive samples approach ~2 fJ per synaptic event, entering the biological vicinity and, in some cases, surpassing the rat reference range. Taken together, the benchmarked landscape spans up to ten orders of magnitude across the full set of systems considered in this study. This result clarifies where current AI hardware stands relative to biological efficiency, identifies event-driven and in-memory computation as the most promising routes toward sustainable AI, and provides a quantitatively grounded reference framework for future neuromorphic benchmarking. INDEX TERMS Artificial neural networks, energy consumption, energy efficiency, memristive devices, neuromorphic computing, spiking neural networks, sustainable AI.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://doi.org/10.1109/access.2026.3683791",
    "openalex_id": "https://openalex.org/W7155562336",
    "relevance": "excluded",
    "review_screen": "unclear",
    "review_reason": "weak use cues: measurement",
    "llm_verdict": "not-knowm",
    "llm_confidence": "high",
    "pdf_knowm": null,
    "knowm_role": null
  },
  {
    "cluster_id": "iaByun-BoREJ",
    "title": "Memristive neural network circuit with fault tolerance for character recognition",
    "authors": [
      "G Mei",
      "L Jikang",
      "X Jingzhi"
    ],
    "first_author_last": "Mei",
    "year": 2026,
    "venue": "Chinese Physics B",
    "link": "https://iopscience.iop.org/article/10.1088/1674-1056/ae3f94/meta",
    "doi": "10.1088/1674-1056/ae3f94/meta",
    "cited_by": 0,
    "snippet": "… memristor crossbar-based neural computing systems [40]. In order to effectively deal with memristor … with deterministic parameters is established based on Knowm-memristor [45]. The …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "Abstract Memristor-based neural networks are one of the most promising approaches for hardware implementation of artificial neural networks. In this paper, a memristor-based neural network circuit based on 1M1R synaptic array structure is designed for character recognition function. Compared to other memristive synaptic arrays, the 1M1R structure can reduce the number of used memristors. However, the memristor may malfunction due to fabrication defects and the influence of external factors, resulting in a decrease in the accuracy of the circuit’s character recognition, and a suitable solution needs to be found to improve the stability and durability of the circuit. Therefore, in this paper, a fault-tolerant module with feedback adjustment capability is designed in the memristive neural network circuit, which can re-adjust the weights of the memristors through insitu training to solve the multiple faults in the memristive neural network, and the effect of the fault-tolerance is verified by character recognition. The experimental results show that the designed memristive neural network circuit can accurately realize character recognition, and the designed fault-tolerant circuit can well tolerate multiple faults, which ensures the stable operation of the circuit under fault conditions.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://doi.org/10.1088/1674-1056/ae3f94",
    "openalex_id": "https://openalex.org/W7126225948",
    "relevance": "excluded",
    "review_screen": "unclear",
    "review_reason": "weak use cues: experimental, experiment",
    "llm_verdict": "not-knowm",
    "llm_confidence": "high",
    "pdf_knowm": null,
    "knowm_role": null
  },
  {
    "cluster_id": "15597534280075841578",
    "title": "Improved memristor model with parasitic parameters",
    "authors": [
      "V Mladenov",
      "S Kirilov"
    ],
    "first_author_last": "Mladenov",
    "year": 2025,
    "venue": "COMPEL The International Journal for Computation and Mathematics in Electrical and Electronic Engineering",
    "link": "https://www.emerald.com/compel/article/doi/10.1108/COMPEL-11-2024-0491/1333022",
    "doi": "10.1108/COMPEL-11-2024-0491/1333022",
    "cited_by": 1,
    "snippet": "… self-directed channel Knowm memristors as widely applicable memory elements and their influence on the normal operation of memristors … chalcogenide materials, as Ge2Se3/SnSe/Ag…",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": true,
    "is_mss": true,
    "devices": [],
    "abstract": "Purpose In the latest years, various innovative and hopeful applications for electronic industry are founded on memristors. They are novel, two-terminal and passive elements, having very good commutating and memory features. For design, synthesis and analysis of memristor circuits, scientists need simple, precise and fast-operating memristor models and suitable software. The purpose of this paper is to provide simplified and quickly functioning memristor models, paying attention on basic parasitic parameters – capacitance, resistance, inductance, additional small-signal DC current and voltage sources for shifting the i–v relations, and analysis of their influence on memristor operation. Models’ simplification ensures analyses of complex memristor-based devices. Design/methodology/approach The optimal values of memristor model’s coefficients and parasitic parameters are estimated, applying experimental voltage–current characteristics of Knowm memristors and using a gradient-descending technique in Simulink-MATLAB. Findings Analyses in MATLAB and LTSPICE approve the correct and fast operation of proposed memristor models, their good memory and switching properties and applicability in different electronic devices. Some potential applications of proposed models are discussed and a comparison with several widely used standard and modified models is conducted. Originality/value Simple modified models of a memristor with parasitic parameters are applied in MATLAB and LTSPICE for finding parasitic capacitance, resistance, inductance and small-signal DC voltage and current components. The amplitude response is analyzed, together with i–v relations at different frequencies in sine-wave and impulse modes.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W7117772695",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "named-in-abstract"
  },
  {
    "cluster_id": "8075909288398201094",
    "title": "Influence of the Ge–Chalcogenide Active Layer on Electrical Conduction in Self-Directed Channel Memristors",
    "authors": [
      "AA Taher",
      "KA Campbell"
    ],
    "first_author_last": "Taher",
    "year": 2026,
    "venue": "Micromachines",
    "link": "https://www.mdpi.com/2072-666X/17/4/403",
    "doi": "10.3390/mi17040403",
    "cited_by": 0,
    "snippet": "",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": true,
    "is_mss": false,
    "devices": [],
    "abstract": "The self-directed channel (SDC) class of memristors employs a multilayer architecture that is designed to enable robust Ag ion conduction, long cycling lifetime, and thermal stability. While several layers contribute to mechanical and chemical reliability, two layers primarily govern the electrical behavior: the amorphous Ge–chalcogenide active layer that is adjacent to the bottom electrode and the overlying metal–chalcogenide source layer. In this work, we investigate how the variation in the chalcogen species in these two layers influences switching characteristics in the pre-write regime, both in the pristine state and after a write/erase cycle, as well as the conduction behavior at room temperature. The devices were fabricated using Ge-rich chalcogenides containing O, S, Se, or Te, combined with SnS, SnSe, or Ag2Se metal–chalcogenide layers. The DC current-voltage measurements were analyzed using the standard linearization approaches to examine whether the transport behavior in the pre-write regime exhibits characteristics that are associated with Ohmic, Schottky, Poole–Frenkel, or space charge limited conduction. These measurements specifically probe the pre-write region of the I-V curve, where early ionic redistribution and structural rearrangement precede the abrupt formation of the conductive channels responsible for the resistive switching. The results show that the chalcogen composition strongly affects the threshold voltage, the resistance window, and the onset of field-enhanced transport, reflecting the differences in ionic distribution and channel formation dynamics. The results indicate that transport evolves with a bias and a compliance current, transitioning between regimes that are influenced by the interface injection and bulk-limited conduction, depending on the material stack. These findings clarify the role of chalcogen chemistry in governing the SDC switching behavior and provide guidance for the material selection in application-specific device design.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://www.mdpi.com/2072-666X/17/4/403/pdf?version=1774514760",
    "openalex_id": "https://openalex.org/W7140821367",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "named-in-abstract"
  },
  {
    "cluster_id": "AoTRbIQmuBEJ",
    "title": "Memristive Conductance Programming and Dot Products for Inference in Machine Learning",
    "authors": [
      "J Tariq",
      "L Cimmino",
      "F Conventi"
    ],
    "first_author_last": "Tariq",
    "year": 2026,
    "venue": "IEEE Transactions on Nuclear Science",
    "link": "https://ieeexplore.ieee.org/abstract/document/11527406/",
    "doi": "10.1109/tns.2026.3695386",
    "cited_by": 0,
    "snippet": "… Memristor-based in-memory computing offers a promising … In fact, memristor conductance programming is paramount … algorithm for KnowM self-directed channel memristors, ensuring …",
    "pdf_url": "https://ieeexplore.ieee.org/iel8/23/11569520/11527406.pdf",
    "is_knowm": true,
    "is_sdc": true,
    "is_mss": false,
    "devices": [],
    "abstract": "Future trigger and data acquisition systems in high-energy physics will face challenges in data throughput and power efficiency. The increasing integration of artificial intelligence (AI) algorithms for on-detector event selection further amplifies these demands. AI implementations require fast and efficient vector-by-matrix multiplication (VMM), which traditional CMOS architectures, originally not designed for AI, struggle to support. Memristor-based in-memory computing offers a promising solution, particularly for analog VMMs in artificial neural networks, where device conductances represent synaptic weights. In fact, memristor conductance programming is paramount for defining artificial neural network weights. This work presents an adaptive conductance tuning algorithm for KnowM self-directed channel memristors, ensuring reliable programming across a 20–250 μS range with a 6–8% error margin. We demonstrate the programming of eight non-overlapping conductance states, establishing the algorithm’s capability for reliable multi-level conductance control. The approach is experimentally validated using a 1×16 memristor array, demonstrating a four-dimensional dot product over 100 test vector pairs.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://doi.org/10.1109/tns.2026.3695386",
    "openalex_id": "https://openalex.org/W7161914458",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "named-in-abstract"
  },
  {
    "cluster_id": "10180409240866826628",
    "title": "SPICE memristor model based on estimate from measured data",
    "authors": [
      "GT Tsenov",
      "S Kirilov",
      "V Mladenov"
    ],
    "first_author_last": "Tsenov",
    "year": 2025,
    "venue": "COMPEL The International Journal for Computation and Mathematics in Electrical and Electronic Engineering",
    "link": "https://www.emerald.com/compel/article/doi/10.1108/COMPEL-11-2024-0492/1249245",
    "doi": "10.1108/COMPEL-11-2024-0492/1249245",
    "cited_by": 2,
    "snippet": "… Knowm memristors, type W and type C. We have two memristor arrays produced by Knowm. … and integrated circuits with Knowm memristors; (b) analog discovery 3 signal generator and …",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "Purpose The real production memristor devices produce a modeling challenge due to having a memristor variance and henceforth a measured difference between breadboard made circuits and LTSPICE or MATLAB simulated circuits with classical models, resulting in variances owed to difference in existing models and real hardware. When a new memristor is studied, usually no model is provided and it’s useful if there is a tool that automatically update models with production parameters. The purpose of this paper is to implement a procedure in MATLAB that takes measured data, approximates parameters and provides a MATLAB and LTSPICE models for precise representation of real memristor devices. Design/methodology/approach The optimal values of production level memristor model’s coefficients can be estimated for various existing models by applying the measured voltage-current relationship and by using optimization procedure to match the coefficients to existing model. With graphical user interface (GUI) in MATLAB environment a user can select measured data and which model to be used as some are good for high frequency and others for low or mid frequency memristors. Findings The analyses, which were performed in MATLAB and LTSPICE, validate the efficiency and accuracy of the proposed memristor model matching procedure. The analysis case utilizes a comparison with some very commonly used standard and modified memristor models. Originality/value A GUI with optimization procedure for parameter estimation of real-world production memristors into simple memristor models or with parasitic parameters is applied in MATLAB and then transferred in LTSPICE with amplitude-frequency responses and voltage-current relations analyzed for different frequencies.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4410044153",
    "relevance": "excluded",
    "review_screen": "likely-cite-only",
    "review_reason": "cite/other-device cues: spice model, ltspice, spice, proposed memristor",
    "pdf_knowm": null,
    "knowm_role": null,
    "human_verdict": "not-knowm",
    "human_reason": "NO (user)"
  },
  {
    "cluster_id": "6mnqN6-sFRAJ",
    "title": "Robust Sb2Se3 memristors via pressure-modulated growth for noise-resilient neuromorphic computing",
    "authors": [
      "Z Wang",
      "C Song",
      "H Chen",
      "X Liu",
      "X Zhang",
      "J Zhu"
    ],
    "first_author_last": "Wang",
    "year": 2026,
    "venue": "Nano Research",
    "link": "https://www.sciopen.com/article/10.26599/NR.2026.94908881",
    "doi": "10.26599/NR.2026.94908881",
    "cited_by": 0,
    "snippet": "… This work establishes the RTE-processed Sb2Se3 memristor as a highperformance … activation energy in the Ag/SnSe/Ge2Se3/W self-directed channel memristor. Mod. Electron. …",
    "pdf_url": "https://www.sciopen.com/local/article_pdf/10.26599/NR.2026.94908881.pdf",
    "is_knowm": false,
    "is_sdc": true,
    "is_mss": true,
    "devices": [],
    "abstract": "Abstract High-fidelity neuromorphic computing requires synaptic hardware that balances analog precision with array-level noise immunity, yet suppressing leakage currents in chalcogenide crossbars often necessitates complex interface engineering. Here, a robust Ag/Sb2Se3/ITO synapse is reported, fabricated via a pressure-modulated rapid thermal evaporation (RTE) strategy that targets intrinsic defect control. Crucially, this thermodynamic optimization preserves the ultralow intrinsic carrier concentration (~1014 cm-3) of the Sb2Se3 functional layer, physically prohibiting background leakage pathways without requiring additional buffer layers. Consequently, the device demonstrates highly uniform analog switching behavior, a substantial ON/OFF ratio (&gt;105), and low set/reset voltages. These characteristics effectively suppress sneak path currents and maximize the sensing margins within the crossbar array. At the system level, physics-based neural networks achieve 96.3% accuracy on MNIST, maintaining exceptional robustness against severe salt-and-pepper noise. Furthermore, we demonstrate that the hardware can execute complex motion perception algorithms, successfully extracting clear motion edges in dynamic spatiotemporal scenarios. This work establishes intrinsic carrier concentration modulation as a minimalist yet powerful paradigm for next-generation noise-resilient edge intelligence.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://www.sciopen.com/local/article_pdf/10.26599/NR.2026.94908881.pdf",
    "openalex_id": "https://openalex.org/W7162520469",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "llm_verdict": "not-knowm",
    "llm_confidence": "high",
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "YA4yJfyDlgwJ",
    "title": "Design of Memristor‐Based Balanced Ternary Full Adder",
    "authors": [
      "XY Wang",
      "CT Dong",
      "JT Huang",
      "H Li"
    ],
    "first_author_last": "Wang",
    "year": 2026,
    "venue": "International Journal of Circuit Theory and Applications",
    "link": "https://onlinelibrary.wiley.com/doi/abs/10.1002/cta.70385",
    "doi": "10.1002/cta.70385",
    "cited_by": 0,
    "snippet": "… Our design and analysis are based on the KNOWM memristor model. LRS and HRS of the device are chosen as 10 kΩ and 4.8 MΩ, and the 50- nm BSIM model for MOSFET transistors (…",
    "pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "abstract": "ABSTRACT Balanced ternary digital logic circuits are designed based on memristors and applied to realize adder circuits, which can alleviate the Von Neumann architecture bottleneck and help extend Moore's Law. Four design methods are presented: decoder‐based method, multiplexer‐based method, method of combining multiplexers with single variable logic circuits, and method based on digital logic gates. The full‐adder circuits implemented by the above four distinct design methods are systematically compared and analyzed. This analysis highlights the strengths and limitations of each approach, thus providing a guideline for future development and optimization of balanced ternary combinational logic circuits aimed at achieving enhanced performance, power efficiency, and compactness.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W7151838128",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "llm_verdict": "not-knowm",
    "llm_confidence": "high",
    "pdf_knowm": "uses-device",
    "knowm_role": "uses-device"
  },
  {
    "cluster_id": "2721808777234926263",
    "title": "A Memristor-Based SNN Hardware Architecture with AHaH Plasticity",
    "authors": [
      "R Xie",
      "G Si",
      "X Xu",
      "M Xu",
      "Y Yang",
      "C Li"
    ],
    "first_author_last": "Xie",
    "year": 2026,
    "venue": "Communications in computer and information science",
    "link": "https://link.springer.com/chapter/10.1007/978-981-92-1599-7_6",
    "doi": "10.1007/978-981-92-1599-7_6",
    "cited_by": 0,
    "snippet": "… framework, a memristor is conceptualized as an ensemble of N metastable switches, each … Simulations were conducted using MATLAB with the generalized MSS memristor model to …",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": true,
    "devices": [],
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W7164756360",
    "relevance": "core",
    "review_screen": null,
    "review_reason": null,
    "pdf_knowm": null,
    "knowm_role": "named-in-abstract"
  },
  {
    "cluster_id": "manual-W7165386536",
    "title": "Research on memristor-based logic circuits",
    "authors": [
      "Weican Chen",
      "Xuefang Xiao",
      "Xinlan Pan"
    ],
    "first_author_last": "Chen",
    "year": 2026,
    "venue": "Journal of Physics: Conference Series",
    "link": "https://iopscience.iop.org/article/10.1088/1742-6596/3261/1/012007",
    "doi": "10.1088/1742-6596/3261/1/012007",
    "cited_by": 0,
    "snippet": "",
    "pdf_url": null,
    "oa_pdf_url": null,
    "is_knowm": true,
    "is_sdc": false,
    "is_mss": true,
    "devices": [],
    "abstract": "As transistor performance approaches physical limits, it severely constrains the further development of integrated circuits. This study focuses on the unique electrical characteristics of memristors, employing the Knowm average metastable switching model to investigate logic gate integration design. First, the SPICE circuit model of the Knowm memristor was constructed in LTSPICE, and its characteristics were verified to confirm core performance metrics, including resistance-state switching response and non-volatility. Subsequently, leveraging mature CMOS technology, we designed and optimized fundamental logic gate units and full-adder circuits. Using LTspice, we validated the logical functionality and analyzed power consumption characteristics.",
    "abstract_source": "openalex",
    "openalex_id": "https://openalex.org/W7165386536",
    "added_manually": true,
    "pdf_knowm": "uses-model",
    "relevance": "core",
    "knowm_role": "uses-model",
    "review_screen": null,
    "review_reason": null
  },
  {
    "cluster_id": "4654876585689072670",
    "title": "Survey of machine learning accelerators",
    "authors": [
      "A Reuther",
      "P Michaleas",
      "M Jones"
    ],
    "first_author_last": "Reuther",
    "year": 2020,
    "venue": "IEEE high …",
    "link": "https://ieeexplore.ieee.org/abstract/document/9286149/",
    "doi": "10.1109/hpec43674.2020.9286149",
    "cited_by": 153,
    "snippet": "New machine learning accelerators are being announced and released each month for a variety of applications from speech recognition, video object detection, assisted driving, and …",
    "pdf_url": "https://arxiv.org/pdf/2009.00993",
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "PLoS-AHaH-2014"
    ],
    "provenance": "cites-harvest",
    "abstract": "New machine learning accelerators are being announced and released each month for a variety of applications from speech recognition, video object detection, assisted driving, and many data center applications. This paper updates the survey of of AI accelerators and processors from last year's IEEE-HPEC paper. This paper collects and summarizes the current accelerators that have been publicly announced with performance and power consumption numbers. The performance and power values are plotted on a scatter graph and a number of dimensions and observations from the trends on this plot are discussed and analyzed. For instance, there are interesting trends in the plot regarding power consumption, numerical precision, and inference versus training. This year, there are many more announced accelerators that are implemented with many more architectures and technologies from vector engines, dataflow engines, neuromorphic designs, flash-based analog memory processing, and photonic-based processing.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://arxiv.org/pdf/2009.00993",
    "openalex_id": "https://openalex.org/W3082020764",
    "pdf_knowm": "uses-model",
    "relevance": "cites",
    "knowm_role": "cites",
    "cites_reviewed": true
  },
  {
    "cluster_id": "13566481968234924395",
    "title": "Conjugated polymers for information storage and neuromorphic computing",
    "authors": [
      "S Liu",
      "X Chen",
      "G Liu"
    ],
    "first_author_last": "Liu",
    "year": 2020,
    "venue": "Polymer International",
    "link": "https://scijournals.onlinelibrary.wiley.com/doi/abs/10.1002/pi.6017",
    "doi": "10.1002/pi.6017",
    "cited_by": 25,
    "snippet": "In the era of information explosion, silicon‐based storage can barely meet the burgeoning demand for data storage and making Moore's law no longer accurate. What is more, the …",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "PLoS-AHaH-2014"
    ],
    "provenance": "cites-harvest",
    "abstract": "Abstract In the era of information explosion, silicon‐based storage can barely meet the burgeoning demand for data storage and making Moore's law no longer accurate. What is more, the traditional von Neumann architecture separates the computing module from the storage unit, which causes a slowing down of the overall computing efficiency. Conjugated polymer memristors, due to the advantages of simple fabrication, convenient operation and low cost, are considered as promising candidates for next‐generation memory and neuromorphic computing applications. This review summarizes the advances in conjugated polymer memristive materials and devices made during the first two decades of the 21st century, and their potential applications in information storage and neuromorphic computing. Focuses are on switching mechanisms and materials classifications, as well as memory, artificial synapse and bioinspired and in‐memory computing performance. © 2020 Society of Chemical Industry",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://onlinelibrary.wiley.com/doi/pdfdirect/10.1002/pi.6017",
    "openalex_id": "https://openalex.org/W3014394088",
    "pdf_knowm": null,
    "relevance": "cites",
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    "cites_reviewed": true
  },
  {
    "cluster_id": "15692507881379788399",
    "title": "Memristors for the curious outsiders",
    "authors": [
      "F Caravelli",
      "JP Carbajal"
    ],
    "first_author_last": "Caravelli",
    "year": 2018,
    "venue": "Technologies",
    "link": "https://www.mdpi.com/2227-7080/6/4/118",
    "doi": "10.3390/technologies6040118",
    "cited_by": 64,
    "snippet": "We present both an overview and a perspective of recent experimental advances and proposed new approaches to performing computation using memristors. A memristor is a 2 …",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
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    "cites_seed": [
      "PLoS-AHaH-2014",
      "Nugent-TRAM-2017",
      "Campbell-SDC-2016"
    ],
    "provenance": "cites-harvest",
    "abstract": "We present both an overview and a perspective of recent experimental advances and proposed new approaches to performing computation using memristors. A memristor is a 2-terminal passive component with a dynamic resistance depending on an internal parameter. We provide an brief historical introduction, as well as an overview over the physical mechanism that lead to memristive behavior. This review is meant to guide nonpractitioners in the field of memristive circuits and their connection to machine learning and neural computation.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://www.mdpi.com/2227-7080/6/4/118/pdf?version=1545128882",
    "openalex_id": "https://openalex.org/W2903854842",
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    "relevance": "cites",
    "knowm_role": "cites",
    "cites_reviewed": true
  },
  {
    "cluster_id": "4391828747145929259",
    "title": "Memristor-based neuromodulation device for real-time monitoring and adaptive control of neuronal populations",
    "authors": [
      "C Dias",
      "D Castro",
      "M Aroso",
      "J Ventura"
    ],
    "first_author_last": "Dias",
    "year": 2022,
    "venue": "ACS Applied Electronic Materials",
    "link": "https://pubs.acs.org/doi/abs/10.1021/acsaelm.2c00198",
    "doi": "10.1021/acsaelm.2c00198",
    "cited_by": 38,
    "snippet": "Neurons are specialized cells for information transmission and information processing. In fact, many neurologic disorders are directly linked not to cellular viability/homeostasis issues …",
    "pdf_url": "https://pubs.acs.org/doi/pdf/10.1021/acsaelm.2c00198",
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "PLoS-AHaH-2014",
      "Campbell-SDC-2016"
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    "provenance": "cites-harvest",
    "abstract": "Neurons are specialized cells for information transmission and information processing. In fact, many neurologic disorders are directly linked not to cellular viability/homeostasis issues but rather to specific anomalies in electrical activity dynamics. Consequently, therapeutic strategies based on the direct modulation of neuronal electrical activity have been producing remarkable results, with successful examples ranging from cochlear implants to deep brain stimulation. Developments in these implantable devices are hindered, however, by important challenges such as power requirements, size factor, signal transduction, and adaptability/computational capabilities. Memristors, neuromorphic nanoscale electronic components able to emulate natural synapses, provide unique properties to address these constraints, and their use in neuroprosthetic devices is being actively explored. Here, we demonstrate, for the first time, the use of memristive devices in a clinically relevant setting where communication between two neuronal populations is conditioned to specific activity patterns in the source population. In our approach, the memristor device performs a pattern detection computation and acts as an artificial synapse capable of reversible short-term plasticity. Using in vitro hippocampal neuronal cultures, we show real-time adaptive control with a high degree of reproducibility using our monitor-compute-actuate paradigm. We envision very similar systems being used for the automatic detection and suppression of seizures in epileptic patients.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://pubs.acs.org/doi/pdf/10.1021/acsaelm.2c00198",
    "openalex_id": "https://openalex.org/W4225279577",
    "pdf_knowm": "uses-device",
    "relevance": "core",
    "knowm_role": "uses-knowm-device",
    "human_verdict": "uses-knowm-device",
    "human_reason": "YES (PDF): neuromodulation device built on Knowm Inc. self-directed channel memristors (per the datasheet)"
  },
  {
    "cluster_id": "16170729450406831056",
    "title": "Coexistence of cyclic sequential pattern recognition and associative memory in neural networks by attractor mechanisms",
    "authors": [
      "J Huo",
      "J Yu",
      "M Wang",
      "Z Yi",
      "J Leng"
    ],
    "first_author_last": "Huo",
    "year": 2024,
    "venue": "IEEE Transactions on Neural Networks and Learning Systems",
    "link": "https://ieeexplore.ieee.org/abstract/document/10459336/",
    "doi": "10.1109/tnnls.2024.3368092",
    "cited_by": 6,
    "snippet": "Neural networks are developed to model the behavior of the brain. One crucial question in this field pertains to when and how a neural network can memorize a given set of patterns …",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": false,
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    "cites_seed": [
      "PLoS-AHaH-2014"
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    "provenance": "cites-harvest",
    "abstract": "Neural networks are developed to model the behavior of the brain. One crucial question in this field pertains to when and how a neural network can memorize a given set of patterns. There are two mechanisms to store information: associative memory and sequential pattern recognition. In the case of associative memory, the neural network operates with dynamical attractors that are point attractors, each corresponding to one of the patterns to be stored within the network. In contrast, sequential pattern recognition involves the network memorizing a set of patterns and subsequently retrieving them in a specific order over time. From a dynamical perspective, this corresponds to the presence of a continuous attractor or a cyclic attractor composed of the sequence of patterns stored within the network in a given order. Evidence suggests that the brain is capable of simultaneously performing both associative memory and sequential pattern recognition. Therefore, these types of attractors coexist within the neural network, signifying that some patterns are stored as point attractors, while others are stored as continuous or cyclic attractors. This article investigates the coexistence of cyclic attractors and continuous or point attractors in certain nonlinear neural networks, enabling the simultaneous emergence of various memory mechanisms. By selectively grouping neurons, conditions are established for the existence of cyclic attractors, continuous attractors, and point attractors, respectively. Furthermore, each attractor is explicitly represented, and a competitive dynamic emerges among these coexisting attractors, primarily regulated by adjustments to external inputs.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4392543883",
    "pdf_knowm": null,
    "relevance": "cites",
    "knowm_role": "cites",
    "human_verdict": "cites-only",
    "human_reason": "CITE (abstract): theoretical attractor NN; cites PLoS",
    "cites_reviewed": true
  },
  {
    "cluster_id": "18128048421888296848",
    "title": "An efficient heterogeneous memristive xnor for in-memory computing",
    "authors": [
      "MA Lebdeh",
      "H Abunahla",
      "B Mohammad"
    ],
    "first_author_last": "Lebdeh",
    "year": 2017,
    "venue": "IEEE Transactions on Circuits and Systems I Regular Papers",
    "link": "https://ieeexplore.ieee.org/abstract/document/8006295/",
    "doi": "10.1109/tcsi.2017.2706299",
    "cited_by": 41,
    "snippet": "Resistive RAM (RRAM) technologies are gaining importance due to their appealing characteristics, which include non-volatility, small form factor, low power consumption, and …",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "PLoS-AHaH-2014"
    ],
    "provenance": "cites-harvest",
    "abstract": "Resistive RAM (RRAM) technologies are gaining importance due to their appealing characteristics, which include non-volatility, small form factor, low power consumption, and ability to perform logic operations in memory. These characteristics make RRAM highly suited for Internet of Things devices and similarly resource-constrained systems. This paper proposes a novel memristor-based xnor gate that enables the execution of xnor/xor function in the memristive crossbar memory. The proposed two-input xnor gate requires two steps to perform the xnor function. The design of the circuit utilizes bipolar and unipolar memristors and permits cascading by only adding an extra step and one computing memristor. To the best of our knowledge, this is the first native stateful xnor logic implementation. Spice simulations have been used to verify the functionality of the proposed circuit. This includes benchmarking the proposed design against the state-of-the-art stateful memristor-based logic circuits. The results for implementing three-input xor using the proposed circuit demonstrate efficient performance in terms of energy, latency, and area. The gate shows 56% saving in energy, 54% less number of steps (latency), and 50% less number of computing MR (area) compared with the state-of-the-art stateful xor/xnor implementations.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W2743575791",
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    "relevance": "cites",
    "knowm_role": "cites",
    "cites_reviewed": true
  },
  {
    "cluster_id": "12851325229921232744",
    "title": "Memristive neural processor utilizing anti-hebbian and hebbian technology",
    "authors": [
      "A Nugent"
    ],
    "first_author_last": "Nugent",
    "year": 2016,
    "venue": "US Patent 9,269,043",
    "link": "https://patents.google.com/patent/US9269043B2/en",
    "doi": null,
    "cited_by": 70,
    "snippet": "US9269043B2 - Memristive neural processor utilizing anti-hebbian and hebbian technology - Google Patents US9269043B2 - Memristive neural processor utilizing anti-hebbian and …",
    "pdf_url": "https://patentimages.storage.googleapis.com/17/9c/c7/0a0ca8fd767a2f/US9269043.pdf",
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "PLoS-AHaH-2014"
    ],
    "provenance": "cites-harvest",
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": null,
    "pdf_knowm": "uses-model",
    "relevance": "core",
    "knowm_role": "named-in-abstract"
  },
  {
    "cluster_id": "17296047709160620914",
    "title": "Enhancing the Switching Performance of CH3NH3PbI3 Memristors by the Control of Size and Characterization Parameters",
    "authors": [
      "HJ Gogoi",
      "AT Mallajosyula"
    ],
    "first_author_last": "Gogoi",
    "year": 2021,
    "venue": "Advanced Electronic Materials",
    "link": "https://advanced.onlinelibrary.wiley.com/doi/abs/10.1002/aelm.202100472",
    "doi": "10.1002/aelm.202100472",
    "cited_by": 23,
    "snippet": "This paper analyzes the effects of scaling and measurement conditions on the performance of hybrid organic inorganic perovskite (HOIP) devices having bipolar resistive switching …",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "PLoS-AHaH-2014"
    ],
    "provenance": "cites-harvest",
    "abstract": "Abstract This paper analyzes the effects of scaling and measurement conditions on the performance of hybrid organic inorganic perovskite (HOIP) devices having bipolar resistive switching characteristics. Electroforming voltage, SET current, and ON/OFF ratios are found to be area dependent. Linear voltage sweep and pulse voltage characterization showed that parameters such as compliance current, voltage scan rate, pulse width, amplitude, and frequency significantly alter the device switching parameters. The CH 3 NH 3 PbI 3 memristors fabricated has FORMING, SET, and RESET voltages of 1.18, 0.17, and −0.13 V, respectively, along with an ON/OFF ratio of 1.3 × 10 3 . It has been found that, both the RESET voltage and current significantly increase with scan rate, whereas the ON/OFF ratio increases significantly with compliance current. In case of voltage pulse characterization, the ON/OFF ratio can be enhanced by increasing the pulse amplitude and width. Additionally, the experimental data fitting to a SPICE based analytical model establishes that the HOIP memristor current conduction is dominated by tunneling process in the OFF state and is ohmic in the ON state. Based on the results, the authors arrive at a general protocol that can be used to characterize memristors made of HOIPs and other related materials such that they can operate optimally.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W3195424059",
    "pdf_knowm": null,
    "relevance": "cites",
    "knowm_role": "cites",
    "human_verdict": "cites-only",
    "human_reason": "CITE (abstract): own perovskite memristor; cites PLoS",
    "cites_reviewed": true
  },
  {
    "cluster_id": "10749612180573920577",
    "title": "The basic I–V characteristics of memristor model: simulation and analysis",
    "authors": [
      "F Ouaja Rziga",
      "K Mbarek",
      "S Ghedira",
      "K Besbes"
    ],
    "first_author_last": "Rziga",
    "year": 2017,
    "venue": "Applied Physics A",
    "link": "https://link.springer.com/article/10.1007/s00339-017-0902-9",
    "doi": "10.1007/s00339-017-0902-9",
    "cited_by": 27,
    "snippet": "The memristor is fundamental electrical element theoretically postulated by Leon Chua in 1971 and successfully fabricated by HP Labs in 2008. However, its electrical characteristics …",
    "pdf_url": "https://link.springer.com/content/pdf/10.1007/s00339-017-0902-9.pdf",
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "PLoS-AHaH-2014"
    ],
    "provenance": "cites-harvest",
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W2598654180",
    "pdf_knowm": null,
    "relevance": "cites",
    "knowm_role": "cites",
    "cites_reviewed": true
  },
  {
    "cluster_id": "4911246885413895772",
    "title": "Evaluation of the computational capabilities of a memristive random network (MN3) under the context of reservoir computing",
    "authors": [
      "LE Suarez",
      "JD Kendall",
      "JC Nino"
    ],
    "first_author_last": "Suarez",
    "year": 2018,
    "venue": "Neural Networks",
    "link": "https://www.sciencedirect.com/science/article/pii/S0893608018302028",
    "doi": "10.1016/j.neunet.2018.07.003",
    "cited_by": 14,
    "snippet": "This work presents the simulation results of a novel recurrent, memristive neuromorphic architecture, the MN 3 and explores its computational capabilities in the performance of a …",
    "pdf_url": "https://par.nsf.gov/servlets/purl/10099322",
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "PLoS-AHaH-2014"
    ],
    "provenance": "cites-harvest",
    "abstract": "This work presents the simulation results of a novel recurrent, memristive neuromorphic architecture, the MN3 and explores its computational capabilities in the performance of a temporal pattern recognition task by considering the principles of the reservoir computing approach. A simple methodology based on the definitions of ordered and chaotic dynamical systems was used to determine the separation and fading memory properties of the architecture. The results show the potential use of this architecture as a reservoir for the on-line processing of time-varying inputs.",
    "abstract_source": "semanticscholar",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W2884285099",
    "pdf_knowm": "uses-model",
    "relevance": "cites",
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    "human_verdict": "cites-only",
    "human_reason": "CITE (abstract): MN3 reservoir architecture simulation; cites PLoS",
    "cites_reviewed": true
  },
  {
    "cluster_id": "17761474906998372551",
    "title": "Memristors: properties, models, materials",
    "authors": [
      "O Krestinskaya",
      "A Irmanova",
      "AP James"
    ],
    "first_author_last": "Krestinskaya",
    "year": 2019,
    "venue": "Modeling and optimization in science and technologies",
    "link": "https://link.springer.com/chapter/10.1007/978-3-030-14524-8_2",
    "doi": "10.1007/978-3-030-14524-8_2",
    "cited_by": 13,
    "snippet": "The practical realization of neuro-memristive systems requires highly accurate simulation models, robust devices and validations on device characteristics. This chapter covers the …",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "PLoS-AHaH-2014",
      "Molter-MSS-2016",
      "Campbell-SDC-2016"
    ],
    "provenance": "cites-harvest",
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W2954575855",
    "pdf_knowm": null,
    "relevance": "cites",
    "knowm_role": "cites",
    "human_verdict": "cites-only",
    "human_reason": "CITE (note): book-chapter review; no PDF available",
    "cites_reviewed": true
  },
  {
    "cluster_id": "5458945260910107591",
    "title": "Memristor-based neural network implementation with adjustable synaptic weights in LTSPICE",
    "authors": [
      "V Mladenov",
      "G Tsenov",
      "S Kirilov"
    ],
    "first_author_last": "Mladenov",
    "year": 2023,
    "venue": "… Conference Automatics and …",
    "link": "https://ieeexplore.ieee.org/abstract/document/10339092/",
    "doi": "10.1109/icai58806.2023.10339092",
    "cited_by": 7,
    "snippet": "The memristors are innovative electronic elements with nano-sized structure and with very good memory and switching abilities. They have very low power consumption and a good …",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": false,
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    "devices": [],
    "cites_seed": [
      "PLoS-AHaH-2014"
    ],
    "provenance": "cites-harvest",
    "abstract": "The memristors are innovative electronic elements with nano-sized structure and with very good memory and switching abilities. They have very low power consumption and a good compatibility to CMOS integrated chips, and they could be used in neural networks, memories, and many other schematics. In this paper an LTSPICE model of artificial neural network with memristor-based synapses is proposed. In this network, each synapse is realized with only one memristor, thus providing a higher reduction in circuit complexity and with main benefit of that individual memristor resistance value can be adjusted with external control voltage signals. The summing and scaling component implementations are based on op-amps and memristors. We use the most common logarithmic-sigmoidal activation function and it is realized by a voltage-controlled source. The operation of the proposed memristor neural network is analyzed and simulated in both L TSPICE and MATLAB, and the derived results are compared and verified successfully. The proposed memristor-based neural network is a significant step for engineering low power complex networks in very high-density integrated circuits and chips.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4389428757",
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    "relevance": "cites",
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    "human_verdict": "cites-only",
    "human_reason": "CITE (abstract): LTSPICE memristor-synapse ANN; cites PLoS",
    "cites_reviewed": true
  },
  {
    "cluster_id": "15141349625434276546",
    "title": "Non-pinched hysteresis in CrOx/TiOy-based memristive devices: Modeling and analysis",
    "authors": [
      "PQ Pham",
      "NLP Le",
      "TA Tran",
      "VS Dang"
    ],
    "first_author_last": "Pham",
    "year": 2026,
    "venue": "Applied Physics Letters",
    "link": "https://pubs.aip.org/aip/apl/article/128/15/153502/3387035",
    "doi": "10.1063/5.0332014",
    "cited_by": 0,
    "snippet": "",
    "pdf_url": null,
    "is_knowm": false,
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    "devices": [],
    "cites_seed": [
      "PLoS-AHaH-2014"
    ],
    "provenance": "cites-harvest",
    "abstract": "Transition-metal oxide memristors are promising for neuromorphic computing, yet most SPICE models overlook material-specific effects such as oxygen stoichiometry and non-pinched hysteresis. Here, we systematically study CrOx/TiOy memristors fabricated under controlled oxygen concentrations (10%–50%) and propose an improved SPICE-compatible model. The devices exhibit oxygen-dependent resistive switching, retention, and pulse-driven plasticity, with optimal performance at 40% oxygen. Our model explicitly reproduces the non-pinched hysteresis observed in I–V curves, consistent with behaviors such as ion immigration, charge trapping, and remnant polarization, and achieves close agreement with experiments across multiple stoichiometries. Validation includes endurance, retention, and synaptic functions such as long-term potentiation/depression and spike-number/amplitude-dependent plasticity. Finally, the model is extended from single devices to a 4 × 4 crossbar array, demonstrating its scalability for artificial neural network simulations. These results emphasize the critical role of oxygen stoichiometry in CrOx/TiOy memristors and introduce a modeling framework that bridges experimental device physics with circuit-level neuromorphic applications.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W7154341476",
    "pdf_knowm": null,
    "relevance": "cites",
    "knowm_role": "cites",
    "human_verdict": "cites-only",
    "human_reason": "CITE (abstract): own CrOx/TiOy device + SPICE model; cites PLoS",
    "cites_reviewed": true
  },
  {
    "cluster_id": "4259189736622390138",
    "title": "Memristor Models with Parasitic Parameters for Analysis of Passive Memory Arrays",
    "authors": [
      "V Mladenov",
      "S Kirilov"
    ],
    "first_author_last": "Mladenov",
    "year": 2026,
    "venue": "Technologies",
    "link": "https://www.mdpi.com/2227-7080/14/3/166",
    "doi": "10.3390/technologies14030166",
    "cited_by": 0,
    "snippet": "",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": false,
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    "devices": [],
    "cites_seed": [
      "PLoS-AHaH-2014",
      "Campbell-SDC-2016"
    ],
    "provenance": "cites-harvest",
    "abstract": "Memristors are valuable elements with very good memory and switching features. They have minimal power consumption, nano-scale sizes, and a possibility for integration with high-density Complementary Metal Oxide Semiconductor (CMOS) integrated circuits. They are applicable in neural networks, memory crossbars, and different electronic devices. This work considers some improved and existing models for memristors, functioning at high-frequency signals with a high speed and very good effectiveness. The main parasitic parameters—series resistance, capacitance, and small-signal direct current (DC) voltage and current shifting signals—are taken into account. An additional leakage conductance is analyzed as a parasitic component. The influence of the parasitic parameters on the normal functioning of memristor-based circuits is analyzed and evaluated at hard-switching and soft-switching modes. For investigations of the main characteristics of the considered models and their applicability in memory arrays, Linear Technology Simulation Program with Integrated Circuits Emphasis (LTSPICE) library models are generated and analyzed. The considered models operate at low-, middle- and high-frequency signals, clearly demonstrating the main properties of memristors. Their appropriate operation in passive memory arrays is analyzed and established. The proposed models have a 26% enhanced accuracy in fitting experimental i-v relations. They ensure good memory and switching properties for memory arrays. This work could be a suitable step towards the design and manufacturing of ultra-high-density memristor-based integrated chips.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://doi.org/10.3390/technologies14030166",
    "openalex_id": "https://openalex.org/W7134093220",
    "pdf_knowm": "uses-device",
    "relevance": "core",
    "knowm_role": "uses-knowm-device",
    "human_verdict": "uses-knowm-device",
    "human_reason": "YES (PDF): measures a Knowm Inc. self-directed-channel memristor (i-v) and fits the model to it"
  },
  {
    "cluster_id": "6307049866063384022",
    "title": "Training of artificial neural networks",
    "authors": [
      "M Le Gallo-Bourdeau",
      "NS Rajalekshmi"
    ],
    "first_author_last": "Gallo-Bourdeau",
    "year": 2022,
    "venue": "US Patent …",
    "link": "https://patents.google.com/patent/US11386319/en",
    "doi": null,
    "cited_by": 12,
    "snippet": "Methods and apparatus are provided for training an artificial neural network, having a succession of neuron layers with interposed synaptic layers each storing a respective set of …",
    "pdf_url": "https://patentimages.storage.googleapis.com/d4/91/ec/42c4dd5b127f1d/US11386319.pdf",
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  {
    "cluster_id": "1945924754510373995",
    "title": "Ferroelectric tunnel junctions: memristors for neuromorphic computing",
    "authors": [
      "S Boyn"
    ],
    "first_author_last": "Boyn",
    "year": 2016,
    "venue": "",
    "link": "https://theses.hal.science/tel-01382194/",
    "doi": "10.70675/e7c2cd52z53cdz4426z801dz58e6a2127289",
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    "snippet": "Classical computer architectures are optimized to process pre-formatted information in a deterministic way and therefore struggle to treat unorganized natural data (images, sounds …",
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    "abstract": "Jonctions tunnel ferroélectriques : memristors pour le calcul neuromorphique Les architectures d’ordinateur classiques sont optimisées pour le traitement déterministe d’informations pré-formatées et ont donc des difficultés avec des données naturelles bruitées (images, sons, etc.). Comme celles-ci deviennent nombreuses, de nouveaux circuits neuromorphiques (inspirés par le cerveau) tels que les réseaux de neurones émergent. Des nano-dispositifs, appelés memristors, pourraient permettre leur implémentation sur puce avec une haute efficacité énergétique et en s’approchant de la haute connectivité synaptique du cerveau.Dans ce travail, nous étudions des memristors basés sur des jonctions tunnel ferroélectriques qui sont composées d’une couche ferroélectrique ultramince entre deux électrodes métalliques. Nous montrons que le renversement de la polarisation de BiFeO3 induit des changements de résistance de quatre ordres de grandeurs et établissons un lien direct entre les états de domaines mixtes et les niveaux de résistance intermédiaires.En alternant les matériaux des électrodes, nous révélons leur influence sur la barrière électrostatique et les propriétés dynamiques des memristors. Des expériences d’impulsion unique de tension montrent un retournement de polarisation ultra-rapide. Nous approfondissons l’étude de cette dynamique par des mesures d’impulsions cumulées. La combinaison de leur analyse avec de l’imagerie par microscopie à force piézoélectrique nous permet d’établir un modèle dynamique du memristor. Suite à la démonstration de la spike-timing-dependent plasticity, une règle d’apprentissage importante, nous pouvons prédire le comportement de notre synapse artificielle. Ceci représente une avance majeure vers la réalisation de réseaux de neurones sur puce dotés d’un auto-apprentissage non-supervisé.",
    "abstract_source": "openalex",
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    "human_reason": "CITE (abstract): own ferroelectric-tunnel-junction memristor; cites PLoS",
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  },
  {
    "cluster_id": "1949682069743411753",
    "title": "Diverse, noisy and parallel: a new spiking neural network approach for humanoid robot control",
    "authors": [
      "R de Azambuja",
      "A Cangelosi"
    ],
    "first_author_last": "Azambuja",
    "year": 2016,
    "venue": "International Joint …",
    "link": "https://ieeexplore.ieee.org/abstract/document/7727325/",
    "doi": "10.1109/ijcnn.2016.7727325",
    "cited_by": 11,
    "snippet": "How exactly our brain works is still an open question, but one thing seems to be clear: biological neural systems are computationally powerful, robust and noisy. Using the …",
    "pdf_url": "https://pearl.plymouth.ac.uk/cgi/viewcontent.cgi?article=2570&context=secam-research",
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    "abstract": "How exactly our brain works is still an open question, but one thing seems to be clear: biological neural systems are computationally powerful, robust and noisy. Using the Reservoir Computing paradigm based on Spiking Neural Networks, also known as Liquid State Machines, we present results from a novel approach where diverse and noisy parallel reservoirs, totalling 3,000 modelled neurons, work together receiving the same averaged feedback. Inspired by the ideas of action learning and embodiment we use the safe and flexible industrial robot BAXTER in our experiments. The robot was taught to draw three different 2D shapes on top of a desk using a total of four joints. Together with the parallel approach, the same basic system was implemented in a serial way to compare it with our new method. The results show our parallel approach enables BAXTER to produce the trajectories to draw the learned shapes more accurately than the traditional serial one.",
    "abstract_source": "openalex",
    "oa_pdf_url": "http://hdl.handle.net/10026.1/10536",
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  {
    "cluster_id": "9989747349058414529",
    "title": "Gradient decomposition methods for training neural networks with non-ideal synaptic devices",
    "authors": [
      "J Zhao",
      "S Huang",
      "O Yousuf",
      "Y Gao"
    ],
    "first_author_last": "Zhao",
    "year": 2021,
    "venue": "Frontiers in Neuroscience",
    "link": "https://www.frontiersin.org/journals/neuroscience/articles/10.3389/fnins.2021.749811/full",
    "doi": "10.3389/fnins.2021.749811/full",
    "cited_by": 9,
    "snippet": "While promising for high-capacity machine learning accelerators, memristor devices have non-idealities that prevent software-equivalent accuracies when used for online training …",
    "pdf_url": "https://www.frontiersin.org/journals/neuroscience/articles/10.3389/fnins.2021.749811/pdf",
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    "abstract": "While promising for high-capacity machine learning accelerators, memristor devices have non-idealities that prevent software-equivalent accuracies when used for online training. This work uses a combination of Mini-Batch Gradient Descent (MBGD) to average gradients, stochastic rounding to avoid vanishing weight updates, and decomposition methods to keep the memory overhead low during mini-batch training. Since the weight update has to be transferred to the memristor matrices efficiently, we also investigate the impact of reconstructing the gradient matrixes both internally ( rank-seq ) and externally ( rank-sum ) to the memristor array. Our results show that streaming batch principal component analysis (streaming batch PCA) and non-negative matrix factorization (NMF) decomposition algorithms can achieve near MBGD accuracy in a memristor-based multi-layer perceptron trained on the MNIST (Modified National Institute of Standards and Technology) database with only 3 to 10 ranks at significant memory savings. Moreover, NMF rank-seq outperforms streaming batch PCA rank-seq at low-ranks making it more suitable for hardware implementation in future memristor-based accelerators.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://doi.org/10.3389/fnins.2021.749811",
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  },
  {
    "cluster_id": "1805124326563932487",
    "title": "Analysis of Memristor-Based Neural Networks and Logic Circuits for Artificial Intelligence Using Standard and Improved Memristor Models",
    "authors": [
      "K Stoyan",
      "T Georgi",
      "M Valeri"
    ],
    "first_author_last": "Stoyan",
    "year": 2026,
    "venue": "Electronics",
    "link": "https://search.proquest.com/openview/4b15922eca648435f392a61f3b2818b4/1?pq-origsite=gscholar&cbl=2032404",
    "doi": "10.3390/electronics15122713",
    "cited_by": 0,
    "snippet": "Memristors are state-of-the-art electronic elements with nano sizes, about 3 nm dimensions, with very good nano-second switching and memory properties, low power usage of about …",
    "pdf_url": null,
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    "abstract": "Memristors are state-of-the-art electronic elements with nano sizes, about 3 nm dimensions, with very good nano-second switching and memory properties, low power usage of about 100 µW, and good compatibility with the current technology of CMOS-integrated chips and circuits. These components are potentially applicable in T-byte memory arrays, artificial neural networks, logic gates and many other digital and analog electronic schemes and devices for artificial intelligence. This paper presents the application of some simple and fast-operating modified memristor models with activation thresholds in neural networks and logic circuits. MATLAB ver. 2016a and LTSPICE ver. XVII products are used for the analysis of memristor neural nets and logical circuits for artificial intelligence. Several simple, accurate and fast-operating existing modified memristor models, together with several frequently used standard memristor models, are utilized for the associated analyses and simulations. A comparison between the used memristor models is conducted. The considered memristor models are tuned, using experimentally recorded i-v relations of tungsten-sulfide Knowm memristors. An accurate functioning of the analyzed neural nets and logic functions is confirmed by the derived results. The considered modified memristor models, neural networks and logic schemes are important in modeling and analysis of memristor-based circuits for ultra-high-density artificial intelligence-integrated chips.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://www.mdpi.com/2079-9292/15/12/2713/pdf?version=1781792625",
    "openalex_id": "https://openalex.org/W7165155236",
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  },
  {
    "cluster_id": "13393061823731281047",
    "title": "Coexistence of bipolar and unipolar memristor switching behavior",
    "authors": [
      "S Ghedira",
      "FO Rziga",
      "K Mbarek"
    ],
    "first_author_last": "Ghedira",
    "year": 2019,
    "venue": "IntechOpen eBooks",
    "link": "https://www.intechopen.com/chapters/66818",
    "doi": "10.5772/intechopen.85176",
    "cited_by": 6,
    "snippet": "The memristor has been theoretically investigated as one of the fundamental electrical elements by Pr. Leon Chua in 1971. Meanwhile, its electrical characteristics are not yet fully …",
    "pdf_url": null,
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    "abstract": "The memristor has been theoretically investigated as one of the fundamental electrical elements by Pr. Leon Chua in 1971. Meanwhile, its electrical characteristics are not yet fully understood. The nonlinear characteristics and the ability to examine large-scale amounts of storing data of this device reveal an interesting development in emerging electronic systems. Research on memristor modeling based on SPICE tools has grown rapidly. This leads us to study the behavior of such devices. Our aim is to simulate different types of memristor behavior. The adjustment of the model is based on the implementation of several parameters, which enables the switching of this device. In this chapter, we prove the flexibility and the correlation of memristor model with different memristive characterization data, by applying different voltage bias, sinusoidal and with a repetitive sweeping. Moreover, we demonstrate the memristor behavior as four types of switching. This includes bipolar switching, unipolar switching, bipolar switching with forgetting effect, and a reversible process between bipolar and unipolar switching. In order to validate this study, we compare our simulation results with experimental data and we prove a good agreement. The SPICE model used in our simulations shows a special advantage for its flexibility and simplicity.",
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    "oa_pdf_url": "https://www.intechopen.com/citation-pdf-url/66818",
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    "human_reason": "CITE (abstract): SPICE switching model; cites PLoS",
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  },
  {
    "cluster_id": "2582141639036355894",
    "title": "Characterization, and modeling of memristor devices",
    "authors": [
      "K Mbarek",
      "FO Rziga",
      "S Ghedira"
    ],
    "first_author_last": "Mbarek",
    "year": 2017,
    "venue": "… on Engineering & MIS …",
    "link": "https://ieeexplore.ieee.org/abstract/document/8273032/",
    "doi": "10.1109/icemis.2017.8273032",
    "cited_by": 5,
    "snippet": "The memristor is a passive two-terminal device that has been invented in 1971 by L. Chua and manufactured in 2008 by a team led by RS Williams in HP Labs. Notwithstanding the …",
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    "abstract": "The memristor is a passive two-terminal device that has been invented in 1971 by L. Chua and manufactured in 2008 by a team led by R.S. Williams in HP Labs. Notwithstanding the knowledge of its ordinary basic I-V characteristics, its behavior not fully understood until now. Hence, it leads us to study the operating behavior of such device in order to classify and identify its basic characteristics. Recently, several memristor devices have been developed in the literature and modeling SPICE memristors seem to be an adequate modeling technique, for its simplicity and flexibility, in order to analyze memristor models using simple and effective methods. In this paper, we adapt a SPICE memristor model, based on the implementation of several parameters. This enables the changing on the I-V characteristics of the device in order to correlate different memristive characterization data using different types of voltage polarizations. Our simulation results demonstrate the flexibility and reliability of our work model. It has been committed to prove the basic I-V characteristics of such device, the switching behavior of this model for different applications (biological, neuromorphic...).",
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    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W2787768744",
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    "human_reason": "CITE (abstract): SPICE model adaptation; cites PLoS",
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  },
  {
    "cluster_id": "5850237201626719580",
    "title": "Memristive analog computing and innovative sensors for neuromorphic systems",
    "authors": [
      "F Moro"
    ],
    "first_author_last": "Moro",
    "year": 2023,
    "venue": "",
    "link": "https://theses.hal.science/tel-04842195/",
    "doi": "10.70675/4846a75az25f1z436az945bz985f565ac361",
    "cited_by": 0,
    "snippet": "Neuromorphic engineering is a field of research in which the latest technology is used to build the next generation of computing and sensing systems, inspired by biological neural …",
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    "abstract": "Calcul analogique memristif et capteurs innovants pour systèmes neuromorphiques L'ingénierie neuromorphique est un domaine de recherche dans lequel les dernières technologies sont utilisées pour construire la prochaine génération de systèmes informatiques et de détection, inspirés des systèmes neuronaux biologiques. Le terme neuromorphique a été inventé à la fin des années 1980 par Carver Mead, faisant référence aux circuits électroniques correspondant étroitement aux principes du calcul biologique. Aujourd'hui, la recherche neuromorphique est devenue un domaine multidisciplinaire rassemblant des scientifiques de différents domaines et travaillant vers des objectifs différents. Ces dernières années, le neuromorphique a gagné en popularité après l'essor du deep learning, une partie de la communauté informatique s'inspirant de la biologie pour un calcul innovant. L'ingénierie neuromorphique a également attiré de nombreux scientifiques des matériaux à la recherche d'applications pour des dispositifs non conventionnels. Le récent ralentissement de la loi de Moore et les coûts croissants de la mise à niveau des nœuds technologiques ont stimulé l'intérêt pour les stratégies informatiques non conventionnelles. Les algorithmes de réseau de neurones, l'épine dorsale de l'intelligence artificielle, ne sont pas facilement implémentés avec les ordinateurs Von Neumann, et l'informatique en mémoire apparaît comme une architecture alternative prometteuse pour l'intelligence artificielle. Cela forme la tempête parfaite pour un changement de paradigme dans les systèmes informatiques et motive le travail de cette thèse. Cette thèse explore le domaine de l'informatique en mémoire avec des mémoires non volatiles pour les systèmes neuromorphiques. Les Resistive Random Access Memories (RRAM) sont intégrées dans une architecture analogique mettant en œuvre un réseau neuronal. Les techniques de formation modernes dérivées du deep learning libèrent tout le potentiel de l'informatique analogique en mémoire. Une architecture modulaire est proposée pour étendre le système à de grands réseaux graphiques. L'informatique basée sur la RRAM est utilisée pour effectuer efficacement la tâche de localisation avec des signaux auditifs. Un système de détection basé sur des piezoelectric micromachined ultrasound transducers (pMUT) de pointe est couplé à un réseau de neurones bio-inspirés, minimisant la consommation d'énergie. Le calcul en mémoire des RRAM est également appliqué à l'olfaction artificielle, où un réseau d'interféromètres Mach-Zender chimiquement fonctionnalisés implémente un capteur de gaz innovant. L'apprentissage en ligne avec un circuit dédié permet une nouvelle utilisation de l'olfaction artificielle. Les mémoires non volatiles sont également impliquées dans de nouvelles formes de calcul, allant au-delà des schémas conventionnels de neuromorphisme. Les RRAM dotent à la fois les synapses et les neurones de mécanismes de plasticité qui coexistent dans un processus d'apprentissage non supervisé. Inspirés des structures complexes des neurones biologiques, des circuits dendritiques sont proposés, prolongeant les architectures de réseaux existantes constituées de neurones et de synapses. Les circuits dendrites améliorent l'efficacité et l'empreinte mémoire des réseaux de neurones neuromorphiques. Les résultats de cette thèse sont significatifs dans les domaines de l'informatique mémoire et des systèmes neuromorphiques.",
    "abstract_source": "openalex",
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    "human_reason": "CITE (abstract): RRAM neuromorphic thesis; cites PLoS",
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  },
  {
    "cluster_id": "1864309520132269406",
    "title": "Mathematical simulation of memristive for classification in machine learning",
    "authors": [
      "AA Hasan",
      "NAZ Abdullah",
      "AD Abbood"
    ],
    "first_author_last": "Hasan",
    "year": 2022,
    "venue": "Periodicals of Engineering and Natural Sciences (PEN)",
    "link": "https://pen.ius.edu.ba/index.php/pen/article/view/584",
    "doi": "10.21533/pen.v10i2.2793",
    "cited_by": 0,
    "snippet": "Over the last few years, neuromorphic computation has been a widely researched topic. One of the neuromorphic computation elements is the memristor. The memristor is a high density …",
    "pdf_url": "https://pen.ius.edu.ba/index.php/pen/article/download/584/292",
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    "abstract": "Over the last few years, neuromorphic computation has been a widely researched topic. One of the neuromorphic computation elements is the memristor. The memristor is a high density, analogue memory storage, and compliance with Ohm's law for minor potential changes. Memristive behaviour imitates synaptic behaviour. It is a nanotechnology that can reduce power consumption, improve synaptic modeling, and reduce data transmission processes. The purpose of this paper is to investigate a customized mathematical model for machine learning algorithms. This model uses a computing paradigm that differs from standard Von-Neumann architectures, and it has the potential to reduce power consumption and increasing performance while doing specialized jobs when compared to regular computers. Classification is one of the most interesting fields in machine learning to classify features patterns by using a specific algorithm. In this study, a classifier based memristive is used with an adaptive spike encoder for input data. We run this algorithm based on Anti-Hebbian and Hebbian learning rules. These investigations employed two of datasets, including breast cancer Wisconsin and Gaussian mixture model datasets. The results indicate that the performance of our algorithm that has been used based on memristive is reasonably close to the optimal solution.",
    "abstract_source": "openalex",
    "oa_pdf_url": "http://pen.ius.edu.ba/index.php/pen/article/download/2793/1103",
    "openalex_id": "https://openalex.org/W4221083815",
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  },
  {
    "cluster_id": "13046389875547972999",
    "title": "Cortical Processing with Thermodynamic-RAM",
    "authors": [
      "MA Nugent",
      "TW Molter"
    ],
    "first_author_last": "Nugent",
    "year": 2014,
    "venue": "arXiv preprint arXiv:1408.3215",
    "link": "https://arxiv.org/abs/1408.3215",
    "doi": null,
    "cited_by": 3,
    "snippet": "AHaH computing forms a theoretical framework from which a biologically-inspired type of computing architecture can be built where, unlike von Neumann systems, memory and …",
    "pdf_url": "https://arxiv.org/pdf/1408.3215",
    "is_knowm": false,
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    "cites_seed": [
      "PLoS-AHaH-2014"
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    "provenance": "cites-harvest",
    "abstract": "AHaH computing forms a theoretical framework from which a biologically-inspired type of computing architecture can be built where, unlike von Neumann systems, memory and processor are physically combined. In this paper we report on an incremental step beyond the theoretical framework of AHaH computing toward the development of a memristor-based physical neural processing unit (NPU), which we call Thermodynamic-RAM (kT-RAM). While the power consumption and speed dominance of such an NPU over von Neumann architectures for machine learning applications is well appreciated, Thermodynamic-RAM offers several advantages over other hardware approaches to adaptation and learning. Benefits include general-purpose use, a simple yet flexible instruction set and easy integration into existing digital platforms. We present a high level design of kT-RAM and a formal definition of its instruction set. We report the completion of a kT-RAM emulator and the successful port of all previous machine learning benchmark applications including unsupervised clustering, supervised and unsupervised classification, complex signal prediction, unsupervised robotic actuation and combinatorial optimization. Lastly, we extend a previous MNIST hand written digits benchmark application, to show that an extra step of reading the synaptic states of AHaH nodes during the train phase (healing) alone results in plasticity that improves the classifier's performance, bumping our best F1 score up to 99.5%.",
    "abstract_source": "semanticscholar",
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  {
    "cluster_id": "13051054340610854772",
    "title": "Simulating memristive networks in systemc-ams",
    "authors": [
      "D Fey",
      "L Riedersberger"
    ],
    "first_author_last": "Fey",
    "year": 2018,
    "venue": "InTech eBooks",
    "link": "https://books.google.com/books?hl=en&lr=&id=TP2PDwAAQBAJ&oi=fnd&pg=PA147&ots=y24-hy8_TO&sig=2966yy6CB-7Z8DIJvplL7VTsurA",
    "doi": "10.5772/intechopen.69662",
    "cited_by": 2,
    "snippet": "This chapter presents a solution for the simulation of large memristive networks with SystemC-AMS. SystemC-AMS allows simulating memristors both on analogue level and on …",
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    "provenance": "cites-harvest",
    "abstract": "This chapter presents a solution for the simulation of large memristive networks with SystemC-AMS. SystemC-AMS allows simulating memristors both on analogue level and on digital level to link analogue memristive devices to digital circuits and system level specifications. We investigate the benefits and drawbacks of a SystemC-AMS simulation compared to a simulation in SPICE. We show for the example of a two-layer memristive network emulating an optical flow algorithm by the detection of moving edges that large memristive networks can be simulated with a free available SystemC-AMS simulation environment, whereas free available SPICE simulation environment fails. However, it is also shown that commercial SPICE simulators are superior against current SystemC-AMS implementations concerning the size of simulated memristive networks. However, SystemC-AMS simulations of memristive networks offer both still more flexibility and similar run times compared to commercial SPICE simulators for small-sized memristive networks. The flexibility and the powerfulness of a SystemC-AMS solution is demonstrated for a complex network that solves edge detection, filtering and detecting of moving objects. The possible run times of the memristive network are determined in the SystemC-AMS simulation environment and are compared with an optical flow algorithm on classical hardware like a CPU and a GPU.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://www.intechopen.com/citation-pdf-url/56096",
    "openalex_id": "https://openalex.org/W2795492318",
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    "relevance": "core",
    "knowm_role": "uses-knowm-model",
    "human_verdict": "uses-knowm-model",
    "human_reason": "YES (PDF): uses the Knowm memristor model (not Biolek) in SystemC-AMS simulations"
  },
  {
    "cluster_id": "Q1r8r7Ng6pcJ",
    "title": "A coupled backward stochastic differential equation (BSDE) framework for metastable transition precursors in a stochastically forced Duffing oscillator",
    "authors": [
      "D Feng"
    ],
    "first_author_last": "Feng",
    "year": 2026,
    "venue": "SSRN Electronic Journal",
    "link": "https://papers.ssrn.com/sol3/papers.cfm?abstract_id=6689318",
    "doi": "10.2139/ssrn.6689318",
    "cited_by": 0,
    "snippet": "This work develops a coupled backward stochastic differential equation framework for metastable transition precursors in a stochastically forced Duffing oscillator. The nonlinear …",
    "pdf_url": "https://papers.ssrn.com/sol3/Delivery.cfm?abstractid=6689318",
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
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      "PLoS-AHaH-2014"
    ],
    "provenance": "cites-harvest",
    "abstract": null,
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    "oa_pdf_url": "https://doi.org/10.2139/ssrn.6689318",
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    "relevance": "cites",
    "knowm_role": "cites",
    "human_verdict": "cites-only",
    "human_reason": "CITE (PDF): generic metastable-switching math (BSDE/Feynman-Kac); Nugent-Molter cited in refs, not the MSS model",
    "cites_reviewed": true
  },
  {
    "cluster_id": "16854182903853321832",
    "title": "Performance Assessment of Memristor Networks as Shortest Path Problem Solvers",
    "authors": [
      "C Fernandez",
      "I Vourkas"
    ],
    "first_author_last": "Fernandez",
    "year": 2020,
    "venue": "IEEE International Symposium …",
    "link": "https://ieeexplore.ieee.org/abstract/document/9181109/",
    "doi": null,
    "cited_by": 1,
    "snippet": "It has been shown that networks of memristors are promising as computing medium for the solution of complex optimization problems. In this context, the solution to the shortest-path …",
    "pdf_url": "http://confcats-event-sessions.s3.amazonaws.com/iscas20/slides/2188.pdf",
    "is_knowm": false,
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    "cites_seed": [
      "PLoS-AHaH-2014",
      "Nugent-TRAM-2017"
    ],
    "provenance": "cites-harvest",
    "abstract": "It has been shown that networks of memristors are promising as computing medium for the solution of complex optimization problems. In this context, the solution to the shortest-path problem (SPP) in a two-dimensional plane has been given wide consideration. Some still open problems in such computing approach concern the time required for the network to reach to a steady state, and the time required to read the result, stored in the state of a subset of memristors that represent the solution. This paper presents a circuit simulation-based performance assessment of memristor networks as SPP solvers. A previous methodology is extended to support weighted directed graphs. We use memristor device models with fundamentally different switching behavior, to check their suitability for such applications. Furthermore, the requirement of binary vs. analog operation of memristors is evaluated. Finally, this approach is compared to known algorithmic solutions to the SPP over a set of large random graphs. Our results contribute to the development of bio-inspired memristor network-based SPP solvers.",
    "abstract_source": "ieee-xplore",
    "oa_pdf_url": null,
    "openalex_id": null,
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    "human_verdict": "cites-only",
    "human_reason": "CITE (abstract): memristor-network shortest-path solver; cites PLoS/Nugent",
    "cites_reviewed": true
  },
  {
    "cluster_id": "16813615423641677035",
    "title": "AHaH computing with thermodynamic RAM: bridging the technology stack",
    "authors": [
      "A Nugent"
    ],
    "first_author_last": "Nugent",
    "year": 2014,
    "venue": "Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE",
    "link": "https://www.spiedigitallibrary.org/conference-proceedings-of-spie/9119/911905/AHaH-computing-with-thermodynamic-RAM-bridging-the-technology-stack/10.1117/12.2053381.short",
    "doi": "10.1117/12.2053381.short",
    "cited_by": 0,
    "snippet": "We introduce the motivations behind AHaH computing, an emerging new form of adaptive computing with many applications in machine learning. We then present a technology stack …",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": true,
    "devices": [],
    "cites_seed": [
      "PLoS-AHaH-2014"
    ],
    "provenance": "cites-harvest",
    "abstract": "We introduce the motivations behind AHaH computing, an emerging new form of adaptive computing with many applications in machine learning. We then present a technology stack or specification describing the multiple levels of abstraction and specialization needed to support AHaH computing.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W2089719095",
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    "relevance": "core",
    "knowm_role": "named-in-abstract"
  },
  {
    "cluster_id": "17086643668193299913",
    "title": "Universal computation using localized limit-cycle attractors in neural networks",
    "authors": [
      "L Baumgarten",
      "S Bornholdt"
    ],
    "first_author_last": "Baumgarten",
    "year": 2021,
    "venue": "arXiv preprint arXiv:2112.05558",
    "link": "https://arxiv.org/abs/2112.05558",
    "doi": null,
    "cited_by": 0,
    "snippet": "Neural networks are dynamical systems that compute with their dynamics. One example is the Hopfield model, forming an associative memory which stores patterns as global …",
    "pdf_url": "https://arxiv.org/pdf/2112.05558",
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "PLoS-AHaH-2014"
    ],
    "provenance": "cites-harvest",
    "abstract": "Neural networks are dynamical systems that compute with their dynamics. One example is the Hopfield model, forming an associative memory which stores patterns as global attractors of the network dynamics. From studies of dynamical networks it is well known that localized attractors also exist. Yet, they have not been used in computing paradigms. Here we show that interacting localized attractors in threshold networks can result in universal computation. We develop a rewiring algorithm that builds universal Boolean gates in a biologically inspired two-dimensional threshold network with randomly placed and connected nodes using collision-based computing. We aim at demonstrating the computational capabilities and the ability to control local limit cycle attractors in such networks by creating simple Boolean gates by means of these local activations. The gates use glider guns, i.e., localized activity that periodically generates ”gliders” of activity that propagate through space. Several such gliders are made to collide, and the result of their interaction is used as the output of a Boolean gate. We show that these gates can be used to build a universal computer.",
    "abstract_source": "semanticscholar",
    "oa_pdf_url": null,
    "openalex_id": null,
    "pdf_knowm": "none",
    "relevance": "cites",
    "knowm_role": "cites",
    "human_verdict": "cites-only",
    "human_reason": "CITE (PDF): limit-cycle attractor networks; Nugent-Molter cited in refs",
    "cites_reviewed": true
  },
  {
    "cluster_id": "16391711436874779313",
    "title": "Gradient Decomposition Methods for Training Neural Networks with Non-Ideal Weights",
    "authors": [
      "J Zhao"
    ],
    "first_author_last": "Zhao",
    "year": 2021,
    "venue": "Frontiers in Neuroscience",
    "link": "https://search.proquest.com/openview/e38c23bd8f8b412ceed0b447f106f9f9/1?pq-origsite=gscholar&cbl=18750&diss=y",
    "doi": "10.3389/fnins.2021.749811",
    "cited_by": 9,
    "snippet": "Resistive switching (memristor) devices are an emerging hardware technology useful for the implementation of dense and efficient synaptic weights in artificial neural networks. Prior …",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "PLoS-AHaH-2014"
    ],
    "provenance": "cites-harvest",
    "abstract": "While promising for high-capacity machine learning accelerators, memristor devices have non-idealities that prevent software-equivalent accuracies when used for online training. This work uses a combination of Mini-Batch Gradient Descent (MBGD) to average gradients, stochastic rounding to avoid vanishing weight updates, and decomposition methods to keep the memory overhead low during mini-batch training. Since the weight update has to be transferred to the memristor matrices efficiently, we also investigate the impact of reconstructing the gradient matrixes both internally ( rank-seq ) and externally ( rank-sum ) to the memristor array. Our results show that streaming batch principal component analysis (streaming batch PCA) and non-negative matrix factorization (NMF) decomposition algorithms can achieve near MBGD accuracy in a memristor-based multi-layer perceptron trained on the MNIST (Modified National Institute of Standards and Technology) database with only 3 to 10 ranks at significant memory savings. Moreover, NMF rank-seq outperforms streaming batch PCA rank-seq at low-ranks making it more suitable for hardware implementation in future memristor-based accelerators.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://doi.org/10.3389/fnins.2021.749811",
    "openalex_id": "https://openalex.org/W3215918518",
    "pdf_knowm": "uses-model",
    "relevance": "cites",
    "knowm_role": "cites",
    "human_verdict": "cites-only",
    "human_reason": "CITE (PDF): same Zhao paper (dup record); Nugent-Molter cited in refs",
    "cites_reviewed": true
  },
  {
    "cluster_id": "RRzuljM2ViIJ",
    "title": "Coexistence of Bipolar and Unipolar Memristor Switching",
    "authors": [
      "S Ghedira",
      "FO Rziga",
      "K Mbarek"
    ],
    "first_author_last": "Ghedira",
    "year": 2019,
    "venue": "IntechOpen eBooks",
    "link": "https://books.google.com/books?hl=en&lr=&id=qGX8DwAAQBAJ&oi=fnd&pg=PA27&ots=LxMsla4dYi&sig=dapcM-DbL4knVKWIYToIKQBf9pI",
    "doi": "10.5772/intechopen.85176",
    "cited_by": 6,
    "snippet": "The memristor has been theoretically investigated as one of the fundamental electrical elements by Pr. Leon Chua in 1971. Meanwhile, its electrical characteristics are not yet fully …",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "PLoS-AHaH-2014"
    ],
    "provenance": "cites-harvest",
    "abstract": "The memristor has been theoretically investigated as one of the fundamental electrical elements by Pr. Leon Chua in 1971. Meanwhile, its electrical characteristics are not yet fully understood. The nonlinear characteristics and the ability to examine large-scale amounts of storing data of this device reveal an interesting development in emerging electronic systems. Research on memristor modeling based on SPICE tools has grown rapidly. This leads us to study the behavior of such devices. Our aim is to simulate different types of memristor behavior. The adjustment of the model is based on the implementation of several parameters, which enables the switching of this device. In this chapter, we prove the flexibility and the correlation of memristor model with different memristive characterization data, by applying different voltage bias, sinusoidal and with a repetitive sweeping. Moreover, we demonstrate the memristor behavior as four types of switching. This includes bipolar switching, unipolar switching, bipolar switching with forgetting effect, and a reversible process between bipolar and unipolar switching. In order to validate this study, we compare our simulation results with experimental data and we prove a good agreement. The SPICE model used in our simulations shows a special advantage for its flexibility and simplicity.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://www.intechopen.com/citation-pdf-url/66818",
    "openalex_id": "https://openalex.org/W2941287996",
    "pdf_knowm": "uses-model",
    "relevance": "cites",
    "knowm_role": "cites",
    "human_verdict": "cites-only",
    "human_reason": "CITE (abstract): same Ghedira chapter (dup record); cites PLoS",
    "cites_reviewed": true
  },
  {
    "cluster_id": "YRqyNVO0XpIJ",
    "title": "Retinal and Neural Dynamics using Memristor-CMOS Architectures",
    "authors": [
      "J Eshraghian"
    ],
    "first_author_last": "Eshraghian",
    "year": 2019,
    "venue": "",
    "link": "https://research-repository.uwa.edu.au/en/publications/retinal-and-neural-dynamics-using-memristor-cmos-architectures/",
    "doi": null,
    "cited_by": 0,
    "snippet": "This thesis is dedicated to the application of ReRAM and memristive systems, to reconstructing the neural dynamics within the retina and the brain. In its present operative …",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "PLoS-AHaH-2014"
    ],
    "provenance": "cites-harvest",
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": null,
    "pdf_knowm": "uses-model",
    "relevance": "core",
    "knowm_role": "uses-knowm-device",
    "human_verdict": "uses-knowm-device",
    "human_reason": "YES (PDF): thesis uses crossbar arrays purchased from Knowm for analogue-weight experiments"
  },
  {
    "cluster_id": "16306618599086901973",
    "title": "Action Learning Experiments Using Spiking Neural Networks and Humanoid Robots",
    "authors": [
      "R De Azambuja"
    ],
    "first_author_last": "Azambuja",
    "year": 2018,
    "venue": "",
    "link": "https://pearl.plymouth.ac.uk/cgi/viewcontent.cgi?article=1253&context=secam-theses",
    "doi": null,
    "cited_by": 0,
    "snippet": "The way our brain works is still an open question, but one thing seems to be clear: biological neural systems are computationally powerful, robust and noisy. Natural nervous system are …",
    "pdf_url": "https://pearl.plymouth.ac.uk/cgi/viewcontent.cgi?article=1253&context=secam-theses",
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "PLoS-AHaH-2014"
    ],
    "provenance": "cites-harvest",
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": null,
    "pdf_knowm": "uses-model",
    "relevance": "cites",
    "knowm_role": "cites",
    "human_verdict": "cites-only",
    "human_reason": "CITE (PDF): reservoir/LSM robot control; AHaH cited as related work",
    "cites_reviewed": true
  },
  {
    "cluster_id": "wZl6eWLjbCMJ",
    "title": "Memristive Stateful Logic Gates for In-Memory Computing Applications",
    "authors": [
      "MA Lebdeh"
    ],
    "first_author_last": "Lebdeh",
    "year": 2017,
    "venue": "",
    "link": "https://khazna.ku.ac.ae/files/6827732/file/",
    "doi": null,
    "cited_by": 0,
    "snippet": "Applications”, Master's thesis, MSc in Electrical and Computer Engineering, Department of Electrical and Computer Engineering, Khalifa University of Science and Technology, United …",
    "pdf_url": "https://khazna.ku.ac.ae/files/6827732/file/",
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "PLoS-AHaH-2014"
    ],
    "provenance": "cites-harvest",
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": null,
    "pdf_knowm": "uses-model",
    "relevance": "cites",
    "knowm_role": "cites",
    "human_verdict": "cites-only",
    "human_reason": "CITE (PDF): stateful logic; Nugent-Molter cited in refs",
    "cites_reviewed": true
  },
  {
    "cluster_id": "15178454882846413081",
    "title": "Thermodynamisches Rechnen: Neuromorphe Computerarchitekturen Teil 2",
    "authors": [
      "T Molter",
      "MA Nugent"
    ],
    "first_author_last": "Molter",
    "year": 2018,
    "venue": "Physik in unserer Zeit",
    "link": "https://onlinelibrary.wiley.com/doi/abs/10.1002/piuz.201801499",
    "doi": "10.1002/piuz.201801499",
    "cited_by": 1,
    "snippet": "Thermodynamische Bits bestehen aus zwei in Serie geschalteten Memristoren und lassen sich als künstliche Synapsen mit Befehlssätzen steuern. Mehrere von ihnen bilden ein …",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "PLoS-AHaH-2014"
    ],
    "provenance": "cites-harvest",
    "abstract": "Zusammenfassung Thermodynamische Bits bestehen aus zwei in Serie geschalteten Memristoren und lassen sich als künstliche Synapsen mit Befehlssätzen steuern. Mehrere von ihnen bilden ein thermodynamisches Neuron, das Lernregeln gehorchen kann. Solche kT‐Neuronen können fast alle Funktionen von Logikgattern nachahmen. Mit ihnen sind rekonfigurierbare Logikgatter konstruierbar, die erheblich Platz, Gewicht und Energie im Vergleich zu digitalen Prozessoren einsparen können. Sie könnten die Basis für eine zukünftige neuromorphe Computerarchitektur bilden.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W2800139405",
    "pdf_knowm": "unknown",
    "relevance": "core",
    "knowm_role": "uses-knowm-model",
    "human_verdict": "uses-knowm-model",
    "human_reason": "YES: Knowm's own work (Molter) — popular-science article on thermodynamic/AHaH computing"
  },
  {
    "cluster_id": "2640380897273349091",
    "title": "Reconfigurable Electronics and Non-Volatile Memory Research",
    "authors": [
      "KA Campbell"
    ],
    "first_author_last": "Campbell",
    "year": 2015,
    "venue": "",
    "link": "https://apps.dtic.mil/sti/html/tr/ADA564795/",
    "doi": "10.21236/ad1000558",
    "cited_by": 0,
    "snippet": "This is a final report for the DEPSCoR grant titled Reconfigurable Electronics and Non-Volatile Memory Research. The primary purpose of this work was to investigate materials …",
    "pdf_url": "https://apps.dtic.mil/sti/pdfs/ADA564795.pdf",
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "PLoS-AHaH-2014"
    ],
    "provenance": "cites-harvest",
    "abstract": "Abstract : This is a final report for the DEPSCoR grant titled Reconfigurable Electronics and Non-Volatile Memory Research. The primary purpose of this work was to investigate materials and fabricate devices that may display electronic properties useful for reconfigurable electronics applications and/or non-volatile memory. The grant enabled the development of microfabrication processes for exotic materials at Boise State University including material synthesis. Single-bit devices, 10 x 10 cross point arrays, 150 x 150 cross point arrays, and 24-pin DIP packaged parts were fabricated with over 10 different materials systems that showed promise for non-volatile memory and reconfigurable electronics. Materials explored included chalcogenides doped with transition metal ions and organics. Devices were discovered that displayed tunable capacitance. Additionally, devices displaying memristive behavior were discovered. This work resulted in two additional AFRL collaborations, an AFRL Educational Partnership Agreement, an SBIR Phase I and an STTR Phase I grant.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W232445355",
    "pdf_knowm": "uses-device",
    "relevance": "core",
    "knowm_role": "uses-knowm-device",
    "human_verdict": "uses-knowm-device",
    "human_reason": "YES (PDF): Campbell's own DTRA report developing the Ge2Se3 self-directed-channel device (Knowm's foundational device work)"
  },
  {
    "cluster_id": "16041489779467936396",
    "title": "Memristor Implementation of a Ternary Storage Circuit",
    "authors": [
      "JB Nilsen"
    ],
    "first_author_last": "Nilsen",
    "year": 2020,
    "venue": "",
    "link": "",
    "doi": null,
    "cited_by": 1,
    "snippet": "",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "PLoS-AHaH-2014",
      "Campbell-SDC-2016"
    ],
    "provenance": "cites-harvest",
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": null,
    "pdf_knowm": "none",
    "relevance": "cites",
    "knowm_role": "cites",
    "human_verdict": "cites-only",
    "human_reason": "CITE (PDF): ternary storage; cites PLoS/Campbell, no Knowm device/model use",
    "cites_reviewed": true
  },
  {
    "cluster_id": "agY5Zi2nRfkJ",
    "title": "Definición y crítica del memristor",
    "authors": [
      "LO Chua"
    ],
    "first_author_last": "Chua",
    "year": null,
    "venue": "",
    "link": "",
    "doi": null,
    "cited_by": 0,
    "snippet": "",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "PLoS-AHaH-2014"
    ],
    "provenance": "cites-harvest",
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": null,
    "pdf_knowm": null,
    "relevance": "cites",
    "knowm_role": "cites",
    "human_verdict": "cites-only",
    "human_reason": "CITE (note): dead end, no PDF",
    "cites_reviewed": true
  },
  {
    "cluster_id": "15117871660536782737",
    "title": "A chaotic circuit based on a physical memristor",
    "authors": [
      "L Minati",
      "LV Gambuzza",
      "WJ Thio",
      "JC Sprott"
    ],
    "first_author_last": "Minati",
    "year": 2020,
    "venue": "Chaos, Solitons & …",
    "link": "https://www.sciencedirect.com/science/article/pii/S0960077920303891",
    "doi": null,
    "cited_by": 140,
    "snippet": "The memristor is a fundamental two-terminal electrical component unique in that it possesses the properties of non-linearity and memory, which are pervasive across natural …",
    "pdf_url": "https://files.wesleythio.com/Webflow_assets/4.Research/thio12.pdf",
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "Molter-MSS-2016",
      "Campbell-SDC-2016"
    ],
    "provenance": "cites-harvest",
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": null,
    "pdf_knowm": "uses-device",
    "relevance": "core",
    "knowm_role": "uses-knowm-device",
    "human_verdict": "uses-knowm-device",
    "human_reason": "YES (PDF): chaotic circuit uses the Knowm Inc. self-directed channel memristor as a nonlinear resistor"
  },
  {
    "cluster_id": "18339054607999893734",
    "title": "High-density memristor-CMOS ternary logic family",
    "authors": [
      "XY Wang",
      "PF Zhou",
      "JK Eshraghian"
    ],
    "first_author_last": "Wang",
    "year": 2020,
    "venue": "… on Circuits and …",
    "link": "https://ieeexplore.ieee.org/abstract/document/9214881/",
    "doi": "10.36227/techrxiv.12598559",
    "cited_by": 2,
    "snippet": "This paper presents the first experimental demonstration of a ternary memristor-CMOS logic family. We systematically design, simulate and experimentally verify the primitive logic …",
    "pdf_url": "https://www.authorea.com/doi/pdf/10.36227/techrxiv.12598559.v1",
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [
      "Sn"
    ],
    "cites_seed": [
      "Molter-MSS-2016"
    ],
    "provenance": "cites-harvest",
    "abstract": "&lt;div&gt;This paper presents the first experimental demonstration&lt;/div&gt;&lt;div&gt;of a ternary memristor-CMOS logic family. We systematically&lt;/div&gt;&lt;div&gt;design, simulate and experimentally verify the primitive&lt;/div&gt;&lt;div&gt;logic functions: the ternary AND, OR and NOT gates. These are then used to build combinational ternary NAND, NOR, XOR and XNOR gates, as well as data handling ternary MAX and MIN gates. Our simulations are performed using a 50-nm process which are verified with in-house fabricated indium-tin-oxide memristors, optimized for fast switching, high transconductance, and low current leakage. We obtain close to an order of magnitude improvement in data density over conventional CMOS logic, and a reduction of switching speed by a factor of 13 over prior state-of-the-art ternary memristor results. We anticipate extensions of this work can realize practical implementation where high data density is of critical importance.&lt;/div&gt;",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://www.techrxiv.org/articles/preprint/High-Density_Memristor-CMOS_Ternary_Logic_Family/12598559/files/23598668.pdf",
    "openalex_id": "https://openalex.org/W4214554236",
    "pdf_knowm": "uses-model",
    "relevance": "core",
    "knowm_role": "uses-knowm-model",
    "human_verdict": "uses-knowm-model",
    "human_reason": "YES (PDF): simulates ternary logic using Knowm's generalized-metastable-switch model"
  },
  {
    "cluster_id": "15119277523680838910",
    "title": "Spatial-temporal hybrid neural network with computing-in-memory architecture",
    "authors": [
      "K Bai",
      "L Liu",
      "Y Yi"
    ],
    "first_author_last": "Bai",
    "year": 2021,
    "venue": "IEEE Transactions on Circuits and Systems I Regular Papers",
    "link": "https://ieeexplore.ieee.org/abstract/document/9406054/",
    "doi": "10.1109/tcsi.2021.3071956",
    "cited_by": 21,
    "snippet": "Deep learning (DL) has gained unprecedented success in many real-world applications. However, DL poses difficulties for efficient hardware implementation due to the needs of a …",
    "pdf_url": "https://par.nsf.gov/servlets/purl/10274093",
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
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    "cites_seed": [
      "Molter-MSS-2016"
    ],
    "provenance": "cites-harvest",
    "abstract": "Deep learning (DL) has gained unprecedented success in many real-world applications. However, DL poses difficulties for efficient hardware implementation due to the needs of a complex gradient-based learning algorithm and the required high memory bandwidth for synaptic weight storage, especially in today's data-intensive environment. Computing-in-memory (CIM) strategies have emerged as an alternative for realizing energy-efficient neuromorphic applications in silicon, reducing resources and energy required for neural computations. In this work, we exploit a CIM-based spatial-temporal hybrid neural network (STHNN) with a unique learning algorithm. To be specific, we integrate both multilayer perceptron and recurrent-based delay-dynamical system, making the network becomes linear separable while processing information in both spatial and temporal domains, better yet, reducing the memory bandwidth and hardware overhead through the CIM architecture. The prototype fabricated in 180 nm CMOS process is built of fully-analog components, yielding an average on-chip classification accuracy up to 86.9% on handprinted alphabet characters with a power consumption of 33 mW. Beyond that, through the handwritten digit database and the radio frequency fingerprinting dataset, software-based numerical evaluations offer 1.6 -to- 9.8 × and 1.9 -to- 4.4 × speedup, respectively, without significantly degrading its classification accuracy compared to the cutting-edge DL approaches.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W3154349591",
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    "relevance": "cites",
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    "human_verdict": "cites-only",
    "human_reason": "CITE (PDF): CIM neuromorphic chip; GMS model only in references",
    "cites_reviewed": true
  },
  {
    "cluster_id": "16531407918617252565",
    "title": "A simple memristor model for memory devices",
    "authors": [
      "S Kirilov"
    ],
    "first_author_last": "Kirilov",
    "year": 2024,
    "venue": "13th International Conference on Modern …",
    "link": "https://ieeexplore.ieee.org/abstract/document/10615437/",
    "doi": "10.1109/mocast61810.2024.10615437",
    "cited_by": 5,
    "snippet": "Memristors are favorable and beneficial electronic components, having respectable memorizing and switching behavior. Owing to their minimal energy requirements, nano …",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "Molter-MSS-2016",
      "Campbell-SDC-2016"
    ],
    "provenance": "cites-harvest",
    "abstract": "Memristors are favorable and beneficial electronic components, having respectable memorizing and switching behavior. Owing to their minimal energy requirements, nano-scale dimensions, and seamless integration with CMOS high-density integrated circuits, memristors hold a potential for application in neural nets, memory arrays, and various electronic configurations. This paper presents an enhanced and simplified model for metal-oxide memristive elements, operating with increased speed and efficiency. For analysis and application in memory matrices, LTSPICE library model is created. The offered memristor model effectively operates in high-frequency mode, representing the key patterns of memristors. Its suitable functioning in complex electronic circuits is analyzed and confirmed.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4401361572",
    "pdf_knowm": null,
    "relevance": "cites",
    "knowm_role": "cites",
    "human_verdict": "cites-only",
    "human_reason": "CITE (abstract): metal-oxide LTSPICE model; cites Molter/Campbell",
    "cites_reviewed": true
  },
  {
    "cluster_id": "8225000574456704236",
    "title": "Delay conditioned generative modelling of resistive drift in memristors",
    "authors": [
      "W El-Geresy",
      "C Papavassiliou",
      "D Gündüz"
    ],
    "first_author_last": "El-Geresy",
    "year": 2026,
    "venue": "ACM Journal on Emerging Technologies in Computing Systems",
    "link": "https://dl.acm.org/doi/abs/10.1145/3821412",
    "doi": "10.1145/3821412",
    "cited_by": 0,
    "snippet": "The modelling of memristive devices is an essential part of the development of novel in-memory computing systems. Models are needed to enable the accurate and efficient …",
    "pdf_url": "https://dl.acm.org/doi/pdf/10.1145/3821412",
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "Molter-MSS-2016"
    ],
    "provenance": "cites-harvest",
    "abstract": "The modelling of memristive devices is an essential part of the development of novel in-memory computing systems. Models are needed to enable the accurate and efficient simulation of memristor device characteristics, for purposes of testing the performance of the devices or the feasibility of their use in future neuromorphic and in-memory computing architectures. The consideration of memristor non-idealities is an essential part of any modelling approach. The nature of the deviation of memristive devices from their initial state, particularly at ambient temperature and in the absence of a stimulating voltage, is of key interest, as it dictates their reliability as information storage media - a property that is of importance for both traditional storage and neuromorphic applications. In this paper, we investigate the use of a generative modelling approach for the simulation of the delay and initial resistance-conditioned resistive drift distribution of memristive devices. We introduce a data normalisation scheme and a novel training technique to allow the model to be conditioned on the continuous inputs. The proposed generative modelling approach is suited for use in end-to-end training and device modelling scenarios, including learned data storage, due to its differentiability and ability to generate target-delay samples without recurrent evaluation.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://arxiv.org/pdf/2408.01539",
    "openalex_id": "https://openalex.org/W4406444229",
    "pdf_knowm": "uses-model",
    "relevance": "cites",
    "knowm_role": "cites",
    "human_verdict": "cites-only",
    "human_reason": "CITE (PDF): generative drift model; cites Molter/Nugent, no Knowm device/model use",
    "cites_reviewed": true
  },
  {
    "cluster_id": "12335725909723428629",
    "title": "Probabilistic memristive networks: Application of a master equation to networks of binary ReRAM cells",
    "authors": [
      "VJ Dowling",
      "VA Slipko",
      "YV Pershin"
    ],
    "first_author_last": "Dowling",
    "year": 2020,
    "venue": "Chaos Solitons & Fractals",
    "link": "https://www.sciencedirect.com/science/article/pii/S0960077920307797",
    "doi": "10.1016/j.chaos.2020.110385",
    "cited_by": 20,
    "snippet": "The possibility of using non-deterministic circuit components has been gaining significant attention in recent years. The modeling and simulation of their circuits require novel …",
    "pdf_url": "https://arxiv.org/pdf/2003.11011",
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "Molter-MSS-2016"
    ],
    "provenance": "cites-harvest",
    "abstract": "Abstract The possibility of using non-deterministic circuit components has been gaining significant attention in recent years. The modeling and simulation of their circuits require novel approaches, as now the state of a circuit at an arbitrary moment in time cannot be predicted deterministically. Generally, these circuits should be described in terms of probabilities, the circuit variables should be calculated on average, and correlation functions should be used to explore interrelations among the variables. In this paper, we use, for the first time, a master equation to analyze the networks composed of probabilistic binary memristors. Analytical solutions of the master equation for the case of identical memristors connected in-series and in-parallel are found. Our analytical results are supplemented by results of numerical simulations that extend our findings beyond the case of identical memristors. The approach proposed in this paper facilitates the development of probabilistic/stochastic electronic circuits and advance their real-world applications.",
    "abstract_source": "semanticscholar",
    "oa_pdf_url": "https://arxiv.org/pdf/2003.11011",
    "openalex_id": "https://openalex.org/W3013734446",
    "pdf_knowm": "uses-model",
    "relevance": "cites",
    "knowm_role": "cites",
    "human_verdict": "cites-only",
    "human_reason": "CITE (abstract): probabilistic-memristor master-equation modeling; cites Molter",
    "cites_reviewed": true
  },
  {
    "cluster_id": "5433620323013418990",
    "title": "Application of metal oxide memristor models in logic gates",
    "authors": [
      "V Mladenov"
    ],
    "first_author_last": "Mladenov",
    "year": 2023,
    "venue": "Electronics",
    "link": "https://www.mdpi.com/2079-9292/12/2/381",
    "doi": "10.3390/electronics12020381",
    "cited_by": 9,
    "snippet": "Memristors, as new electronic elements, have been under rigorous study in recent years, owing to their good memory and switching properties, low power consumption, nano …",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "Molter-MSS-2016"
    ],
    "provenance": "cites-harvest",
    "abstract": "Memristors, as new electronic elements, have been under rigorous study in recent years, owing to their good memory and switching properties, low power consumption, nano-dimensions and a good compatibility to present integrated circuits, related to their promising applications in electronic circuits and chips. The main purpose of this paper is the application and analysis of the operations of metal–oxide memristors in logic gates and complex schemes, using several standard and modified memristor models and a comparison between their behavior in LTSPICE at a hard-switching, paying attention to their fast operation and switching properties. Several basic logic gates—OR, AND, NOR, NAND, XOR, based on memristors and CMOS transistors are considered. The logic schemes based on memristors are applicable in electronic circuits with artificial intelligence. They are analyzed in LTSPICE for pulse signals and a hard-switching functioning of the memristors. The analyses confirm the proper, fast operation and good switching properties of the considered modified memristor models in logical circuits, compared to several standard models. The modified models are compared to several classical models, according to some significant criteria such as operating frequency, simulation time, accuracy, complexity and switching properties. Based on the basic memristor logic gates, a more complex logic scheme is analyzed.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://www.mdpi.com/2079-9292/12/2/381/pdf?version=1674033752",
    "openalex_id": "https://openalex.org/W4315700798",
    "pdf_knowm": "uses-model",
    "relevance": "cites",
    "knowm_role": "cites",
    "human_verdict": "cites-only",
    "human_reason": "CITE (PDF): logic gates with own metal-oxide model; GMS model only in references",
    "cites_reviewed": true
  },
  {
    "cluster_id": "13386581929662592382",
    "title": "A Physics-Regularized Neural Surrogate Framework for Printed Memristors",
    "authors": [
      "SL Jurj"
    ],
    "first_author_last": "Jurj",
    "year": 2026,
    "venue": "IEEE Access",
    "link": "https://ieeexplore.ieee.org/abstract/document/11364217/",
    "doi": "10.1109/access.2026.3658220",
    "cited_by": 0,
    "snippet": "Printed memristors offer a pathway to low-cost, flexible neuromorphic hardware, but their variability and filamentary switching pose challenges for fast, accurate device modeling. We …",
    "pdf_url": "https://ieeexplore.ieee.org/iel8/6287639/6514899/11364217.pdf",
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "Molter-MSS-2016"
    ],
    "provenance": "cites-harvest",
    "abstract": "Printed memristors offer a pathway to low-cost, flexible neuromorphic hardware, but their variability and filamentary switching pose challenges for fast, accurate device modeling. We introduce a Physics-Regularized Neural Surrogate (PRNS) for printed memristors, combining data-driven learning with physics-based regularization terms (masked Ohmic/Space-Charge Limited Current (SCLC) constraints and Ordinary Differential Equation (ODE) consistency). While classical Physics-Informed Neural Networks (PINNs) enforce governing equations through differentiable Partial Differential Equation (PDE)/ODE residuals, here physical relations act as regularization rather than hard constraints. The model embeds Ohmic conduction, SCLC, and interfacial transport equations into network training while explicitly handling device-to-device variability via parameter perturbation and noise injection. We validate the approach on a literature-calibrated synthetic dataset representative of flexographically printed Ag/PMMA:PVA/ITO devices, achieving relative Root Mean Square Error (RRMSE) of 0.0633 versus 0.2730 for the Voltage-ThrEshold Adaptive Memristor (VTEAM) model (4.31× improvement). Cross-validation yields RRMSE 0.115 ± 0.062, with stability under 10% added noise. Extended validation across digitized I-V curves from three printed memristor technologies (inkjet-printed IGZO, aerosol-jet MoS₂, paper-based MoS₂/graphene) demonstrates competitive or superior accuracy versus VTEAM, Yakopcic, Stanford-PKU, and MMS models. Supplementary experiments (15 tests) confirm comprehensive reliability modeling including temperature-dependent retention (activation energy Eₐ = 0.379 eV), endurance degradation (660-cycle lifetime), and electro-thermal coupling effects. Circuit integration via one-transistor-one-resistor (1T1R) memory cell simulation shows 29% lower write energy (94.2 pJ vs. 133.6 pJ) with gradual analog switching. The formulation supports SPICE-compatible lookup table (LUT)/behavioral export; all code and datasets are released openly for reproducibility.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://doi.org/10.1109/access.2026.3658220",
    "openalex_id": "https://openalex.org/W7125802351",
    "pdf_knowm": null,
    "relevance": "cites",
    "knowm_role": "cites",
    "human_verdict": "cites-only",
    "human_reason": "CITE (abstract): printed Ag/PMMA:PVA/ITO memristors, VTEAM comparison; cites Molter, no Knowm use",
    "cites_reviewed": true
  },
  {
    "cluster_id": "5039826142736445856",
    "title": "Majority voting for low power and low complexity preamble detection by hybrid memristor-CMOS architecture",
    "authors": [
      "E Kalanaki",
      "B Ebrahimi",
      "MA Pourmina"
    ],
    "first_author_last": "Kalanaki",
    "year": 2025,
    "venue": "Analog Integrated Circuits and Signal Processing",
    "link": "https://link.springer.com/article/10.1007/s10470-025-02413-0",
    "doi": "10.1007/s10470-025-02413-0",
    "cited_by": 0,
    "snippet": "In modern embedded systems, efficient and low-power communication is essential, especially as these systems increasingly handle concurrent wireless protocols. Preamble …",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "Molter-MSS-2016"
    ],
    "provenance": "cites-harvest",
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4410578017",
    "pdf_knowm": null,
    "relevance": "cites",
    "knowm_role": "cites",
    "human_verdict": "cites-only",
    "human_reason": "CITE (abstract): hybrid-memristor preamble detection; cites Molter, no Knowm device/model use",
    "cites_reviewed": true
  },
  {
    "cluster_id": "11547001991659096219",
    "title": "A stochastic compact model describing memristor plasticity and volatility",
    "authors": [
      "A Malik",
      "C Papavassiliou"
    ],
    "first_author_last": "Malik",
    "year": 2021,
    "venue": "2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)",
    "link": "https://ieeexplore.ieee.org/abstract/document/9665591/",
    "doi": "10.1109/icecs53924.2021.9665591",
    "cited_by": 8,
    "snippet": "A memristor compact model, which can both capture state volatility and describe short-term and long-term memory transitions, is introduced. The model is based on an energy …",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "Molter-MSS-2016"
    ],
    "provenance": "cites-harvest",
    "abstract": "A memristor compact model, which can both capture state volatility and describe short-term and long-term memory transitions, is introduced. The model is based on an energy landscape acting as a pseudo-potential which generates the driving forces for configurational changes. A stable conductance change in this model is implemented through a sequence of transitions between states of plasticity occurring over different time-scales. Such transitions also modify the detail of the pseudopotential landscape, this way altering the probability distribution of subsequent state-change events. This approach departs from the usual method of applying perfectly non-volatile increments on the state variable. The model has been coded in Verilog-A, so that it can be used in many popular SPICE engines. The proposed model is semi-quantitatively fitted to measurements taken on Pt/TiO2/Pt stack memristor devices.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4206490554",
    "pdf_knowm": null,
    "relevance": "cites",
    "knowm_role": "cites",
    "human_verdict": "cites-only",
    "human_reason": "CITE (abstract): compact model fitted to Pt/TiO2/Pt devices; cites Molter",
    "cites_reviewed": true
  },
  {
    "cluster_id": "373826025103076934",
    "title": "Detection through deep neural networks: a reservoir computing approach for mimo-ofdm symbol detection",
    "authors": [
      "K Bai",
      "L Liu",
      "Z Zhou",
      "Y Yi"
    ],
    "first_author_last": "Bai",
    "year": 2020,
    "venue": "… of the 39th International Conference on …",
    "link": "https://dl.acm.org/doi/abs/10.1145/3400302.3415722",
    "doi": "10.1145/3400302.3415722",
    "cited_by": 4,
    "snippet": "The Reservoir Computing, a neural computing framework suited for temporal information processing, utilizes a dynamic reservoir layer for high-dimensional encoding, enhancing the …",
    "pdf_url": "https://dl.acm.org/doi/pdf/10.1145/3400302.3415722",
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "Molter-MSS-2016"
    ],
    "provenance": "cites-harvest",
    "abstract": "The Reservoir Computing, a neural computing framework suited for temporal information processing, utilizes a dynamic reservoir layer for high-dimensional encoding, enhancing the separability of the network. In this paper, we exploit a Deep Learning (DL)-based detection strategy for Multiple-input, Multiple-output Orthogonal Frequency-Division Multiplexing (MIMO-OFDM) symbol detection. To be specific, we introduce a Deep Echo State Network (DESN), a unique hierarchical processing structure with multiple time intervals, to enhance the memory capacity and accelerate the detection efficiency. The resulting hardware prototype with the hybrid memristor-CMOS co-design provides the in-memory computing and parallel processing capabilities, significantly reducing the hardware and power overhead. With the standard 180nm CMOS process and memristive synapses, the introduced DESN consumes merely 105mW of power consumption, exhibiting 16.7% power reduction compared to shallow ESN designs even with more dynamic layers and associated neurons. Furthermore, numerical evaluations demonstrate advantages of the DESN over state-of-the-art detection techniques in the literate for MIMO-OFDM systems even with a very limited training set, yielding a 47.8% improvement against conventional symbol detection techniques.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W3112413575",
    "pdf_knowm": "uses-model",
    "relevance": "cites",
    "knowm_role": "cites",
    "human_verdict": "cites-only",
    "human_reason": "CITE (PDF): reservoir-computing detector; GMS model only in references",
    "cites_reviewed": true
  },
  {
    "cluster_id": "11482368665396761237",
    "title": "Octave Memristor Models' Library and Application for Analysis of Memristors and Memristor-Based Circuits",
    "authors": [
      "S Kirilov"
    ],
    "first_author_last": "Kirilov",
    "year": 2025,
    "venue": "Proceedings of the Technical University of Sofia",
    "link": "https://e-university.tu-sofia.bg/ETUS/konferencii/files/169/paper_10.47978@TUS.2024.74.02.004.pdf",
    "doi": "10.47978/tus.2024.74.02.004",
    "cited_by": 0,
    "snippet": "Memristors are favorable electronic components with decent switching and memory features. Owing to their low energy usage, nano-scale sizes, and sound compatibility with …",
    "pdf_url": "https://e-university.tu-sofia.bg/ETUS/konferencii/files/169/paper_10.47978@TUS.2024.74.02.004.pdf",
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "Molter-MSS-2016",
      "Campbell-SDC-2016"
    ],
    "provenance": "cites-harvest",
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4407085059",
    "pdf_knowm": "uses-device",
    "relevance": "cites",
    "knowm_role": "cites",
    "human_verdict": "cites-only",
    "human_reason": "CITE (PDF): Octave model library; references the MSS/Campbell models in the bibliography",
    "cites_reviewed": true
  },
  {
    "cluster_id": "ltZ4o9lOmi4J",
    "title": "Memristive Crossbar for Hyper Dimensional Consumer Text Analytics Accelerator",
    "authors": [
      "PM Navaz",
      "R Chithra",
      "A James"
    ],
    "first_author_last": "Navaz",
    "year": 2023,
    "venue": "21st IEEE Interregional …",
    "link": "https://ieeexplore.ieee.org/abstract/document/10198153/",
    "doi": "10.1109/newcas57931.2023.10198153",
    "cited_by": 0,
    "snippet": "Hyper Dimensional (HD) Computing when employed for machine learning tasks such as learning and classification involve the computation and comparison of large hypervectors …",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "Molter-MSS-2016"
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    "abstract": "Hyper Dimensional (HD) Computing when employed for machine learning tasks such as learning and classification involve the computation and comparison of large hypervectors within memory. The dimensionality of hypervectors in the order of thousands makes it difficult to implement HD computing in von Neumann systems. The in-memory computing capability of the memristor crossbar will speed up the vectormatrix multiplication to perform HD computing. The paper presents a memristive accelerator design for hyper-dimensional consumer text analytics. The hyper-dimensional computing offers simple encoding and data transformation techniques with higher accuracy in comparison with conventional techniques. The circuit implementation of the KNN-based HD classification using Ngrams is proposed in the paper. The effect of device variations on the performance of the proposed system is evaluated and the performance is compared with conventional classifiers. The trade-off between accuracy and dimensionality in HD computing is presented.",
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    "abstract": "Wydawnictwo SIGMA-NOT wydaje czasopisma fachowe informujące swoich czytelników o najnowszych osiągnięciach naukowych i nowoczesnych rozwiązaniach technicznych w Polsce i na świecie, popularyzuje problemy techniczne oraz poszerza wiedzę i kulturę techniczną.",
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    "title": "Harnessing memristor circuits and device variability in emergent computing applications",
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    "abstract": "Τα σύγχρονα ηλεκτρονικά συστήματα επιδεικνύουν πρωτοφανείς δυνατότητες αποθήκευσης και επεξεργασίας πληροφοριών, χρησιμοποιώντας τη σύγχρονη τεχνολογία συμπληρωματικού μετάλλου-οξειδίου-ημιαγωγού (CMOS) σε νανοκλίμακα και την αρχιτεκτονική υπολογιστών γενικής χρήσης von Neumann. Παρ' όλα αυτά, με την αύξηση του όγκου της συλλογής πληροφοριών και την ανάγκη για την υπολογιστικά απαιτητική επεξεργασία τους, οι συμβατικές τεχνολογία και αρχιτεκτονική υπολογιστών δυσκολεύονται να συμβαδίσουν, καθώς συναντούν τους αντίστοιχους περιορισμούς τους είτε από φυσικής είτε από πρακτικής άποψης, δηλαδή τα όρια σμίκρυνσης, το αυξανόμενο κόστος, τη θερμότητα και την κατανάλωση ενέργειας. Τις τελευταίες δεκαετίες διερευνώνται εντατικά νέες προσεγγίσεις τόσο στην τεχνολογία όσο και στην αρχιτεκτονική υπολογιστών, με στόχο την ανάπτυξη καινοτόμων ηλεκτρονικών συστημάτων με προηγμένη ενεργειακή απόδοση, ταχύτητα λειτουργίας και μικρό εμβαδόν ολοκλήρωσης.Σε αυτή την κατεύθυνση, το memristor, ένα νέο ηλεκτρονικό στοιχείο με διαστάσεις στην κλίμακα του νανομέτρου, έρχεται ως ένας πολλά υποσχόμενος υποψήφιος για να διευρύνει τα όρια της τρέχουσας προηγμένης τεχνολογίας και των υπολογιστικών συστημάτων. Με την πρώτη τους υλοποίηση να χρονολογείται πριν από περίπου μια δεκαετία, οι διατάξεις memristor παρέχουν πρωτοφανή χαρακτηριστικά ως μία ηλεκτρονική διάταξη, όπως η μη πτητική αναλογική αποθήκευση πληροφοριών με γρήγορη και χαμηλής ισχύος λειτουργία. Αξιοποιώντας αυτό το χαρακτηριστικό, τα memristor χρησιμοποιούνται επί του παρόντος σε ανερχόμενες τεχνολογίες μνήμης, καθώς και αποτελούν την κορυφαία τεχνολογία για μελλοντικές υλοποιήσεις κυκλωμάτων τεχνητών νευρωνικών δικτύων και νευρομορφικών υπολογιστών. Ωστόσο, από τεχνολογική άποψη, οι διατάξεις memristor βρίσκονται σε πρώιμο στάδιο, καθώς αντιμετωπίζουν ακόμη σημαντικά ζητήματα που εμποδίζουν την ευρεία εμπορική τους αξιοποίηση. Πρώτον, η μοντελοποίηση των μηχανισμών αγωγής και της δυναμικής συμπεριφοράς τους βρίσκεται ακόμη υπό διερεύνηση και απέχουμε πολύ από ένα πρότυπο μοντέλο memristor που να αποτυπώνει με ακρίβεια τα χαρακτηριστικά των κατασκευασμένων διατάξεων memristor. Επιπλέον, τα υπάρχοντα μοντέλα memristor που επιτυγχάνουν ακριβή περιγραφή της δυναμικής της διάταξης αντιμετωπίζουν ζητήματα αριθμητικής σταθερότητας που επηρεάζουν τη σωστή αξιοποίησή τους σε προσομοιωτές κυκλωμάτων. Δεύτερον, λόγω της φύσης του memristor, η προσαύξηση της αγωγιμότητάς του προκύπτει από εγγενώς στοχαστικές διαδικασίες, π.χ. η μετακίνηση ιόντων, οι οποίες οδηγούν σε υψηλή μεταβλητότητα κατά τη λειτουργία της διάταξης, επηρεάζοντας επίσης τη λειτουργικότητά της μέσα σε ένα κύκλωμα.Με στόχο την αντιμετώπιση των προαναφερθέντων ζητημάτων στο πλαίσιο της παρούσας διδακτορικής διατριβής, η μοντελοποίηση της διάταξης memristor αντιμετωπίστηκε με μια διττή προσέγγιση. Αφενός, έχοντας ως βάση ένα υπάρχον μοντέλο memristor με βάση τη φυσική, πραγματοποιούνται οι απαραίτητοι μαθηματικοί μετασχηματισμοί για την εξαγωγή μιας αναλυτικής και υπερβατικής μορφής της δυναμικής συμπεριφοράς της διάταξης υπό σταθερή θετική και αρνητική διέγερση, αντίστοιχα, επιτρέποντας την αναλυτική μελέτη του προγραμματισμού του memristor. Πέρα από το ντετερμινιστικό μοντέλο, έχει αναπτυχθεί ένα πιθανοκρατικό μαθηματικό πλαίσιο για τη μοντελοποίηση του memristor με γνώμονα τη στοχαστικότητα, το οποίο βασίζεται στις κύριες εξισώσεις των διεργασιών άλματος Markov. Το προτεινόμενο πλαίσιο αποτυπώνει την πιθανοκρατική μεταγωγή των διατάξεων memristor που προέρχεται από την εγγενή στοχαστικότητα της διάταξης. Εκτός από τη δυαδική στοχαστική μεταγωγή, η προσέγγιση αυτή επιτρέπει για πρώτη φορά πολλαπλές πεπερασμένες καταστάσεις, παρέχοντας ευελιξία και περαιτέρω ακρίβεια στην πιθανοκρατική μοντελοποίηση των memristor.Από τη σκοπιά της σχεδίασης κυκλωμάτων, η στοχαστικότητα του memristor επιβάλλει επιζήμια μεταβλητότητα στον προγραμματισμό των διατάξεων memristor. Για την αντιμετώπιση αυτού του προβλήματος, υιοθέτησα μια αντισυμβατική προσέγγιση όπου ο θόρυβος προστίθεται στα σήματα προγραμματισμού για να ενισχυθεί η ικανότητα μεταγωγής του memristor. Μια τέτοια προσέγγιση βασίζεται στο φαινόμενο του μη γραμμικού συστήματος που ονομάζεται Στοχαστικός Συντονισμός (Stochastic Resonance - SR), το οποίο υποστηρίζει ότι ένα κατάλληλα επιλεγμένο θορυβώδες σήμα μπορεί να βελτιώσει την απόδοση ενός μη γραμμικού συστήματος. Αρχικά, ο SR χρησιμοποιήθηκε για την ενίσχυση του παραθύρου αντίστασης μιας διάταξης memristor. Στη συνέχεια, στην παρούσα διατριβή, το φαινόμενο αυτό μελετήθηκε για μια ευρύτερη ποικιλία μοντέλων memristor, συμπεριλαμβανομένης της μεταβλητότητας της διάταξης, το φαινόμενο αποδείχθηκε επίσης με πειραματικές μετρήσεις σε μεμονωμένες διατάξεις memristor. Πραγματοποιήθηκε λεπτομερής μελέτη για τον υποβοηθούμενο από θόρυβο προγραμματισμό ενός memristor σε κυψέλες μνήμης ReRAM, είτε μεμονωμένα είτε σε συστοιχία διασταυρωμένων αγωγών, αναδεικνύοντας την αποδοτικότητα της προτεινόμενης προσέγγισης υποβοηθούμενης από θόρυβο ως προς την καταναλισκόμενη ισχύ, καθώς τα ονομαστικά πλάτη τάσης προγραμματισμού μπορούν να μειωθούν παρουσία θορύβου χωρίς να βλάπτεται η ακρίβεια προγραμματισμού.Πέρα από την αντιμετώπιση της στοχαστικότητας του memristor ως επιζήμιο χαρακτηριστικό, η εκμετάλλευσή του στο πλαίσιο ενός νέου υπολογιστικού παραδείγματος διερευνήθηκε κατά τη διάρκεια αυτής της διατριβής. Λαμβάνοντας υπόψη μια δομή Αναδυόμενων Υπολογισμών, γνωστή ως Κυψελιδωτά Αυτόματα (Cellular Automata - CA), η διάταξη memristor ενσωματώνεται στη συστοιχία CA ως μέρος των απλοϊκών τοπικά αλληλεπιδρώντων υπολογιστικών μονάδων, που ονομάζονται κυψελίδες (CA cells), οι οποίες την αποτελούν. Ενώ αρχικά έχουν προταθεί ως ντετερμινιστικές δομές, οι ικανότητες των CA επεκτείνονται μετά την ενσωμάτωση της πιθανοκρατικής μεταγωγής του memristor στις κυψελίδες, καθιερώνοντας τη νέα δομή Πιθανοκρατικών Κυψελιδωτών Αυτομάτων με memristor (memristor-based Probabilistic CA - MemPCA). Έχοντας της απλούστερη μορφή CA, τα στοιχειώδη κυψελιδωτά αυτόματα (Elementary Cellular Automata - ECA), όπου κάθε κελί περιέχει μια δυαδική κατάσταση και το εύρος της αλληλεπίδρασης των κελιών περιορίζεται στο ελάχιστο δυνατό, δηλαδή στα δύο γειτονικά κελιά σε ένα μονοδιάστατο πλέγμα, μελετήθηκε η επίδραση της πιθανοκρατικής μεταγωγής των memristor για όλους τους κανόνες αλληλεπίδρασης των κυψελίδων, με αποτέλεσμα τη βελτίωση της εντροπίας του συστημάτος σε ορισμένο ποσό πιθανότητας μεταγωγής. Επιπλέον, πραγματοποιήθηκε η πρώτη εφαρμογή των ECA σε επίπεδο τρανζίστορ με την χρήση μίας προσέγγισης που βασίζεται ολοκληρωτικά σε memristor, που συμμετέχουν τόσο στο κύκλωμα των κυψελίδων όσο και σε εκείνο των κανόνων. Η προτεινόμενη νέα υλοποίηση MemPCA είναι σε θέση να επιτύχει υψηλή ταχύτητα λειτουργίας και χαμηλές απαιτήσεις σε επιφάνεια ολοκληρωσης, ενώ παράλληλα ενσωματώνει μια εξαιρετικά γρήγορη πηγή εντροπίας ανά κυψελίδα, δηλαδή τη διάταξη memristor. Η λειτουργικότητα του συστήματος επιδεικνύεται τόσο σε ντετερμινιστικές όσο και σε πιθανοκρατικές λειτουργίες, οι οποίες μπορούν να προσαρμόζονται από εξωτερικά επιλεγμένες παραμέτρους, χωρίς καμία τροποποίηση του κυκλώματος. Τέλος, η προτεινόμενη προσέγγιση MemPCA παρέχει επίσης αναδιαμορφώσιμη υλοποίηση της μονάδας κανόνων που επιτρέπει τόσο τη χωρική όσο και τη χρονική ανομοιογένεια των κανόνων.",
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    "year": 2025,
    "venue": "Journal of Circuits Systems and Computers",
    "link": "https://www.worldscientific.com/doi/abs/10.1142/S0218126625300107",
    "doi": "10.1142/S0218126625300107",
    "cited_by": 0,
    "snippet": "In this paper, the authors proposed a new power-efficient binary-to-ternary converter (BTC) circuit using a hybrid memristor-MOS-Logic architecture. The proposed BTC features three …",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "Molter-MSS-2016"
    ],
    "provenance": "cites-harvest",
    "abstract": "In this paper, the authors proposed a new power-efficient binary-to-ternary converter (BTC) circuit using a hybrid memristor-MOS-Logic architecture. The proposed BTC features three binary inputs and two ternary outputs, facilitating the effective execution of multi-valued logic operations. The proposed design uses the memristor-ratio-logic (MRL) technique, which is suitable for designing hybrid memristor-MOS-based circuits. The proposed design was simulated using SPICE and the 45 nm CMOS predictive technology model (PTM) technology parameters with [Formula: see text] supply. Moreover, the proposed BTC provides an improved PDP compared to the state-of-the-art design available in the literature. The authors also demonstrate that the proposed design is applied to MATLAB data processing and image reconstruction, laying the foundation for potential image processing applications. Simulation results confirm the design’s accuracy, low power consumption and robustness, making it a promising candidate for digital design and high-performance computing applications.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4412190023",
    "pdf_knowm": "uses-model",
    "relevance": "cites",
    "knowm_role": "cites",
    "human_verdict": "cites-only",
    "human_reason": "CITE (abstract): memristor-MOS ratio-logic converter (45nm CMOS); cites Molter, no Knowm use",
    "cites_reviewed": true
  },
  {
    "cluster_id": "hX70r8Eu3OsJ",
    "title": "Exploration of big data and machine learning in retail",
    "authors": [
      "J Edblom"
    ],
    "first_author_last": "Edblom",
    "year": 2017,
    "venue": "",
    "link": "https://www.diva-portal.org/smash/get/diva2:1139925/FULLTEXT01.pdf",
    "doi": null,
    "cited_by": 0,
    "snippet": "More and more business areas are today conforming to the big data domain, and the retail business has a lot to earn by giving the customer data more attention. However, most …",
    "pdf_url": "https://www.diva-portal.org/smash/get/diva2:1139925/FULLTEXT01.pdf",
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "Molter-MLTRAM-2016"
    ],
    "provenance": "cites-harvest",
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": null,
    "pdf_knowm": "uses-model",
    "relevance": "cites",
    "knowm_role": "cites",
    "human_verdict": "cites-only",
    "human_reason": "CITE (PDF): retail big-data/ML thesis; tangential Molter/Nugent citation",
    "cites_reviewed": true
  },
  {
    "cluster_id": "14147482503121785092",
    "title": "All-Printed Flexible Memristor with Metal–Non-Metal-Doped TiO2 Nanoparticle Thin Films",
    "authors": [
      "M Khan",
      "HM Mutee Ur Rehman",
      "R Tehreem",
      "M Saqib"
    ],
    "first_author_last": "Khan",
    "year": 2022,
    "venue": "Nanomaterials",
    "link": "https://www.mdpi.com/2079-4991/12/13/2289",
    "doi": "10.3390/nano12132289",
    "cited_by": 36,
    "snippet": "A memristor is a fundamental electronic device that operates like a biological synapse and is considered as the solution of classical von Neumann computers. Here, a fully printed and …",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [
      "Cr"
    ],
    "cites_seed": [
      "Nugent-TRAM-2017"
    ],
    "provenance": "cites-harvest",
    "abstract": "A memristor is a fundamental electronic device that operates like a biological synapse and is considered as the solution of classical von Neumann computers. Here, a fully printed and flexible memristor is fabricated by depositing a thin film of metal–non-metal (chromium-nitrogen)-doped titanium dioxide (TiO2). The resulting device exhibited enhanced performance with self-rectifying and forming free bipolar switching behavior. Doping was performed to bring stability in the performance of the memristor by controlling the defects and impurity levels. The forming free memristor exhibited characteristic behavior of bipolar resistive switching with a high on/off ratio (2.5 × 103), high endurance (500 cycles), long retention time (5 × 103 s) and low operating voltage (±1 V). Doping the thin film of TiO2 with metal–non-metal had a significant effect on the switching properties and conduction mechanism as it directly affected the energy bandgap by lowering it from 3.2 eV to 2.76 eV. Doping enhanced the mobility of charge carriers and eased the process of filament formation by suppressing its randomness between electrodes under the applied electric field. Furthermore, metal–non-metal-doped TiO2 thin film exhibited less switching current and improved non-linearity by controlling the surface defects.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://www.mdpi.com/2079-4991/12/13/2289/pdf?version=1656849307",
    "openalex_id": "https://openalex.org/W4283805564",
    "pdf_knowm": null,
    "relevance": "cites",
    "knowm_role": "cites",
    "cites_reviewed": true
  },
  {
    "cluster_id": "14699814932907203575",
    "title": "Memristive logic in crossbar memory arrays: Variability-aware design for higher reliability",
    "authors": [
      "M Escudero",
      "I Vourkas",
      "A Rubio"
    ],
    "first_author_last": "Escudero",
    "year": 2019,
    "venue": "IEEE Transactions on Nanotechnology",
    "link": "https://ieeexplore.ieee.org/abstract/document/8745694/",
    "doi": "10.1109/tnano.2019.2923731",
    "cited_by": 29,
    "snippet": "The advent of the first TiO 2-based memristor in 2008 revived the scientific interest both from academia and industry for this device technology and has so far led to several emerging …",
    "pdf_url": "https://upcommons.upc.edu/bitstreams/6b508869-62f3-462e-b6e3-801e6dc049b4/download",
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "Nugent-TRAM-2017"
    ],
    "provenance": "cites-harvest",
    "abstract": "The advent of the first TiO <sub xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sub> -based memristor in 2008 revived the scientific interest both from academia and industry for this device technology and has so far led to several emerging applications including logic and in-memory computing. Several memristive logic families have been proposed in the current quest for energy-efficient future computing systems. However, the limited device endurance and variability (both cycle-to-cycle and device-to-device) are important parameters to be considered in the assessment of logic operations. In this work, we used an accurate physics-based model of a bipolar memristor (supporting parasitics of the device structure and variability of switching voltages and resistance states) and demonstrate that performance of memristor-based in-memory computations can de degraded owing to both variability and state drift impact, if such features are not properly considered in the design flow. Inspired on pseudo-NMOS ratioed logic and based upon a previous CMOS-like logic scheme, we propose a crossbar-compatible memristive ratioed logic style which is tolerant to device variability and does not affect device endurance as computations do not involve conditional switching of memristors. Using the Cadence Virtuoso suite, we compare this logic scheme with MAGIC and CNIMP approaches, focusing on the universal NOR gate and more complex logic functions.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://hdl.handle.net/2117/168773",
    "openalex_id": "https://openalex.org/W2953470840",
    "pdf_knowm": "none",
    "relevance": "cites",
    "knowm_role": "cites",
    "cites_reviewed": true
  },
  {
    "cluster_id": "2443557200764875741",
    "title": "ReRAM-based ratioed combinational circuit design: a solution for in-memory computing",
    "authors": [
      "C Fernandez",
      "I Vourkas"
    ],
    "first_author_last": "Fernandez",
    "year": 2020,
    "venue": "9th International Conference on …",
    "link": "https://ieeexplore.ieee.org/abstract/document/9200279/",
    "doi": "10.1109/mocast49295.2020.9200279",
    "cited_by": 7,
    "snippet": "While the von Neumann architecture played a leading role in CMOS-based computing systems for several decades, nowadays in-memory computing is an alternative approach …",
    "pdf_url": "http://www.ids.uni-bremen.de/conf/mocast2020/papers/MOCAST_2020_paper_96.pdf",
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "Nugent-TRAM-2017"
    ],
    "provenance": "cites-harvest",
    "abstract": "While the von Neumann architecture played a leading role in CMOS-based computing systems for several decades, nowadays in-memory computing is an alternative approach being pursued, with resistive switching devices (memristors) in crossbar arrays considered as the enabling technology. In this context, this paper provides a practical solution for a viable in-memory computing architecture within the reach of today's technology, through a variability-tolerant ReRAM-based ratioed combinational logic design scheme, inspired on the pseudo-NMOS logic design. The reason we focus on this scheme is because it is simple, crossbar-compatible, completely tolerant to variability, compatible with either filamentary or interfacial switching type devices, and it does not affect the memristor endurance. We highlight all the important characteristics and advantages offered by this scheme, compared to other stateful logic schemes based on memristors, such as IMPLY and MAGIC. We conclude this paper presenting SPICEbased circuit simulation results concerning a 1-bit full adder implementation and show that our proposed ratioed logic design outperforms the rest in terms of speed and area requirements.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W3089261923",
    "pdf_knowm": "uses-model",
    "relevance": "cites",
    "knowm_role": "cites",
    "human_verdict": "cites-only",
    "human_reason": "CITE (abstract): ReRAM ratioed combinational logic; cites Nugent",
    "cites_reviewed": true
  },
  {
    "cluster_id": "3393924836189869343",
    "title": "Exploring the “resistance change per energy unit” as universal performance parameter for resistive switching devices",
    "authors": [
      "J Gomez",
      "I Vourkas",
      "A Abusleme",
      "R Rodriguez"
    ],
    "first_author_last": "Gomez",
    "year": 2019,
    "venue": "Solid-State Electronics",
    "link": "https://www.sciencedirect.com/science/article/pii/S0038110119302965",
    "doi": "10.1016/j.sse.2019.107748",
    "cited_by": 10,
    "snippet": "Resistive switching (RS) device (memristor) technology is continuously maturing towards industrial establishment. There are RS devices that demonstrate an “incremental”(analog) …",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "Nugent-TRAM-2017",
      "Campbell-SDC-2016"
    ],
    "provenance": "cites-harvest",
    "abstract": "Abstract Resistive switching (RS) device (memristor) technology is continuously maturing towards industrial establishment. There are RS devices that demonstrate an “incremental” (analog) switching behavior, whereas others change their state in a binary form. The final achieved resistance is generally a function of the applied pulse characteristics, i.e. amplitude and duration. However, variability —both from device to device but also from cycle to cycle— and the stochastic nature of internal RS phenomena, still hold back any universal tuning approach based solely on these two magnitudes, making also difficult the qualitative comparison between devices with different material compounds owing to the required SET/RESET voltages being dependent on the biasing conditions. In this work we demonstrate experimentally using commercial RS devices from Knowm Inc. that the switching energy is very insensitive to the biasing conditions. We explored experimentally the SET-RESET behavior of bipolar RS devices from the energy point of view. We figured out the quantitative effect of the injected energy to the resistive state of the devices, and proposed an analytical model to explain our observations in the energy consumed by the device during the switching process. Our results lay the foundations for the definition of “resistance change per energy unit” as a performance parameter for this emerging device technology.",
    "abstract_source": "semanticscholar",
    "oa_pdf_url": "http://hdl.handle.net/2117/179395",
    "openalex_id": "https://openalex.org/W2996118940",
    "pdf_knowm": "uses-device",
    "relevance": "core",
    "knowm_role": "named-in-abstract"
  },
  {
    "cluster_id": "9518844927968204195",
    "title": "Variability-tolerant memristor-based ratioed logic in crossbar array",
    "authors": [
      "M Escudero",
      "I Vourkas",
      "A Rubio",
      "F Moll"
    ],
    "first_author_last": "Escudero",
    "year": 2018,
    "venue": "Proceedings of the 14th IEEE …",
    "link": "https://dl.acm.org/doi/abs/10.1145/3232195.3232213",
    "doi": "10.1145/3232195.3232213",
    "cited_by": 8,
    "snippet": "The advent of the first TiO2-based memristor in 2008 revived the scientific interest both from academia and industry for this device technology, with several emerging applications …",
    "pdf_url": "https://dl.acm.org/doi/pdf/10.1145/3232195.3232213",
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "Nugent-TRAM-2017"
    ],
    "provenance": "cites-harvest",
    "abstract": "The advent of the first TiO2-based memristor in 2008 revived the scientific interest both from academia and industry for this device technology, with several emerging applications including that of logic circuits. Several memristive logic families have been proposed, each with different attributes, in the current quest for energy-efficient computing systems of the future. However, limited endurance of memristor devices and variations (both cycle-to-cycle and device-to-device) are important parameters to be considered in the evaluation of such logic families. In this work we build upon an accurate physics-based model of a bipolar metal-oxide resistive RAM device (supporting parasitics of the device structure and variability of switching voltages and resistance states) and use it to show how performance of memristor-based logic circuits can de degraded owing to both variability and state-drift impact. Based on previous work on CMOS-like memristive logic circuits, we propose a memristive ratioed logic scheme, which is crossbar-compatible, i.e. suitable for in-/near-memory computing, and tolerant to device variability, while also it does not affect the device endurance since computations do not involve switching the memristor states. As a figure of merit, we compare such new logic scheme with MAGIC, focusing on the universal NOR logic gate.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://hdl.handle.net/2117/130146",
    "openalex_id": "https://openalex.org/W2905754513",
    "pdf_knowm": "none",
    "relevance": "cites",
    "knowm_role": "cites",
    "human_verdict": "cites-only",
    "human_reason": "CITE (PDF): ratioed logic; Nugent TRAM cited in refs",
    "cites_reviewed": true
  },
  {
    "cluster_id": "17437089182521069384",
    "title": "Reliability-aware ratioed logic operations for energy-efficient computational ReRAM",
    "authors": [
      "C Fernandez",
      "I Vourkas"
    ],
    "first_author_last": "Fernandez",
    "year": 2022,
    "venue": "… on Very Large Scale Integration (VLSI …",
    "link": "https://ieeexplore.ieee.org/abstract/document/9939627/",
    "doi": "10.1109/vlsi-soc54400.2022.9939627",
    "cited_by": 5,
    "snippet": "Resistive RAM (ReRAM) technology is continuously maturing and it is attracting important investments towards more energy-efficient computing systems. Recent approaches to …",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "Nugent-TRAM-2017"
    ],
    "provenance": "cites-harvest",
    "abstract": "Resistive RAM (ReRAM) technology is continuously maturing and it is attracting important investments towards more energy-efficient computing systems. Recent approaches to ReRAM-based computing consider the inmemory computations equivalent to memory read operations. In this context, here we summarize a nonstateful ratioed logic style and guide the reader through the design of a computational 1T1R ReRAM module supporting reliable, variability-tolerant, and device technology-independent in-memory logic operations. We present circuit simulations of a 1-bit Full Adder to validate the robustness of the multi-level ratioed logic computations. Moreover, we underline the advantageous performance of nonstateful ratioed logic compared to stateful logic alternatives. Through a common ground basis used to simplify comparisons by translating computing steps/cycles into memory read/write operations, we found promising results in terms of delay and energy consumption compared to performance of stateful logic counterparts. Such results highlight the important benefits gained by basing all in-memory logic computations on memory read operations instead of conditional write operations.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4308659714",
    "pdf_knowm": "none",
    "relevance": "cites",
    "knowm_role": "cites",
    "human_verdict": "cites-only",
    "human_reason": "CITE (abstract): reliability-aware ReRAM ratioed logic; cites Nugent",
    "cites_reviewed": true
  },
  {
    "cluster_id": "17199440366881512574",
    "title": "Design and simulation of peripheral driving circuitry for computational ReRAM",
    "authors": [
      "C Fernandez",
      "I Vourkas",
      "A Rubio"
    ],
    "first_author_last": "Fernandez",
    "year": 2022,
    "venue": "37th Conference on …",
    "link": "https://ieeexplore.ieee.org/abstract/document/9970082/",
    "doi": "10.1109/dcis55711.2022.9970082",
    "cited_by": 5,
    "snippet": "As an alternative approach to the von Neumann architecture, the notion of computational resistive random-access memory (ReRAM) has emerged, promising faster and more energy …",
    "pdf_url": "https://upcommons.upc.edu/server/api/core/bitstreams/952ca0ea-648b-43de-a58e-a503c6e5aed0/content",
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "Nugent-TRAM-2017"
    ],
    "provenance": "cites-harvest",
    "abstract": "As an alternative approach to the von Neumann architecture, the notion of computational resistive random-access memory (ReRAM) has emerged, promising faster and more energy-efficient computing systems. In this context, we present a classification of ReRAM-compatible logic design strategies and highlight the potential of nonstateful ratioed logic for computational ReRAM modules. We provide insights towards the design of ad-hoc peripheral circuitry that allows the fusion of memory and ratioed logic operations in the ReRAM module in a reliable manner; i.e., the driving/sensing circuitry allows carrying out memory operations and in-memory multilevel ratioed logic operations. To this end, we present in detail a computational ReRAM driver and focus our description on the operational features that enable memory/logic operations in every row of the crossbar array. We validate circuit functionality through LTSpice simulations for read/write memory and logic operations using a threshold-type bipolar ReRAM device model. The presented practical solutions contribute to the viable development of computational ReRAM.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://upcommons.upc.edu/bitstreams/952ca0ea-648b-43de-a58e-a503c6e5aed0/download",
    "openalex_id": "https://openalex.org/W4311214623",
    "pdf_knowm": "none",
    "relevance": "cites",
    "knowm_role": "cites",
    "human_verdict": "cites-only",
    "human_reason": "CITE (PDF): ReRAM driver; Nugent TRAM cited in refs",
    "cites_reviewed": true
  },
  {
    "cluster_id": "4494375652056484344",
    "title": "A voltage-driven window function concept for behavioral memristor device modeling",
    "authors": [
      "C Fernandez",
      "J Ortiz",
      "I Vourkas"
    ],
    "first_author_last": "Fernandez",
    "year": 2020,
    "venue": "IEEE International …",
    "link": "https://ieeexplore.ieee.org/abstract/document/9180664/",
    "doi": null,
    "cited_by": 4,
    "snippet": "Development of memristor device models is a research topic of utmost interest. As the resistance switching mechanism is not always known in all details, several “behavioral” …",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "Nugent-TRAM-2017"
    ],
    "provenance": "cites-harvest",
    "abstract": "Development of memristor device models is a research topic of utmost interest. As the resistance switching mechanism is not always known in all details, several “behavioral” models employ window functions (WFs) to improve accuracy and to capture the switching-rate dependency on the bias conditions. The WFs published so far are functions of just the state variable(s), whose effectiveness was tested in fitting typical hysteretic i-v characteristics, ignoring the effect of the applied signal magnitude in dynamic behavior. In this context, we introduce a generalized concept of bias-dependent WFs, designed to enhance simple behavioral models by making possible capturing rich dynamic time-response of memristors. An implementation example is presented and its effect on the response of a threshold-based model of a voltage-controlled bipolar memristor is evaluated in simulations with LTSPICE.",
    "abstract_source": "ieee-xplore",
    "oa_pdf_url": null,
    "openalex_id": null,
    "pdf_knowm": "uses-model",
    "relevance": "cites",
    "knowm_role": "cites",
    "human_verdict": "cites-only",
    "human_reason": "CITE (abstract): behavioral window-function modeling; cites Nugent",
    "cites_reviewed": true
  },
  {
    "cluster_id": "8666222135853508571",
    "title": "Recent advances in halide perovskite memristors: From materials to applications",
    "authors": [
      "S Liu",
      "J Zeng",
      "Q Chen",
      "G Liu"
    ],
    "first_author_last": "Liu",
    "year": 2023,
    "venue": "Frontiers of Physics",
    "link": "https://link.springer.com/article/10.1007/s11467-023-1344-9",
    "doi": "10.1007/s11467-023-1344-9",
    "cited_by": 13,
    "snippet": "With the emergence of the Internet of Things (IoT) and the rapid growth of big data generated by edge devices, there has been a growing need for electronic devices that are …",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "Campbell-SDC-2016"
    ],
    "provenance": "cites-harvest",
    "abstract": "With the emergence of the Internet of Things (IoT) and the rapid growth of big data generated by edge devices, there has been a growing need for electronic devices that are capable of processing and transmitting data at low power and high speeds. Traditional Complementary Metal-Oxide-Semiconductor (CMOS) devices are nonvolatile and often limited by their ability for certain IoT applications due to their unnecessary power consumption for data movement in von Neuman architecture-based systems. This has led to a surge in research and development efforts aimed at creating innovative electronic components and systems that can overcome these shortcomings and meet the evolving needs of the information era, which share features such as improved energy efficiency, higher processing speeds, and increased functionality. Memristors are a novel type of electronic device that has the potential to break down the barrier between storage and computing. By storing data and processing information within the same device, memristors can minimize the need for data movement, which allows for faster processing speeds and reduced energy consumption. To further improve the energy efficiency and reliability of memristors, there has been a growing trend toward diversifying the selection of dielectric materials used in memristors. Halide perovskites (HPs) have unique electrical and optical properties, including ion migration, charge trapping effect caused by intrinsic defects, excellent optical absorption efficiency, and high charge mobility, which makes them highly promising in applications of memristors. In this paper, we provide a comprehensive overview of the recent development in resistive switching behaviors of HPs and the underlying mechanisms. Furthermore, we summarize the diverse range of HPs, their respective performance metrics, as well as their applications in various fields. Finally, we critically evaluate the current bottlenecks and possible opportunities in the future research of HP memristors.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4389568015",
    "pdf_knowm": null,
    "relevance": "cites",
    "knowm_role": "cites",
    "human_verdict": "cites-only",
    "human_reason": "CITE (abstract): halide-perovskite memristor review; cites Campbell only",
    "cites_reviewed": true
  },
  {
    "cluster_id": "9649758262273439870",
    "title": "Neuromorphic circuit of classical and operant conditioning based on tunable neural circuitry motifs",
    "authors": [
      "M Guo",
      "L Kong",
      "G Dou",
      "HHC Iu"
    ],
    "first_author_last": "Guo",
    "year": 2024,
    "venue": "IEEE Transactions on Circuits and Systems I Regular Papers",
    "link": "https://ieeexplore.ieee.org/abstract/document/10608449/",
    "doi": "10.1109/tcsi.2024.3431588",
    "cited_by": 20,
    "snippet": "Most memristive bionic circuits focus on how to realize bionic functions, few studies consider the biomimetic of the circuit structure and operation rules, so it is difficult to learn, memorize …",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "Campbell-SDC-2016"
    ],
    "provenance": "cites-harvest",
    "abstract": "Most memristive bionic circuits focus on how to realize bionic functions, few studies consider the biomimetic of the circuit structure and operation rules, so it is difficult to learn, memorize, and make decisions as biological neural networks. In this work, a multifunctional neuromorphic circuit inspired by tunable neural circuitry motifs is proposed. The circuit is more closely with biological characteristics in both structure and functions, which is designed based on neural circuit architectures. By connecting different neural circuitry motifs, the circuit realizes operant conditioning functions such as random exploration, behavioral frequency modulation, and decision-making. Also, the circuit integrated classical conditioning and operant conditioning in order to mimic the decision-making process, which was driven by the association of secondary and primary stimuli. In addition, the factors influencing decision-making are researched, such as the rates of learning and forgetting, and the conversion of short-term to long-term memory. The operational results of the proposed circuits in LTspice show that they can mimic the aforementioned functions, which have advantages in bionicity and scalability. This work can be applied in intelligent robotic platforms to achieve exploration and rescue in complex environments.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4400943733",
    "pdf_knowm": null,
    "relevance": "cites",
    "knowm_role": "cites",
    "human_verdict": "cites-only",
    "human_reason": "CITE (abstract): LTspice conditioning circuit; cites Campbell only",
    "cites_reviewed": true
  },
  {
    "cluster_id": "6719280003915282848",
    "title": "Voltage‐Driven Fluorine Motion for Novel Organic Spintronic Memristor",
    "authors": [
      "A Nachawaty",
      "T Chen",
      "F Ibrahim",
      "Y Wang"
    ],
    "first_author_last": "Nachawaty",
    "year": 2024,
    "venue": "Advanced Materials",
    "link": "https://advanced.onlinelibrary.wiley.com/doi/abs/10.1002/adma.202401611",
    "doi": "10.1002/adma.202401611",
    "cited_by": 13,
    "snippet": "Integrating tunneling magnetoresistance (TMR) effect in memristors is a long‐term aspiration because it allows to realize multifunctional devices, such as multi‐state memory and tunable …",
    "pdf_url": "https://lilloa.hal.science/hal-04614360/document",
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "Campbell-SDC-2016"
    ],
    "provenance": "cites-harvest",
    "abstract": "Abstract Integrating tunneling magnetoresistance (TMR) effect in memristors is a long‐term aspiration because it allows to realize multifunctional devices, such as multi‐state memory and tunable plasticity for synaptic function. However, the reported TMR in different multiferroic tunnel junctions is limited to 100%. This work demonstrates a giant TMR of −266% in La 0.6 Sr 0.4 MnO 3 (LSMO)/poly(vinylidene fluoride)(PVDF)/Co memristor with thin organic barrier. Different from the ferroelectricity‐based memristors, this work discovers that the voltage‐driven florine (F) motion in the junction generates a huge reversible resistivity change up to 10 6 % with nanosecond ( ns ) timescale. Removing F from PVDF layer suppresses the dipole field in the tunneling barrier, thereby significantly enhances the TMR. Furthermore, the TMR can be tuned by different polarizing voltage due to the strong modification of spin‐polarization at the LSMO/PVDF interface upon F doping. Combining of high TMR in the organic memristor paves the way to develop high‐performance multifunctional devices for storage and neuromorphic applications.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://onlinelibrary.wiley.com/doi/pdfdirect/10.1002/adma.202401611",
    "openalex_id": "https://openalex.org/W4399419226",
    "pdf_knowm": "uses-device",
    "relevance": "cites",
    "knowm_role": "cites",
    "human_verdict": "cites-only",
    "human_reason": "CITE (PDF): own organic spintronic memristor; cites Campbell only",
    "cites_reviewed": true
  },
  {
    "cluster_id": "11696821586402527087",
    "title": "High-temperature memristors enabled by interfacial engineering",
    "authors": [
      "J Zhao",
      "CS Jorgensen",
      "K Mahalingam",
      "C Bowers"
    ],
    "first_author_last": "Zhao",
    "year": 2026,
    "venue": "Science",
    "link": "https://www.science.org/doi/abs/10.1126/science.aeb9934",
    "doi": "10.1126/science.aeb9934",
    "cited_by": 1,
    "snippet": "",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [
      "W"
    ],
    "cites_seed": [
      "Campbell-SDC-2016"
    ],
    "provenance": "cites-harvest",
    "abstract": "Nonvolatile memories (NVMs) that operate reliably at high temperatures are essential for electronics in extreme environments. Here, we report graphene (Gra)/HfO x /tungsten (W) memristors that operated reliably up to 700°C, with an ON/OFF current ratio of &gt;10 3 , data retention &gt;50 hours, and endurance &gt;10 9 switching cycles. Transmission electron microscopy revealed substantial W diffusion into the inert platinum (Pt) electrode in conventional Pt/HfO x /W memristors after high-temperature annealing, which was responsible for the thermal failure in conventional devices but not observed in Gra/HfO x /W devices. First-principles calculations attributed the enhanced thermal stability to weaker W adsorption and higher surface diffusion barriers on Gra compared with metals such as Pt. These results underscore the critical role of interfacial engineering and the potential of two-dimensional materials for enabling reliable high-temperature NVM technologies.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W7140528177",
    "pdf_knowm": null,
    "relevance": "cites",
    "knowm_role": "cites",
    "human_verdict": "cites-only",
    "human_reason": "CITE (abstract): own Gra/HfOx/W high-temperature memristors; cites Campbell only",
    "cites_reviewed": true
  },
  {
    "cluster_id": "9633436583223657844",
    "title": "Unravelling the data retention mechanisms under thermal stress on 2D memristors",
    "authors": [
      "S Aldana",
      "H Zhang"
    ],
    "first_author_last": "Aldana",
    "year": 2023,
    "venue": "ACS Omega",
    "link": "https://pubs.acs.org/doi/abs/10.1021/acsomega.3c03200",
    "doi": "10.1021/acsomega.3c03200",
    "cited_by": 17,
    "snippet": "Memristors based on two-dimensional (2D) materials are a rapidly growing research area due to their potential in energy-efficient in-memory processing and neuromorphic …",
    "pdf_url": "https://pubs.acs.org/doi/pdf/10.1021/acsomega.3c03200",
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "Campbell-SDC-2016"
    ],
    "provenance": "cites-harvest",
    "abstract": "High Resolution Image Download MS PowerPoint Slide Memristors based on two-dimensional (2D) materials are a rapidly growing research area due to their potential in energy-efficient in-memory processing and neuromorphic computing. However, the data retention of these emerging memristors remains sparsely investigated, despite its crucial importance to device performance and reliability. In this study, we employ kinetic Monte–Carlo simulations to investigate the data retention of a 2D planar memristor. The operation of the memristor depends on field-driven on defect migration, while thermal diffusion gradually evens the defect distribution, leading to the degradation of the high resistance state (HRS) and diminishing the ON/OFF ratio. Notably, we examine the resilience of devices based on single crystals of transition metal dichalcogenides (TMDs) in harsh environments. Specifically, our simulations show that MoS 2 -based devices have negligible degradation after 10 years of thermal annealing at 400 K. Furthermore, the variability in data retention lifetime across different temperatures is less than 22%, indicating a relatively consistent performance over a range of thermal conditions. We also demonstrate that device miniaturization does not compromise data retention lifetime. Moreover, employing materials with higher activation energy for defect migration can significantly enhance data retention at the cost of increased switching voltage. These findings shed light on the behavior of 2D memristors and pave the way for their optimization in practical applications.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://pubs.acs.org/doi/pdf/10.1021/acsomega.3c03200",
    "openalex_id": "https://openalex.org/W4384933627",
    "pdf_knowm": "uses-device",
    "relevance": "cites",
    "knowm_role": "cites",
    "human_verdict": "cites-only",
    "human_reason": "CITE (PDF): 2D-material memristors; cites Campbell only",
    "cites_reviewed": true
  },
  {
    "cluster_id": "15101401252211413248",
    "title": "Implementing bionic associate memory based on spiking signal",
    "authors": [
      "M Guo",
      "K Zhao",
      "J Sun",
      "S Wen",
      "G Dou"
    ],
    "first_author_last": "Guo",
    "year": 2023,
    "venue": "Information Sciences",
    "link": "https://www.sciencedirect.com/science/article/pii/S0020025523011982",
    "doi": "10.1016/j.ins.2023.119613",
    "cited_by": 19,
    "snippet": "Most of the associate memory circuits are at the simulation stage. If these designs are to be realized in hardware, they pose substantial requirements in terms of experimental …",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "Campbell-SDC-2016"
    ],
    "provenance": "cites-harvest",
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4386319526",
    "pdf_knowm": null,
    "relevance": "cites",
    "knowm_role": "cites",
    "human_verdict": "cites-only",
    "human_reason": "CITE (abstract): spiking associate-memory circuit; cites Campbell only",
    "cites_reviewed": true
  },
  {
    "cluster_id": "2309241473252880661",
    "title": "Magnetic-field controlled organic spintronic memristor for neural network computation",
    "authors": [
      "T Chen",
      "Y Nie",
      "Y Hao",
      "S Shen",
      "J Pan"
    ],
    "first_author_last": "Chen",
    "year": 2025,
    "venue": "ACS Applied Materials & Interfaces",
    "link": "https://pubs.acs.org/doi/abs/10.1021/acsami.5c14275",
    "doi": "10.1021/acsami.5c14275",
    "cited_by": 2,
    "snippet": "Memristors are emerging as key electronic components that retain resistance states without power. Their nonvolatile nature and ability to mimic synaptic behavior make them ideal for …",
    "pdf_url": "https://arxiv.org/pdf/2510.23542",
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "Campbell-SDC-2016"
    ],
    "provenance": "cites-harvest",
    "abstract": "Memristors are emerging as key electronic components that retain resistance states without power. Their nonvolatile nature and ability to mimic synaptic behavior make them ideal for next-generation memory technologies and neuromorphic computing systems inspired by the human brain. In this study, we present a novel organic spintronic memristor based on a La 0.67 Sr 0.33 MnO 3 (LSMO)/poly(vinylidene fluoride) (PVDF)/Co heterostructure exhibiting biologically inspired synaptic behavior. Driven by fluorine atom migration within the PVDF layer, the device demonstrates both long-term depression and long-term potentiation under controlled electrical polarization. Distinctively, the resistance states can also be modulated by an external magnetic field via the tunneling magnetoresistance effect, introducing a nonelectrical means of tuning synaptic plasticity. This magnetic control mechanism enables multistate modulation without compromising device performance or endurance. Furthermore, convolutional neural network simulations incorporating this magnetic tuning capability reveal enhanced pattern recognition accuracy and improved training stability, especially at high learning rates. These findings underscore the potential of organic spintronic memristors as high-performance, low-power neuromorphic elements, particularly suited for applications in flexible and wearable electronics.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://arxiv.org/pdf/2510.23542",
    "openalex_id": "https://openalex.org/W4415470967",
    "pdf_knowm": "uses-device",
    "relevance": "cites",
    "knowm_role": "cites",
    "human_verdict": "cites-only",
    "human_reason": "CITE (PDF): own organic spintronic memristor; cites Campbell only",
    "cites_reviewed": true
  },
  {
    "cluster_id": "8927275908037123944",
    "title": "A mixed-kernel, variable-dimension memristive CNN for electronic nose recognition",
    "authors": [
      "J Chen",
      "L Wang",
      "S Duan"
    ],
    "first_author_last": "Chen",
    "year": 2021,
    "venue": "Neurocomputing",
    "link": "https://www.sciencedirect.com/science/article/pii/S0925231221010432",
    "doi": "10.1016/j.neucom.2021.07.009",
    "cited_by": 36,
    "snippet": "Due to the dynamic characteristics, memristors have great potential for implementing various neural network training and applications. By applying memristors to neural networks as a …",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "Campbell-SDC-2016"
    ],
    "provenance": "cites-harvest",
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W3182269511",
    "pdf_knowm": null,
    "relevance": "cites",
    "knowm_role": "cites",
    "human_verdict": "cites-only",
    "human_reason": "CITE (abstract): memristive CNN for e-nose; cites Campbell only",
    "cites_reviewed": true
  },
  {
    "cluster_id": "8962375786770936770",
    "title": "A fully configurable PUF using dynamic variations of resistive crossbar arrays",
    "authors": [
      "J Li",
      "Y Cui",
      "C Wang",
      "C Gu",
      "W Liu"
    ],
    "first_author_last": "Li",
    "year": 2022,
    "venue": "IEEE Transactions on Nanotechnology",
    "link": "https://ieeexplore.ieee.org/abstract/document/9946437/",
    "doi": "10.1109/tnano.2022.3221372",
    "cited_by": 14,
    "snippet": "A resistive random access memory (RRAM) as an emerging nanoelectronic device, is widely used for memory and physical unclonable function (PUF) applications. The compatibility of …",
    "pdf_url": "https://pure.qub.ac.uk/files/388215602/Dynamic_PUF_23Nov2022.pdf",
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "Campbell-SDC-2016"
    ],
    "provenance": "cites-harvest",
    "abstract": "A resistive random access memory (RRAM) as an emerging nanoelectronic device, is widely used for memory and physical unclonable function (PUF) applications. The compatibility of RRAM PUFs with memory architectures can be exploited to reduce the hardware overhead. Therefore, an intrinsic PUF using dynamic variations of resistive crossbar arrays is presented in this paper. Based on an improved sense amplifier (SA), the proposed intrinsic RRAM PUF can be fully configured as a memory cell or a PUF cell, leading to a minimal design overhead. Using the device-to-device (D2D) variation of an RRAM, a significant number of challenge-response pairs (CRPs) is generated with a flexible configuration of the resistive crossbar arrays. The proposed RRAM PUF can be refreshed to a new instance relying on the cycle-to-cycle (C2C) variation of an RRAM. An efficient challenge generation method is presented to improve the security of the proposed RRAM PUF. To verify the performance of the proposed RRAM PUF, 20 instances are simulated and implemented using a compact Spice model and a UMC 65 nm CMOS process technology, respectively. The simulation results show that the proposed RRAM PUF exhibits good performances with a high uniqueness, reliability, and reconfigurability. The randomness of the PUF is evaluated by the National Institute of Standards and Technology (NIST) and autocorrelation function (ACF) tests. Moreover, the experimental results show that the proposed RRAM PUF achieves a good resistance against machine learning (ML) attacks.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://pureadmin.qub.ac.uk/ws/files/388215602/Dynamic_PUF_23Nov2022.pdf",
    "openalex_id": "https://openalex.org/W4312264836",
    "pdf_knowm": "uses-device",
    "relevance": "core",
    "knowm_role": "uses-knowm-device",
    "human_verdict": "uses-knowm-device",
    "human_reason": "YES (PDF): PUF built on the Knowm SDC stack (Ge2Se3/Ag/SnSe/W) with measured switching; uses Molter LTSpice models"
  },
  {
    "cluster_id": "9998715413925748464",
    "title": "Uncontrolled learning: Codesign of neuromorphic hardware topology for neuromorphic algorithms",
    "authors": [
      "F Barrows",
      "J Lin",
      "F Caravelli"
    ],
    "first_author_last": "Barrows",
    "year": 2025,
    "venue": "Advanced Intelligent Systems",
    "link": "https://advanced.onlinelibrary.wiley.com/doi/abs/10.1002/aisy.202400739",
    "doi": "10.1002/aisy.202400739",
    "cited_by": 5,
    "snippet": "Neuromorphic computing has the potential to revolutionize future technologies and our understanding of intelligence, yet it remains challenging to realize in practice. The learning …",
    "pdf_url": "https://advanced.onlinelibrary.wiley.com/doi/pdf/10.1002/aisy.202400739",
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "Campbell-SDC-2016"
    ],
    "provenance": "cites-harvest",
    "abstract": "Neuromorphic computing has the potential to revolutionize future technologies and our understanding of intelligence, yet it remains challenging to realize in practice. The learning‐from‐mistakes algorithm, inspired by the brain's simple learning rules of inhibition and pruning, is one of the few brain‐like training methods. This algorithm is implemented in neuromorphic memristive hardware through a codesign process that evaluates essential hardware trade‐offs. While the algorithm effectively trains small networks as binary classifiers and perceptrons, performance declines significantly with increasing network size unless the hardware is tailored to the algorithm. This work investigates the trade‐offs between depth, controllability, and capacity—the number of learnable patterns—in neuromorphic hardware. This highlights the importance of topology and governing equations, providing theoretical tools to evaluate a device's computational capacity based on its measurements and circuit structure. The findings show that breaking neural network symmetry enhances both controllability and capacity. Additionally, by pruning the circuit, neuromorphic algorithms in all‐memristive circuits can utilize stochastic resources to create local contrasts in network weights. Through combined experimental and simulation efforts, the parameters are identified that enable networks to exhibit emergent intelligence from simple rules, advancing the potential of neuromorphic computing.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://onlinelibrary.wiley.com/doi/pdfdirect/10.1002/aisy.202400739",
    "openalex_id": "https://openalex.org/W4408475514",
    "pdf_knowm": "cites",
    "relevance": "core",
    "knowm_role": "uses-knowm-device",
    "human_verdict": "uses-knowm-device",
    "human_reason": "YES (PDF): experimentally implements memristive networks using Knowm tungsten-doped 16-pin packages (8 devices/chip)"
  },
  {
    "cluster_id": "3310238375800337900",
    "title": "PySpice-Simulated In Situ Learning with Memristor Emulation for Single-Layer Spiking Neural Networks",
    "authors": [
      "SL Jurj"
    ],
    "first_author_last": "Jurj",
    "year": 2024,
    "venue": "Electronics",
    "link": "https://www.mdpi.com/2079-9292/13/23/4665",
    "doi": "10.3390/electronics13234665",
    "cited_by": 2,
    "snippet": "This paper presents a novel approach to in situ memristive learning by training spiking neural networks (SNNs) entirely within the circuit using memristor emulators in SPICE. The …",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "Campbell-SDC-2016"
    ],
    "provenance": "cites-harvest",
    "abstract": "This paper presents a novel approach to in situ memristive learning by training spiking neural networks (SNNs) entirely within the circuit using memristor emulators in SPICE. The circuit models neurons using Lapicque neurons and employs pulse-based spike encoding to simulate spike-timing-dependent plasticity (STDP), a key learning mechanism in SNNs. The Lapicque neuron model operates according to the Leaky Integrate-and-Fire (LIF) model, which is used in this study to model spiking behavior in memristor-based SNNs. More exactly, the first memristor emulator in PySpice, a Python library for circuit simulation, was developed and integrated into a memristive circuit capable of in situ learning, named the “In Situ Memristive Learning Method for Pattern Classification”. This novel technique enables time-based computation, where neurons accumulate incoming spikes and fire once a threshold is reached, mimicking biological neuron behavior. The proposed method was rigorously tested on three diverse datasets: XPUE, a custom non-dominating 3 × 3 image dataset; a 3 × 5 digit dataset ranging from 0 to 5; and a resized 10 × 10 version of the Modified National Institute of Standards and Technology (MNIST) dataset. The neuromorphic circuit achieved successful pattern learning across all three datasets, outperforming comparable results from other in situ training simulations on SPICE. The learning process harnesses the cumulative effect of memristors, enabling the network to learn a representative pattern for each label efficiently. This advancement opens new avenues for neuromorphic computing and paves the way for developing autonomous, adaptable pattern classification neuromorphic circuits.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://www.mdpi.com/2079-9292/13/23/4665/pdf?version=1732629283",
    "openalex_id": "https://openalex.org/W4404711432",
    "pdf_knowm": "uses-device",
    "relevance": "cites",
    "knowm_role": "cites",
    "human_verdict": "cites-only",
    "human_reason": "CITE (PDF): PySpice memristor-emulation SNN; single SDC/Campbell reference, no Knowm device/model use",
    "cites_reviewed": true
  },
  {
    "cluster_id": "10065943944678540929",
    "title": "Pulse shape and timing dependence on the spike-timing dependent plasticity response of ion-conducting memristors as synapses",
    "authors": [
      "KA Campbell",
      "KT Drake"
    ],
    "first_author_last": "Campbell",
    "year": 2016,
    "venue": "Frontiers in Bioengineering and Biotechnology",
    "link": "https://www.frontiersin.org/journals/bioengineering-and-biotechnology/articles/10.3389/fbioe.2016.00097/full",
    "doi": "10.3389/fbioe.2016.00097/full",
    "cited_by": 35,
    "snippet": "Ion-conducting memristors comprised of the layered materials Ge2Se3/SnSe/Ag are promising candidates for neuromorphic computing applications. Here, the spike-timing …",
    "pdf_url": "https://www.frontiersin.org/journals/bioengineering-and-biotechnology/articles/10.3389/fbioe.2016.00097/pdf",
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": true,
    "devices": [],
    "cites_seed": [
      "Campbell-SDC-2016"
    ],
    "provenance": "cites-harvest",
    "abstract": "Ion-conducting memristors comprised of the layered materials Ge2Se3/SnSe/Ag are promising candidates for neuromorphic computing applications. Here, the spike-timing dependent plasticity (STDP) application is demonstrated for the first time with a single memristor type operating as a synapse over a timescale of 10 orders of magnitude, from nanoseconds through seconds. This large dynamic range allows the memristors to be useful in applications that require slow biological times, as well as fast times such as needed in neuromorphic computing, thus allowing multiple functions in one design for one memristor type – a “one size fits all” approach. This work also investigated the effects of varying the spike pulse shapes on the STDP response of the memristors. These results showed that small changes in the pre and postsynaptic pulse shape can have a significant impact on the STDP. These results may provide circuit designers with insights into how pulse shape affects the actual memristor STDP response and aid them in the design of neuromorphic circuits and systems that can take advantage of certain features in the memristor STDP response that are programmable via the pre and postsynaptic pulse shapes. In addition, the energy requirement per memristor is approximated based on the pulse shape and timing responses. The energy requirement estimated per memristor operating on slower biological timescales (ms to s) is larger (nJ range), as expected, than the faster (ns) operating times (~0.1 pJ in some cases). Lastly, the memristors responded in a similar manner under normal STDP conditions (pre- and post-spikes applied to opposite memristor terminals) as they did to the case where a waveform corresponding to the difference between pre- and post-spikes was applied to only one electrode, with the other electrode held at ground potential. By applying the difference signal to only one terminal, testing of the memristor in various applications can be achieved with a simplified test set up, and thus be easier to accomplish in most laboratories.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://www.frontiersin.org/articles/10.3389/fbioe.2016.00097/pdf",
    "openalex_id": "https://openalex.org/W2562620981",
    "pdf_knowm": "uses-device",
    "relevance": "core",
    "knowm_role": "named-in-abstract"
  },
  {
    "cluster_id": "938326119931863286",
    "title": "Information transfer in neuronal circuits: From biological neurons to neuromorphic electronics",
    "authors": [
      "D Gandolfi",
      "L Benatti",
      "T Zanotti",
      "GM Boiani"
    ],
    "first_author_last": "Gandolfi",
    "year": 2024,
    "venue": "Intelligent Computing",
    "link": "https://spj.science.org/doi/abs/10.34133/icomputing.0059",
    "doi": "10.34133/icomputing.0059",
    "cited_by": 6,
    "snippet": "The advent of neuromorphic electronics is increasingly revolutionizing the concept of computation. In the last decade, several studies have shown how materials, architectures …",
    "pdf_url": "https://spj.science.org/doi/pdf/10.34133/icomputing.0059",
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "Campbell-SDC-2016"
    ],
    "provenance": "cites-harvest",
    "abstract": "The advent of neuromorphic electronics is increasingly revolutionizing the concept of computation. In the last decade, several studies have shown how materials, architectures, and neuromorphic devices can be leveraged to achieve brain-like computation with limited power consumption and high energy efficiency. Neuromorphic systems have been mainly conceived to support spiking neural networks that embed bioinspired plasticity rules such as spike time-dependent plasticity to potentially support both unsupervised and supervised learning. Despite substantial progress in the field, the information transfer capabilities of biological circuits have not yet been achieved. More importantly, demonstrations of the actual performance of neuromorphic systems in this context have never been presented. In this paper, we report similarities between biological, simulated, and artificially reconstructed microcircuits in terms of information transfer from a computational perspective. Specifically, we extensively analyzed the mutual information transfer at the synapse between mossy fibers and granule cells by measuring the relationship between pre- and post-synaptic variability. We extended this analysis to memristor synapses that embed rate-based learning rules, thus providing quantitative validation for neuromorphic hardware and demonstrating the reliability of brain-inspired applications.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://doi.org/10.34133/icomputing.0059",
    "openalex_id": "https://openalex.org/W4391494179",
    "pdf_knowm": "uses-device",
    "relevance": "core",
    "knowm_role": "uses-knowm-device",
    "human_verdict": "uses-knowm-device",
    "human_reason": "YES (PDF): presents the Knowm SDC device (full W/Ge2Se3/Ag/Ge2Se3/SnSe/Ge2Se3:C/W stack) and its plasticity as the neuromorphic substrate"
  },
  {
    "cluster_id": "10543936469641884528",
    "title": "Ultra-low power logic in memory with commercial grade memristors and FPGA-based smart-IMPLY architecture",
    "authors": [
      "L Benatti",
      "T Zanotti",
      "P Pavan",
      "FM Puglisi"
    ],
    "first_author_last": "Benatti",
    "year": 2023,
    "venue": "SSRN Electronic Journal",
    "link": "https://www.sciencedirect.com/science/article/pii/S0167931723001272",
    "doi": "10.2139/ssrn.4455816",
    "cited_by": 1,
    "snippet": "Reducing power consumption in nowadays computer technologies represents an increasingly difficult challenge. Conventional computing architectures suffer from the so …",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "Campbell-SDC-2016"
    ],
    "provenance": "cites-harvest",
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": "http://dx.doi.org/10.2139/ssrn.4455816",
    "openalex_id": "https://openalex.org/W4377236017",
    "pdf_knowm": "uses-device",
    "relevance": "core",
    "knowm_role": "uses-knowm-device",
    "human_verdict": "uses-knowm-device",
    "human_reason": "YES (PDF): logic-in-memory on commercial Knowm SDC devices (Self-Directed Channel, Ge2Se3)"
  },
  {
    "cluster_id": "15336252618075583297",
    "title": "A bio-inspired neuromorphic system for fusing visual features and autonomous learning",
    "authors": [
      "M Guo",
      "Y Zi",
      "L Liu",
      "J Liu",
      "Q Yang",
      "J Xu",
      "G Dou",
      "L Wang"
    ],
    "first_author_last": "Guo",
    "year": 2026,
    "venue": "Neural Networks",
    "link": "https://www.sciencedirect.com/science/article/pii/S0893608026005575",
    "doi": "10.1016/j.neunet.2026.109097",
    "cited_by": 0,
    "snippet": "AbstractThis work presents a brain-inspired neural network model for multi-modal image classification based on dual-feature fusion. Inspired by the parallel processing of color and …",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "Campbell-SDC-2016"
    ],
    "provenance": "cites-harvest",
    "abstract": "This work presents a brain-inspired neural network model for multi-modal image classification based on dual-feature fusion. Inspired by the parallel processing of color and shape in the brain's ventral visual pathway, our model comprises three core components: 1) a feature fusion module that integrates and matches visual features from different modalities; 2) a learning memory module that employs memristor-based synaptic plasticity to learn and consolidate correct feature associations; and 3) a classification module that enables rapid inference through long-term memory. The memristor-enabled circuit dynamically generates feature weights, allowing the system to discriminate between features based on pulse width or voltage amplitude. After learning, the system bypasses the fusion module for direct classification, which is a dynamic pathway switch that enhances both speed and circuit efficiency. Experimental results validate the circuit's scalability through multi-image classification of Teenage Mutant Ninja Turtles characters and its extension to real-time person recognition in inspection robots, demonstrating its potential for high-speed, low-power AI systems.",
    "abstract_source": "semanticscholar",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W7160827471",
    "pdf_knowm": null,
    "relevance": "cites",
    "knowm_role": "cites",
    "human_verdict": "cites-only",
    "human_reason": "CITE (abstract): bio-inspired neuromorphic visual-fusion circuit; generic memristor, cites Campbell only",
    "cites_reviewed": true
  },
  {
    "cluster_id": "12493933426035541684",
    "title": "Biologically plausible information propagation in a complementary metal-oxide semiconductor integrate-and-fire artificial neuron circuit with memristive synapses",
    "authors": [
      "L Benatti",
      "T Zanotti",
      "D Gandolfi",
      "J Mapelli"
    ],
    "first_author_last": "Benatti",
    "year": 2023,
    "venue": "Nano Futures",
    "link": "https://iopscience.iop.org/article/10.1088/2399-1984/accf53/meta",
    "doi": "10.1088/2399-1984/accf53/meta",
    "cited_by": 8,
    "snippet": "Neuromorphic circuits based on spikes are currently envisioned as a viable option to achieve brain-like computation capabilities in specific electronic implementations while …",
    "pdf_url": "https://iopscience.iop.org/article/10.1088/2399-1984/accf53/pdf",
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "Campbell-SDC-2016"
    ],
    "provenance": "cites-harvest",
    "abstract": "Abstract Neuromorphic circuits based on spikes are currently envisioned as a viable option to achieve brain-like computation capabilities in specific electronic implementations while limiting power dissipation given their ability to mimic energy-efficient bioinspired mechanisms. While several network architectures have been developed to embed in hardware the bioinspired learning rules found in the biological brain, such as spike timing-dependent plasticity, it is still unclear if hardware spiking neural network architectures can handle and transfer information akin to biological networks. In this work, we investigate the analogies between an artificial neuron combining memristor synapses and rate-based learning rule with biological neuron response in terms of information propagation from a theoretical perspective. Bioinspired experiments have been reproduced by linking the biological probability of release with the artificial synapse conductance. Mutual information and surprise have been chosen as metrics to evidence how, for different values of synaptic weights, an artificial neuron allows to develop a reliable and biological resembling neural network in terms of information propagation and analysis.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://iopscience.iop.org/article/10.1088/2399-1984/accf53/pdf",
    "openalex_id": "https://openalex.org/W4366605893",
    "pdf_knowm": "uses-device",
    "relevance": "core",
    "knowm_role": "uses-knowm-device",
    "human_verdict": "uses-knowm-device",
    "human_reason": "YES (PDF): uses commercial C-doped SDC memristors by Knowm (dual in-line package), measured I-V"
  },
  {
    "cluster_id": "6423684596088130693",
    "title": "Main-line memristor mounted type loaded-line phase shifter realization",
    "authors": [
      "IL Marković",
      "MM Potrebić",
      "DV Tošić"
    ],
    "first_author_last": "Marković",
    "year": 2017,
    "venue": "Microelectronic Engineering",
    "link": "https://www.sciencedirect.com/science/article/pii/S0167931717303696",
    "doi": "10.1016/j.mee.2017.11.005",
    "cited_by": 14,
    "snippet": "In this paper, we present a possible application of memristive switches for implementation of main-line mounted loaded-line phase shifters. The underlining idea is to replace PIN diodes …",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "Campbell-SDC-2016"
    ],
    "provenance": "cites-harvest",
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W2767630104",
    "pdf_knowm": null,
    "relevance": "cites",
    "knowm_role": "cites",
    "human_verdict": "cites-only",
    "human_reason": "CITE (abstract): RF phase shifter; Pi/Biolek models, cites Campbell, no Knowm use",
    "cites_reviewed": true
  },
  {
    "cluster_id": "10425384617321572472",
    "title": "A comprehensive simulation framework to validate progressive read-monitored write schemes for ReRAM",
    "authors": [
      "J Cayo",
      "I Vourkas"
    ],
    "first_author_last": "Cayo",
    "year": 2023,
    "venue": "14th Spanish Conference on Electron …",
    "link": "https://ieeexplore.ieee.org/abstract/document/10339485/",
    "doi": "10.1109/cde58627.2023.10339485",
    "cited_by": 8,
    "snippet": "This work introduces a simulation framework for behavioral models of resistive switching devices. Along with variability, the presented approach incorporates dynamic bias …",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "Campbell-SDC-2016"
    ],
    "provenance": "cites-harvest",
    "abstract": "This work introduces a simulation framework for behavioral models of resistive switching devices. Along with variability, the presented approach incorporates dynamic bias-dependent switching behavior, transition faults (soft errors) attributed to the fading memory property, as well as stuck-at faults (hard errors) due to overstressing of RS devices. All these attributes are developed as model add-ons in a compact and SPICE-compatible form for comprehensive circuit simulations towards the validation of read-monitored progressive WRITE schemes for practical resistive memory (ReRAM) applications.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4389577560",
    "pdf_knowm": "uses-device",
    "relevance": "cites",
    "knowm_role": "cites",
    "human_verdict": "cites-only",
    "human_reason": "CITE (abstract): behavioral RS simulation framework; cites Campbell only",
    "cites_reviewed": true
  },
  {
    "cluster_id": "7408395386003899915",
    "title": "Multisensory Memristive Circuits With Parallel Processing and Dual Adaptive Features",
    "authors": [
      "M Guo",
      "X Zhang",
      "W Guo",
      "G Dou",
      "D Chen"
    ],
    "first_author_last": "Guo",
    "year": 2025,
    "venue": "IEEE Transactions on Circuits and Systems I Regular Papers",
    "link": "https://ieeexplore.ieee.org/abstract/document/11301822/",
    "doi": "10.1109/tcsi.2025.3632287",
    "cited_by": 4,
    "snippet": "As the brain-like intelligence develops rapidly, it is urgent to design a more convenient and efficient control framework to cope with the challenge of processing multisensory signals in …",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "Campbell-SDC-2016"
    ],
    "provenance": "cites-harvest",
    "abstract": "As the brain-like intelligence develops rapidly, it is urgent to design a more convenient and efficient control framework to cope with the challenge of processing multisensory signals in parallel. Therefore, a multisensory memristive circuit with dual adaptive, parallel processing, and multilevel reinforcement features is proposed. The circuit is mainly composed of modules for receptors, STM and LTM, attention, environmental monitoring and mutual associative memory. Automatic encoding of different sensorial signals is realised by the receptor modules. Dual adaptive regulation of the internal associative memory and external environmental changes on the circuit is implemented by modules of attention and environmental monitoring. Multilevel reinforcement memory is achieved through the interconnection of multiple dimensional features of the same objects. The process of encoding transformation of stimuli, experience memory, and feedback learning is automatically achieved in the brain-inspired neural network structure, which avoids the problems such as encoding difficulties during the conversion of the operating objects, and enables the realization of more brain-like intelligence. The circuit is applied to gripping and recognizing in robotic arms and the scenario memory of different production lines is simulated, which is promising for application in automated factories.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4417438486",
    "pdf_knowm": null,
    "relevance": "cites",
    "knowm_role": "cites",
    "human_verdict": "cites-only",
    "human_reason": "CITE (abstract): LTspice brain-like multisensory circuit; cites Campbell only",
    "cites_reviewed": true
  },
  {
    "cluster_id": "17871469071520932063",
    "title": "System interfaces for accurate READing from memristive devices in multi-level ReRAM and neuromorphic computing applications",
    "authors": [
      "I Vourkas"
    ],
    "first_author_last": "Vourkas",
    "year": 2025,
    "venue": "Parallel Processing Letters",
    "link": "https://www.worldscientific.com/doi/abs/10.1142/S0129626425500112",
    "doi": "10.1142/S0129626425500112",
    "cited_by": 2,
    "snippet": "This paper discusses the practical aspects of developing system interfaces for the reliable sensing of the analog resistive state of memristive devices, implementing multi-level …",
    "pdf_url": "https://www.worldscientific.com/doi/pdf/10.1142/S0129626425500112",
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "Campbell-SDC-2016"
    ],
    "provenance": "cites-harvest",
    "abstract": "This paper discusses the practical aspects of developing system interfaces for the reliable sensing of the analog resistive state of memristive devices, implementing multi-level resistive memory (ReRAM) cells or synaptic weights in neuromorphic computing applications. More specifically, it presents a general implementation method for ad-hoc sensing systems designed for memristive devices, with a particular focus on the design of the READ circuit module. Through detailed comparison and analysis of experimental results, this study proposes a versatile circuit that utilizes a current-to-voltage converting stage with a transimpedance amplifier (TIA), along with a suggested algorithm for iterative operation which will improve resolution, when needed, at the cost of longer READ processes. The proposed algorithm automatically adjusts the circuit parameters to maintain the output voltage of the TIA within an acceptable range, ensuring high-precision READings. This approach avoids saturation of the TIA while also preventing the low-level signals, which could compromise the precision of the READ process. Simulation results using LTSpice validate the operation and usefulness of the proposed circuit, enhancing the tutorial value of this work for both the practical implementation of research prototypes and more advanced applications of memristive devices developed by students, researchers, and engineers working in emerging device technologies.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://doi.org/10.1142/s0129626425500112",
    "openalex_id": "https://openalex.org/W4413308047",
    "pdf_knowm": "uses-device",
    "relevance": "core",
    "knowm_role": "uses-knowm-device",
    "human_verdict": "uses-knowm-device",
    "human_reason": "YES (PDF): READ/WRITE drivers experimentally tested with self-directed channel (SDC) memristive devices developed by Knowm Inc."
  },
  {
    "cluster_id": "1913285761075025110",
    "title": "Memristor dynamics involved in cells communication for a 2D non‐linear network",
    "authors": [
      "A Isah",
      "AST Nguetcho",
      "S Binczak"
    ],
    "first_author_last": "Isah",
    "year": 2020,
    "venue": "IET Signal Processing",
    "link": "https://ietresearch.onlinelibrary.wiley.com/doi/abs/10.1049/iet-spr.2020.0136",
    "doi": "10.1049/iet-spr.2020.0136",
    "cited_by": 11,
    "snippet": "In this study, the authors consider a first step to apply memristor devices in a cellular non‐linear network (CNN), where the advantages of the non‐linearity, nanoscalability and …",
    "pdf_url": "https://ietresearch.onlinelibrary.wiley.com/doi/pdf/10.1049/iet-spr.2020.0136",
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "Campbell-SDC-2016"
    ],
    "provenance": "cites-harvest",
    "abstract": "In this study, the authors consider a first step to apply memristor devices in a cellular non‐linear network (CNN), where the advantages of the non‐linearity, nanoscalability and memory effect could be taken into account to implement a 2D‐CNN for signal and image processing – Memristors are used in the coupling mode to connect adjacent cells serially. They drive the analytical model describing the transmission of information from one cell to another via memristor, whose description in the – q plane is given, then improved to overcome the problem of discontinuities for some values of the charge . The modified model is then chosen to be continued for all initial conditions and all parameters sets. Moreover, numerical simulations from SPICE and MATLAB software confirm the authors’ analytical predictions.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://onlinelibrary.wiley.com/doi/pdfdirect/10.1049/iet-spr.2020.0136",
    "openalex_id": "https://openalex.org/W3022290185",
    "pdf_knowm": "uses-device",
    "relevance": "cites",
    "knowm_role": "cites",
    "human_verdict": "cites-only",
    "human_reason": "CITE (PDF): own model; SDC/Campbell cited as an example device technology",
    "cites_reviewed": true
  },
  {
    "cluster_id": "7DRSoQ0iC1sJ",
    "title": "Energy-Efficient Epileptic Seizure Prediction Using RRAM-Based In-Memory Computing",
    "authors": [
      "A Khan",
      "SM Varnosfaderani",
      "M Alhawari"
    ],
    "first_author_last": "Khan",
    "year": 2026,
    "venue": "IEEE Journal on Emerging and Selected Topics in Circuits and Systems",
    "link": "https://ieeexplore.ieee.org/abstract/document/11415615/",
    "doi": "10.1109/jetcas.2026.3668819",
    "cited_by": 0,
    "snippet": "This work investigates the feasibility of an energy-efficient resistive random-access memory (RRAM) crossbar array framework for epileptic seizure prediction using the CHB-MIT …",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "Campbell-SDC-2016"
    ],
    "provenance": "cites-harvest",
    "abstract": "This work investigates the feasibility of an energy-efficient resistive random-access memory (RRAM) crossbar array framework for epileptic seizure prediction using the CHB-MIT electroencephalogram (EEG) dataset. Traditional von Neumann architectures face limitations in scalability and energy efficiency for real-time medical applications, motivating the exploration of in-memory computing with RRAM devices. We develop a domain-specific feature extraction methodology tailored to EEG signals and implement a seizure prediction algorithm that can be mapped directly onto a crossbar-based architecture. To evaluate the robustness of the approach, the extracted features were quantized to a 1-bit representation and processed as inputs. Despite the aggressive quantization, the proposed workflow achieved mean prediction accuracies exceeding 75% for hardware inference, demonstrating resilience to reduced precision. Furthermore, the system exhibits extremely low read energy consumption at the picojoule level, enabling performance metrics far surpassing conventional digital platforms. The combination of high accuracy, ultra-low power requirements, and hardware-friendly implementation highlights the promise of RRAM-based in-memory computing as a scalable solution for real-time, patient-specific epilepsy monitoring and intervention in wearable and implantable devices.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W7131888971",
    "pdf_knowm": null,
    "relevance": "cites",
    "knowm_role": "cites",
    "human_verdict": "cites-only",
    "human_reason": "CITE (abstract): generic RRAM crossbar seizure prediction (CHB-MIT EEG); cites Campbell only",
    "cites_reviewed": true
  },
  {
    "cluster_id": "15261582541109476546",
    "title": "Varistructure resistive switching memory devices through dynamical redox of oxides",
    "authors": [
      "HN Li",
      "L Wang",
      "J Zhu",
      "YX He",
      "XQ Liu",
      "YQ Wang"
    ],
    "first_author_last": "Li",
    "year": 2026,
    "venue": "Applied Physics Letters",
    "link": "https://pubs.aip.org/aip/apl/article/128/1/012106/3376996",
    "doi": "10.1063/5.0281237",
    "cited_by": 0,
    "snippet": "Hafnium oxide-based resistive switching (RS) devices are promising candidates for next-generation nonvolatile memories because of their ability to integrate into silicon electronics …",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "Campbell-SDC-2016"
    ],
    "provenance": "cites-harvest",
    "abstract": "Hafnium oxide-based resistive switching (RS) devices are promising candidates for next-generation nonvolatile memories because of their ability to integrate into silicon electronics. However, irreversible and unidirectional movements of oxygen vacancies in functional oxide in memristors limit the improvement of ON/OFF ratio and endurance simultaneously as well as the highest working temperature up to 300 °C. Here, we design varistructure RS devices through oxygen vacancy engineering and dynamical redox of Ta. The ON/OFF ratio and the endurance are largely co-improved due to dynamical redox of Ta at the interfaces. Compared to all current RS memories, it cumulatively demonstrates high endurance (105), retention (104 s), ON/OFF ratio (104–106), operation speed (75 ns), and low write voltage (2 V). Remarkably, the RS devices remain stable up to 300 °C.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W7119504875",
    "pdf_knowm": null,
    "relevance": "cites",
    "knowm_role": "cites",
    "human_verdict": "cites-only",
    "human_reason": "CITE (abstract): own HfOx varistructure RS devices; cites Campbell only",
    "cites_reviewed": true
  },
  {
    "cluster_id": "1396556426029515925",
    "title": "Analyzing analog, digital, asymmetric, and butterfly-like hysteresis characteristics using generalized memristor model",
    "authors": [
      "AKR Poreddy",
      "T Dixit",
      "RB",
      "P Kokil"
    ],
    "first_author_last": "Poreddy",
    "year": 2026,
    "venue": "Semiconductor Science and Technology",
    "link": "https://iopscience.iop.org/article/10.1088/1361-6641/ae5ccb/meta",
    "doi": "10.1088/1361-6641/ae5ccb/meta",
    "cited_by": 0,
    "snippet": "The memristor, garnering considerable attention due to its potential applications in various fields, including neuromorphic computing, analog and digital circuits, memory devices, and …",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "Campbell-SDC-2016"
    ],
    "provenance": "cites-harvest",
    "abstract": "Abstract The memristor, garnering considerable attention due to its potential applications in various fields, including neuromorphic computing, analog and digital circuits, memory devices, and chaotic circuits, is exceptionally promising for the development of next-generation circuits. Numerous hysteresis phenomena, each exhibiting diverse properties, are widely documented within the realm of memristors. It is widely assumed that memristors can be categorized into different types based on the presence of three distinct key signatures, commonly referred to as the three fingerprints of memristors. The memristor shows promise as a building block for synaptic devices that require analog behavior, memory devices that necessitate digital-type hysteresis, and applications that necessitate butterfly-like hysteresis. The currently available models of memristors need to be more adequate in elucidating every facet of their current–voltage behavior. A novel set of window functions is methodically developed in this work, emphasizing the customization of the analog, digital, asymmetrical and butterfly-like features. The experimentally observed characteristics and behavior is explainable by these models using a variety of control parameters, including voltage range, frequency, ramp-rate, and amplitude variation. These generalized models will play a crucial role in advancing memristor-based circuitry and the continued expansion of the field.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W7152057345",
    "pdf_knowm": null,
    "relevance": "cites",
    "knowm_role": "cites",
    "human_verdict": "cites-only",
    "human_reason": "CITE (abstract): generalized memristor window-function modeling; cites Campbell only",
    "cites_reviewed": true
  },
  {
    "cluster_id": "11859798395641069967",
    "title": "Benchmarking RRAM crossbar arrays for epileptic seizure prediction",
    "authors": [
      "A Khan",
      "SM Varnosfaderani",
      "M Alhawari"
    ],
    "first_author_last": "Khan",
    "year": 2024,
    "venue": "IEEE 67th …",
    "link": "https://ieeexplore.ieee.org/abstract/document/10658668/",
    "doi": "10.1109/mwscas60917.2024.10658668",
    "cited_by": 1,
    "snippet": "This paper explores an energy-efficient resistive random access memory (RRAM) crossbar array framework for predicting epileptic seizures using the CUB-MIT electroen-cephalogram …",
    "pdf_url": "https://par.nsf.gov/servlets/purl/10614804",
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "Campbell-SDC-2016"
    ],
    "provenance": "cites-harvest",
    "abstract": "This paper explores an energy-efficient resistive random access memory (RRAM) crossbar array framework for predicting epileptic seizures using the CUB-MIT electroen-cephalogram (EEG) dataset. RRAMs have significant potential for in-memory computing, offering a promising solution to over-come the limitations of the traditional Von Neumann architecture. By integrating a domain-specific feature extraction approach and evaluating the optimal RRAM hardware parameters using the NeuroSim+ benchmarking platform, we assess the performance of RRAM crossbars for predicting epileptic seizures. Our proposed workflow achieves accuracy levels above 80% despite the EEG data being quantized to 1-bit, highlighting the robustness and efficiency of our approach for epileptic seizure prediction.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4402716143",
    "pdf_knowm": "uses-device",
    "relevance": "excluded",
    "knowm_role": null,
    "human_verdict": "not-knowm",
    "human_reason": "NO (user): generic RRAM/NeuroSim+ seizure-prediction work, cites Campbell only"
  },
  {
    "cluster_id": "16595526942228198683",
    "title": "Polarity reversal effect of a memristor from the circuit point of view and insights into the memristor fuse",
    "authors": [
      "A Isah",
      "AS Tchakoutio Nguetcho",
      "S Binczak"
    ],
    "first_author_last": "Isah",
    "year": 2021,
    "venue": "Frontiers in Communications and Networks",
    "link": "https://www.frontiersin.org/journals/communications-and-networks/articles/10.3389/frcmn.2021.647528/full",
    "doi": "10.3389/frcmn.2021.647528/full",
    "cited_by": 6,
    "snippet": "As the memristor device is asymmetrical in nature, it is not a bilateral element like the resistor in terms of circuit functionality. Thus, it causes hindrance in some memristor-based …",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "Campbell-SDC-2016"
    ],
    "provenance": "cites-harvest",
    "abstract": "As the memristor device is asymmetrical in nature, it is not a bilateral element like the resistor in terms of circuit functionality. Thus, it causes hindrance in some memristor-based applications such as in cellular nonlinear network neighborhood connections and in some application areas where its orientation is essentially expected to act as a bilateral circuit element reliable for bidirectional communication, for example, in signal and image processing or in electrical synapse devices. We introduce a memristor-based network for each purpose where we replace the conventional series resistances by memristors. The memristor asymmetry is described from the circuit point of view allowing us to observe its interaction within the network. Moreover, a memristor fuse is proposed in order to achieve the memristive effect with symmetry, which is formed basically by connecting two memristors antiserially. We, therefore, analyze the memristor fuse from its basic principle along with the theoretical analysis and then observe the response from the circuit point of view.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://www.frontiersin.org/articles/10.3389/frcmn.2021.647528/pdf",
    "openalex_id": "https://openalex.org/W3182216536",
    "pdf_knowm": "uses-device",
    "relevance": "cites",
    "knowm_role": "cites",
    "human_verdict": "cites-only",
    "human_reason": "CITE (PDF): SDC/Campbell cited as example device technology, no Knowm device/model use",
    "cites_reviewed": true
  },
  {
    "cluster_id": "6820012299366532689",
    "title": "Reliable leakage-enabled memristor model for large-scale circuits",
    "authors": [
      "MM Rabiee",
      "M Gholipour",
      "N TaheriNejad"
    ],
    "first_author_last": "Rabiee",
    "year": 2025,
    "venue": "Journal of Computational Electronics",
    "link": "https://link.springer.com/article/10.1007/s10825-025-02377-4",
    "doi": "10.1007/s10825-025-02377-4",
    "cited_by": 0,
    "snippet": "Memristors offer great potential for advanced memory and computing systems due to their ability to retain their resistance state. Several simulation models have been proposed to …",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "Campbell-SDC-2016"
    ],
    "provenance": "cites-harvest",
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4411748290",
    "pdf_knowm": null,
    "relevance": "cites",
    "knowm_role": "cites",
    "human_verdict": "cites-only",
    "human_reason": "CITE (abstract): leakage-enabled memristor model verified against the BELIEVER model; cites Campbell, no direct Knowm device use",
    "cites_reviewed": true
  },
  {
    "cluster_id": "10010611814336502819",
    "title": "An RRAM-based PUF with adjustable programmable voltage and multi-mode operation",
    "authors": [
      "Y Cui",
      "J Li",
      "C Gu",
      "C Wang",
      "W Liu"
    ],
    "first_author_last": "Cui",
    "year": 2023,
    "venue": "Proceedings of the 18th ACM …",
    "link": "https://dl.acm.org/doi/abs/10.1145/3611315.3633258",
    "doi": "10.1145/3611315.3633258",
    "cited_by": 1,
    "snippet": "The resistive random access memory (RRAM) is one of the promising technology based solutions for energy-efficient reconfigurable logic in memory (LiM) designs. In this paper, a …",
    "pdf_url": "https://dl.acm.org/doi/pdf/10.1145/3611315.3633258",
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "Campbell-SDC-2016"
    ],
    "provenance": "cites-harvest",
    "abstract": "The resistive random access memory (RRAM) is one of the promising technology based solutions for energy-efficient reconfigurable logic in memory (LiM) designs. In this paper, a Multi-Mode Configurable Physical Unclonable Function (MC-PUF) is proposed for secure RRAM-based LiM applications. The proposed MC-PUF can be configured to different working modes by adjusting the programming voltages of the corresponding RRAM. When the proposed MC-PUF is configured in a weak write mode, it exploits the inherent variations of an RRAM by adjusting the programming voltages to a switching probability of 50%. When the proposed MC-PUF is programmed in a normal reset voltage and configured in a parallel competition mode, it generates a response by selecting two parallel RRAMs. With the same number of RRAMs, the proposed MC-PUF generates more challenge-response pairs (CRPs) compared to conventional designs. The implementation of the MC-PUF on an RRAM crossbar array is presented. The results from both the experiment and simulation demonstrate that the proposed MC-PUF has good uniqueness, high reliability as well as excellent configurability.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://dl.acm.org/doi/pdf/10.1145/3611315.3633258",
    "openalex_id": "https://openalex.org/W4391236128",
    "pdf_knowm": "uses-device",
    "relevance": "core",
    "knowm_role": "uses-knowm-device",
    "human_verdict": "uses-knowm-device",
    "human_reason": "YES (PDF): RRAM PUF on Knowm self-directed channel device + metastable-switch model"
  },
  {
    "cluster_id": "7398790212883162201",
    "title": "How to 'Tame' a memristor: advanced control unit for reliable ReRAM operation leveraging prognostics and health management approaches",
    "authors": [
      "I Vourkas"
    ],
    "first_author_last": "Vourkas",
    "year": 2026,
    "venue": "International Journal of Parallel Emergent and Distributed Systems",
    "link": "https://www.tandfonline.com/doi/abs/10.1080/17445760.2026.2636490",
    "doi": "10.1080/17445760.2026.2636490",
    "cited_by": 0,
    "snippet": "This work explores the practical exploitation of ReRAM technology, addressing erratic switching cell performance by leveraging comprehensive memory access methods aligned …",
    "pdf_url": "https://www.tandfonline.com/doi/pdf/10.1080/17445760.2026.2636490",
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "Campbell-SDC-2016"
    ],
    "provenance": "cites-harvest",
    "abstract": "This work explores the practical exploitation of ReRAM technology, addressing erratic switching cell performance by leveraging comprehensive memory access methods aligned with prognostics and health management (PHM) principles. The paper highlights the operational characteristics of memristive devices while rigorously reviewing their non-ideal aspects through experimental measurements. A novel resistance-to-data mapping strategy is introduced to formulate PHM-enhanced REA D/WRITE methods, improving ReRAM cell reliability and endurance. The practical development of a ReRAM control unit (ReMCU) is presented with design alternatives that aim to significantly advance the practical exploitation of ReRAM technology across emerging applications, from nonvolatile memory chips to neuromorphic/edge computing.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://www.tandfonline.com/doi/pdf/10.1080/17445760.2026.2636490?needAccess=true",
    "openalex_id": "https://openalex.org/W7134074506",
    "pdf_knowm": "uses-device",
    "relevance": "core",
    "knowm_role": "uses-knowm-device",
    "human_verdict": "uses-knowm-device",
    "human_reason": "YES (PDF): experimental results on SDC bipolar devices from Knowm Inc. in 2x2 passive crossbar arrays (measured HRS/LRS resistance)"
  },
  {
    "cluster_id": "11921825530003360308",
    "title": "Brain‐Like Biomimetic Circuit Design Based on Memristor",
    "authors": [
      "L Liu"
    ],
    "first_author_last": "Liu",
    "year": 2024,
    "venue": "International Journal of Circuit Theory and Applications",
    "link": "https://onlinelibrary.wiley.com/doi/abs/10.1002/cta.4399",
    "doi": "10.1002/cta.4399",
    "cited_by": 1,
    "snippet": "In this work, inspired by the neural mechanisms of the human brain, a brain‐like biomimetic circuit based on visual information processing is proposed. The circuit is mainly composed …",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "Campbell-SDC-2016"
    ],
    "provenance": "cites-harvest",
    "abstract": "ABSTRACT In this work, inspired by the neural mechanisms of the human brain, a brain‐like biomimetic circuit based on visual information processing is proposed. The circuit is mainly composed of test module, cognitive module, categorization module, and output module. The cognitive module mimics the function of memory neurons in the brain, generating memory potentials to store information while receiving visual information stimuli. The categorization module mimics the function of the visual cortex, enabling the conversion from memory to action. I verified the feasibility of this circuit for information processing using LTspice. This study provides new ideas and insights for the future development of visual information processing technology for electronic products.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://onlinelibrary.wiley.com/doi/pdfdirect/10.1002/cta.4399",
    "openalex_id": "https://openalex.org/W4405385500",
    "pdf_knowm": null,
    "relevance": "cites",
    "knowm_role": "cites",
    "human_verdict": "cites-only",
    "human_reason": "CITE (abstract): LTspice brain-like biomimetic circuit; generic memristor, cites Campbell only",
    "cites_reviewed": true
  },
  {
    "cluster_id": "15448300241308744138",
    "title": "Modeling memristor radiation interaction events and the effect on neuromorphic learning circuits",
    "authors": [
      "SG Dahl",
      "R Ivans",
      "KD Cantley"
    ],
    "first_author_last": "Dahl",
    "year": 2018,
    "venue": "Proceedings of the International …",
    "link": "https://dl.acm.org/doi/abs/10.1145/3229884.3229885",
    "doi": "10.1145/3229884.3229885",
    "cited_by": 10,
    "snippet": "An ideal memristor model is modified to include the effects of radiation interactions with the device. Modeling is done in Cadence Virtuoso design suite using Verilog-A. Simulations …",
    "pdf_url": "https://dl.acm.org/doi/pdf/10.1145/3229884.3229885",
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "Campbell-SDC-2016"
    ],
    "provenance": "cites-harvest",
    "abstract": "An ideal memristor model is modified to include the effects of radiation interactions with the device. Modeling is done in Cadence Virtuoso design suite using Verilog-A. Simulations include the effect of radiation events that could change the state of device or can ionize the device to create e-h+ pairs or change the off-state resistance of the device. Combination of these events occurring simultaneously is also studied. Simulation results are compared with the experimental results published in existing research papers. Finally, transient simulation of a three-input, two-output spiking electronic neural network with memristive synapses is performed. Varying amounts of energy deposited by radiation are modeled, and it is observed that radiation exposure dramatically alters the synaptic weight evolution.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W2883186904",
    "pdf_knowm": "uses-device",
    "relevance": "cites",
    "knowm_role": "cites",
    "human_verdict": "cites-only",
    "human_reason": "CITE (PDF): Boise State radiation study; cites Campbell, no Knowm device/model use",
    "cites_reviewed": true
  },
  {
    "cluster_id": "3597426250336318545",
    "title": "Memristive Wilson–Cowan Neuron Models: Innovative Conceptual Framework and Programmable Analog and Digital Implementations",
    "authors": [
      "AY Baran",
      "JL Randrianantenaina"
    ],
    "first_author_last": "Baran",
    "year": 2025,
    "venue": "International Journal of Circuit Theory and Applications",
    "link": "https://onlinelibrary.wiley.com/doi/abs/10.1002/cta.70219",
    "doi": "10.1002/cta.70219",
    "cited_by": 1,
    "snippet": "Since general purposes of memristors are not yet widely available as standard, off‐the‐shelf components, finding a reliable hardware equivalent is essential for accurately implementing …",
    "pdf_url": "https://www.researchgate.net/profile/Jean-Randrianantenaina/publication/397557625_Memristive_Wilson-Cowan_Neuron_Models_Innovative_Conceptual_Framework_and_Programmable_Analog_and_Digital_Implementations/links/6915bd84cbd367756c1181a3/Memristive-Wilson-Cowan-Neuron-Models-Innovative-Conceptual-Framework-and-Programmable-Analog-and-Digital-Implementations.pdf",
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "Campbell-SDC-2016"
    ],
    "provenance": "cites-harvest",
    "abstract": "ABSTRACT Since general purposes of memristors are not yet widely available as standard, off‐the‐shelf components, finding a reliable hardware equivalent is essential for accurately implementing a memristive neural system. With this motivation, we improve the piecewise‐linear, piecewise quadratic, and cubic monotone‐increasing functions‐based memristive Wilson–Cowan (W‐C) neuron models in this paper. After determining the control parameters of these three memristive W‐C neuron models, we calculate their equilibrium points and Lyapunov exponents and then, we also illustrate the influence of the control parameters through bifurcation diagrams. Thus, the W‐C neuron model is re‐defined as including the essential characteristics of the memristors. Following the theoretical analysis of the memristive neuron models, we develop an alternative framework for spike‐timing‐dependent plasticity (STDP)‐based network structures. Finally, the hardware confirmations of these models are built separately by using field programmable gate array (FPGA) and field programmable analog array (FPAA).",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4416158406",
    "pdf_knowm": null,
    "relevance": "cites",
    "knowm_role": "cites",
    "human_verdict": "cites-only",
    "human_reason": "CITE (abstract): Wilson-Cowan neuron models on FPGA/FPAA; generic, cites Campbell only",
    "cites_reviewed": true
  },
  {
    "cluster_id": "4325249324800091774",
    "title": "Design Steps towards a MCU-based Instrumentation System for Memristor-based Crossbar Arrays",
    "authors": [
      "J Cayo",
      "I Vourkas"
    ],
    "first_author_last": "Cayo",
    "year": 2021,
    "venue": "10th International Conference on …",
    "link": "https://ieeexplore.ieee.org/abstract/document/9493362/",
    "doi": "10.1109/mocast52088.2021.9493362",
    "cited_by": 7,
    "snippet": "The memristor technology has a great potential for nonvolatile memory, circuit reconfigurability, and edge computing paradigms. Several such applications rely on the use …",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "Campbell-SDC-2016"
    ],
    "provenance": "cites-harvest",
    "abstract": "The memristor technology has a great potential for nonvolatile memory, circuit reconfigurability, and edge computing paradigms. Several such applications rely on the use of dense passive crossbar arrays, which are now becoming commercially available and accessible to researchers. However, experimental measurements on crossbar arrays not only require special caution but also special driving techniques, both for reading and writing of data, while addressing the current sneak-paths problem. This makes highly relevant the development of instrumentation solutions that provide a safe and proper way to experimental work with passive memristive crossbars. In this direction, we present our early design steps towards the development of an instrumentation printed circuit board (PCB) which addresses the characterization and testing of memristive crossbar chips. The PCB will be interfaced through a STM32 microcontroller system and has a PCI socket compatible with crossbar chips sold by Knowm Inc. We present the driving circuitry in detail and LTspice circuit simulation results that verify/quantify the performance of reading/writing processes.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W3184456821",
    "pdf_knowm": null,
    "relevance": "core",
    "knowm_role": "named-in-abstract"
  },
  {
    "cluster_id": "1222767223599730318",
    "title": "Design and Simulation of a Hyperdimensional Computing System with Memristive Associative Memory for Image Classification.",
    "authors": [
      "K Pizarro",
      "I Vourkas"
    ],
    "first_author_last": "Pizarro",
    "year": 2024,
    "venue": "International Journal of Unconventional …",
    "link": "https://www.researchgate.net/profile/Ioannis-Vourkas/publication/388647334_Design_and_Simulation_of_a_Hyperdimensional_Computing_System_with_Memristive_Associative_Memory_for_Image_Classification/links/67a0ec99645ef274a4623f6b/Design-and-Simulation-of-a-Hyperdimensional-Computing-System-with-Memristive-Associative-Memory-for-Image-Classification.pdf",
    "doi": null,
    "cited_by": 1,
    "snippet": "Data-intensive application tasks have always fueled research and development towards more powerful computing systems. In this context, the recently proposed framework of hyper …",
    "pdf_url": "https://www.researchgate.net/profile/Ioannis-Vourkas/publication/388647334_Design_and_Simulation_of_a_Hyperdimensional_Computing_System_with_Memristive_Associative_Memory_for_Image_Classification/links/67a0ec99645ef274a4623f6b/Design-and-Simulation-of-a-Hyperdimensional-Computing-System-with-Memristive-Associative-Memory-for-Image-Classification.pdf",
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "Campbell-SDC-2016"
    ],
    "provenance": "cites-harvest",
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": null,
    "pdf_knowm": "uses-device",
    "relevance": "cites",
    "knowm_role": "cites",
    "human_verdict": "cites-only",
    "human_reason": "CITE (PDF): HDC associative-memory simulation; Knowm/Campbell appear only in the bibliography, no device/model use",
    "cites_reviewed": true
  },
  {
    "cluster_id": "277236244256029686",
    "title": "Analysis of a novel fractional-order chaotic circuit with a feedback memristor: design, dynamics, and application",
    "authors": [
      "H Salman",
      "AA Kader",
      "F Kamal"
    ],
    "first_author_last": "Salman",
    "year": 2025,
    "venue": "Gulf Journal of Mathematics",
    "link": "https://www.gjom.org/index.php/gjom/article/view/2633",
    "doi": "10.56947/gjom.v19i2.2633",
    "cited_by": 0,
    "snippet": "In this research, a novel fractional-order chaotic circuit incorporating a feedback memristor is presented. The structure of the circuit and the associated mathematical model are described …",
    "pdf_url": "https://www.gjom.org/index.php/gjom/article/download/2633/599",
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "Campbell-SDC-2016"
    ],
    "provenance": "cites-harvest",
    "abstract": "In this research, a novel fractional-order chaotic circuit incorporating a feedback memristor is presented. The structure of the circuit and the associated mathematical model are described in detail. The complex dynamics of the circuit are analyzed using stability analysis, Poincaré maps and numerical simulations, revealing the presence of a saddle fixed point and coexisting attractors. The influence of changing the system variables and initial conditions is studied using bifurcation plots and Lyapunov exponents. The circuit exhibits a variety of nonlinear behaviours including periodic, quasi-periodic, and chaotic dynamics. Furthermore, experimental simulations performed with a chain-ship circuit configuration validate the theoretical results and show strong agreement with the numerical analysis. Finally, a robust sound encryption scheme is presented that exploits the pseudorandom sequences generated by the chaotic memristive circuit.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://gjom.org/index.php/gjom/article/download/2633/599",
    "openalex_id": "https://openalex.org/W4409608610",
    "pdf_knowm": "uses-device",
    "relevance": "cites",
    "knowm_role": "cites",
    "human_verdict": "cites-only",
    "human_reason": "CITE (PDF): fractional-order chaotic circuit; single reference to Campbell's self-directed-channel device, no Knowm device/model use",
    "cites_reviewed": true
  },
  {
    "cluster_id": "5600160927812210553",
    "title": "On the Development of Prognostics and System Health Management (PHM) Techniques for ReRAM Applications",
    "authors": [
      "J Cayo",
      "M Melivilu",
      "A Rubio"
    ],
    "first_author_last": "Cayo",
    "year": 2023,
    "venue": "IEEE 29th …",
    "link": "https://ieeexplore.ieee.org/abstract/document/10224898/",
    "doi": "10.1109/iolts59296.2023.10224898",
    "cited_by": 3,
    "snippet": "The resistive switching (RS) technology has many promising applications, but the inherent variability of RS devices has been an important obstacle for the progress towards mass …",
    "pdf_url": "https://upcommons.upc.edu/bitstreams/47efc8ce-2cfe-4bce-abe6-e0d267b5d723/download",
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "Campbell-SDC-2016"
    ],
    "provenance": "cites-harvest",
    "abstract": "The resistive switching (RS) technology has many promising applications, but the inherent variability of RS devices has been an important obstacle for the progress towards mass production. Nonidealities of device switching performance have been widely modeled so far, and device degradation has been addressed through testing for fault diagnosis. However, online soft-error “prognosis” concerning both the progressive degradation and transition faults, has been given little consideration. In this direction, we present preliminary results towards the development of prognostics and system health management (PHM) techniques for resistive memory (ReRAM) applications. We propose addressing soft errors through a rich in context scheme used to encode binary information in form of resistance. In out simulations we assumed a ReRAM driver with multi-level READ capability and developed an enhanced progressive feedback-WRITE scheme to ensure not only successful WRITE and reliable READ operations, but also to permit the early online prognosis of potential device failure. Preliminary system-level simulation results validate the expected functionality and represent a reasonable approach towards the design of robust ReRAM controllers.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://upcommons.upc.edu/bitstreams/47efc8ce-2cfe-4bce-abe6-e0d267b5d723/download",
    "openalex_id": "https://openalex.org/W4386211371",
    "pdf_knowm": "uses-device",
    "relevance": "core",
    "knowm_role": "uses-knowm-device",
    "human_verdict": "uses-knowm-device",
    "human_reason": "YES (PDF): characterizes a 2x2 passive crossbar of SDC devices commercialized by Knowm Inc."
  },
  {
    "cluster_id": "17904430239163040070",
    "title": "Current assisted memory effect in superconductor–ferromagnet bilayers: A potential candidate for memristors",
    "authors": [
      "HM Jafri",
      "X Ma",
      "H Huang",
      "C Zhao"
    ],
    "first_author_last": "Jafri",
    "year": 2019,
    "venue": "Superconductor Science and Technology",
    "link": "https://iopscience.iop.org/article/10.1088/1361-6668/ab1dbf/meta",
    "doi": "10.1088/1361-6668/ab1dbf/meta",
    "cited_by": 5,
    "snippet": "Superconductivity and ferromagnetism are two very useful phenomena, hoewever they rarely coexist in bulk materials. Bringing them together in an artificial hybrid bilayer produces …",
    "pdf_url": "https://ira.lib.polyu.edu.hk/bitstream/10397/106419/1/Shi_Current_Assisted_Memory.pdf",
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "Campbell-SDC-2016"
    ],
    "provenance": "cites-harvest",
    "abstract": "Abstrsct Superconductivity and ferromagnetism are two very useful phenomena, hoewever they rarely coexist in bulk materials. Bringing them together in an artificial hybrid bilayer produces some unusual results. We designed and studied a system of superconductor-ferromagnet bilayer with a thin insulating buffer layer between them. Such a superconductor-ferromagnet bilayer with magnetostatic coupling is proposed for use as a multibit superconductor memory device and a potential candidate as a memristor. Numerical simulations were performed by using Ginzburg–Landau and Landau–Lifshitz-Gilbert models for superconductor and ferromagnet materials, which highlighted some interesting resistive memory effects in the superconducting layer in the bilayer system. A vortex pattern in the superconductor was observed to be strongly coupled with the ferromagnet domain structure, while their dynamics were controlled by the current flowing through the superconductor. Carrier concentration, energy components and magnetization in the superconducting layer were studied as a function of applied current pulses in the superconductor layer, indicating the information storage of the current pulses. Multiple resistive states were observed, pointing towards the possibility that such a device could be used as a multibit data storage device.",
    "abstract_source": "openalex",
    "oa_pdf_url": "http://ira.lib.polyu.edu.hk/bitstream/10397/106419/1/Shi_Current_Assisted_Memory.pdf",
    "openalex_id": "https://openalex.org/W2943603904",
    "pdf_knowm": null,
    "relevance": "cites",
    "knowm_role": "cites",
    "human_verdict": "cites-only",
    "human_reason": "CITE (abstract): superconductor-ferromagnet bilayer memory; cites Campbell as memristor-context, no Knowm use",
    "cites_reviewed": true
  },
  {
    "cluster_id": "O5BNfrmit1MJ",
    "title": "Exploring amorphous Ge-As-Se-Te as an active layer candidate in memristive devices",
    "authors": [
      "W Correr",
      "C Chouinard",
      "S Messaddeq"
    ],
    "first_author_last": "Correr",
    "year": 2023,
    "venue": "Materials Today Electronics",
    "link": "https://www.sciencedirect.com/science/article/pii/S2772949423000402",
    "doi": "10.1016/j.mtelec.2023.100064",
    "cited_by": 0,
    "snippet": "The implementation of resistive switches in neuromorphic computing and long-term data storage has been delayed by inherent difficulties in their fabrication process, their stability …",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "Campbell-SDC-2016"
    ],
    "provenance": "cites-harvest",
    "abstract": "The implementation of resistive switches in neuromorphic computing and long-term data storage has been delayed by inherent difficulties in their fabrication process, their stability and reproducibility. Low operating voltages, high-density integration and low energy consumption are common challenges in resistive switch design. Here, we report the implementation of a resistive switch based on the amorphous semiconductor Ge15As25Se15Te45 (GAST) between an inert (W) and an active (Ag) electrode. The device was built using contact photolithography and standard microfabrication techniques, allowing the integration with traditional manufacturing processes. The device is able to switch at voltages as low as 0.15 V and 0.6 V, when operating in DC and pulsed conditions, respectively. Our results suggest that the adoption of mixed conductors such as GAST may yield devices that operate at low voltages and low energy for neuromorphic applications.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://doi.org/10.1016/j.mtelec.2023.100064",
    "openalex_id": "https://openalex.org/W4387342493",
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    "relevance": "cites",
    "knowm_role": "cites",
    "human_verdict": "cites-only",
    "human_reason": "CITE (PDF): own amorphous Ge-As-Se-Te device; cites Campbell's SDC as related chalcogenide work, no Knowm use",
    "cites_reviewed": true
  },
  {
    "cluster_id": "5618822946688429169",
    "title": "Impact of radiation on pattern recognition in memristor-based neuromorphic circuits",
    "authors": [
      "KD Cantley"
    ],
    "first_author_last": "Cantley",
    "year": 2021,
    "venue": "",
    "link": "https://apps.dtic.mil/sti/html/trecms/AD1137552/",
    "doi": null,
    "cited_by": 2,
    "snippet": "By the nature of their dense interconnectivity, future electronic spiking neural networks (SNNs) have the potential to be extraordinarily robust and defect-tolerant, in addition to …",
    "pdf_url": "https://apps.dtic.mil/sti/pdfs/AD1137552.pdf",
    "is_knowm": false,
    "is_sdc": false,
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    "devices": [],
    "cites_seed": [
      "Campbell-SDC-2016"
    ],
    "provenance": "cites-harvest",
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
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    "relevance": "cites",
    "knowm_role": "cites",
    "human_verdict": "cites-only",
    "human_reason": "CITE (PDF): work uses a TiO2 ionic-drift model; SDC/Campbell only cited as an alternative model, no Knowm device/model use",
    "cites_reviewed": true
  },
  {
    "cluster_id": "741351497655007056",
    "title": "Mechanisms of the Formation of Conductive Channels in Bipolar Memristors of Various Designs",
    "authors": [
      "AN Aleshin",
      "NV Zenchenko",
      "KY Kharitonova"
    ],
    "first_author_last": "Aleshin",
    "year": 2024,
    "venue": "Nanobiotechnology Reports",
    "link": "https://link.springer.com/article/10.1134/S2635167624602900",
    "doi": "10.1134/S2635167624602900",
    "cited_by": 1,
    "snippet": "The work presents and describes various mechanisms for the formation of a conductive channel in bipolar memristors of the vacancy and ionic types: in the first case, due to the …",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "Campbell-SDC-2016"
    ],
    "provenance": "cites-harvest",
    "abstract": "Abstract The work presents and describes various mechanisms for the formation of a conductive channel in bipolar memristors of the vacancy and ionic types: in the first case, due to the generation and growth of conductive threads, and in the second, due to segregation processes with the formation of spatial associations of ions from the material of the active electrode. The current—voltage characteristics for both types of memristors are presented and a comparison of the design features of these memristors is conducted.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4408777988",
    "pdf_knowm": null,
    "relevance": "cites",
    "knowm_role": "cites",
    "human_verdict": "cites-only",
    "human_reason": "CITE (abstract): own bipolar-memristor conductive-channel mechanisms; cites Campbell only",
    "cites_reviewed": true
  },
  {
    "cluster_id": "3988776963864663871",
    "title": "Reliability-aware circuit design to mitigate impact of device defects and variability in emerging memristor-based applications",
    "authors": [
      "M Escudero López"
    ],
    "first_author_last": "López",
    "year": 2020,
    "venue": "",
    "link": "https://upcommons.upc.edu/entities/publication/1644e1ce-4713-4885-8ed2-2cedbc1f5197",
    "doi": "10.5821/dissertation-2117-190675",
    "cited_by": 0,
    "snippet": "In the last decades, semiconductor industry has fostered a fast downscale in technology, propelling the large scale integration of CMOS-based systems. The benefits in …",
    "pdf_url": "https://upcommons.upc.edu/bitstreams/7e734525-86d2-4369-94e9-0c8a1f1f8ebc/download",
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "Campbell-SDC-2016"
    ],
    "provenance": "cites-harvest",
    "abstract": "In the last decades, semiconductor industry has fostered a fast downscale in technology, propelling the large scale integration of CMOS-based systems. The benefits in miniaturization are numerous, highlighting faster switching frequency, lower voltage supply and higher device density. However, this aggressive scaling trend it has not been without challenges, such as leakage currents, yield reduction or the increase in the overall system power dissipation. New materials, changes in the device structures and new architectures are key to keep the miniaturization trend. It is foreseen that 2D integration will eventually come to an insurmountable physical and economic limit, in which new strategic directions are required, such as the development of new device structures, 3D architectures or heterogeneous systems that takes advantage of the best of different technologies, both the ones already consolidated as well as emergent ones that provide performance and efficiency improvements in applications. In this context, memristor arises as one of several candidates in the race to find suitable emergent devices. Memristor, a blend of the words memory and resistor, is a passive device postulated by Leon Chua in 1971. In contrast with the other fundamental passive elements, memristors have the distinctive feature of modifying their resistance according to the charge that passes through these devices, and remaining unaltered when charge no longer flows. Although when it appeared no physical device implementation was acknowledged, HP Labs claimed in 2008 the manufacture of the first real memristor. This milestone triggered an unexpectedly high research activity about memristors, both in searching new materials and structures as well as in potential applications. Nowadays, memristors are not only appreciated in memory systems by their nonvolatile storage properties, but in many other fields, such as digital computing, signal processing circuits, or non-conventional applications like neuromorphic computing or chaotic circuits. In spite of their promising features, memristors show a primarily downside: they show significant device variation and limited lifetime due degradation compared with other alternatives. This Thesis explores the challenges that memristor variation and malfunction imposes in potential applications. The main goal is to propose circuits and strategies that either avoid reliability problems or take advantage of them. Throughout a collection of scenarios in which reliability issues are present, their impact is studied by means of simulations. This thesis is contextualized and their objectives are exposed in Chapter 1. In Chapter 2 the memristor is introduced, at both conceptual and experimental levels, and different compact levels are presented to be later used in simulations. Chapter 3 deepens in the phenomena that causes the lack of reliability in memristors, and models that include these defects in simulations are provided. The rest of the Thesis covers different applications. Therefore, Chapter 4 exhibits nonvolatile memory systems, and specifically an online test method for faulty cells. Digital computing is presented in Chapter 5, where a solution for the yield reduction in logic operations due to memristors variability is proposed. Lastly, Chapter 6 reviews applications in the analog domain, and it focuses in the exploitation of results observed in faulty memristor-based interconnect mediums for chaotic systems synchronization purposes. Finally, the Thesis concludes in Chapter 7 along with perspectives about future work. Este trabajo desarrolla un novedoso dispositivo condensador basado en el uso de la nanotecnología. El dispositivo parte del concepto existente de metal-aislador-metal (MIM), pero en lugar de una capa aislante continua, se utilizan nanopartículas dieléctricas. Las nanopartículas son principalmente de óxido de silicio (sílice) y poliestireno (PS) y los valores de diámetro son 255nm y 295nm respectivamente. Las nanopartículas contribuyen a una alta relación superficie/volumen y están fácilmente disponibles a bajo costo. La tecnología de depósito desarrollada en este trabajo se basa en la técnica de electrospray, que es una tecnología de fabricación ascendente (bottom-up) que permite el procesamiento por lotes y logra un buen compromiso entre una gran superficie y un bajo tiempo de depósito. Con el objetivo de aumentar la superficie de depósito, la configuración de electrospray ha sido ajustada para permitir áreas de depósito de 1cm2 a 25cm2. El dispositivo fabricado, los llamados condensadores de metal aislante de nanopartículas (NP-MIM) ofrecen valores de capacidad más altos que un condensador convencional similar con una capa aislante continua. En el caso de los NP-MIM de sílice, se alcanza un factor de hasta 1000 de mejora de la capacidad, mientras que los NP-MIM de poliestireno exhibe una ganancia de capacidad en el rango de 11. Además, los NP-MIM de sílice muestran comportamientos capacitivos en específicos rangos de frecuencias que depende de la humedad y el grosor de la capa de nanopartículas, mientras que los NP-MIM de poliestireno siempre mantienen su comportamiento capacitivo. Los dispositivos fabricados se han caracterizado mediante medidas de microscopía electrónica de barrido (SEM) complementadas con perforaciones de haz de iones focalizados (FIB) para caracterizar la topografía de los NP-MIMs. Los dispositivos también se han caracterizado por medidas de espectroscopia de impedancia, a diferentes temperaturas y humedades. El origen de la capacitancia aumentada está asociado en parte a la humedad en las interfaces de las nanopartículas. Se ha desarrollado un modelo de un circuito basado en elementos distribuidos para ajustar y predecir el comportamiento eléctrico de los NP-MIMs. En resumen, esta tesis muestra el diseño, fabricación, caracterización y modelización de un nuevo y prometedor condensador nanopartículas metal-aislante-metal que puede abrir el camino al desarrollo de una nueva tecnología de supercondensadores MIM.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://upcommons.upc.edu/bitstream/2117/190675/1/TMEL1de1.pdf",
    "openalex_id": "https://openalex.org/W3043656780",
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    "relevance": "cites",
    "knowm_role": "cites",
    "cites_reviewed": true
  },
  {
    "cluster_id": "KlEhd7ca3TcJ",
    "title": "Analysis of Learning Mechanisms in Spiking Neural Networks with R (t) Elements and Memristive Synapses",
    "authors": [
      "F Afrin"
    ],
    "first_author_last": "Afrin",
    "year": 2024,
    "venue": "",
    "link": "https://scholarworks.boisestate.edu/td/2302/",
    "doi": "10.18122/td.2302.boisestate",
    "cited_by": 0,
    "snippet": "As Moore's law ends, the conventional von Neumann computer architecture with binary-coded data representation has reached its bottleneck because of having separate …",
    "pdf_url": "https://scholarworks.boisestate.edu/cgi/viewcontent.cgi?article=3440&context=td",
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "Campbell-SDC-2016"
    ],
    "provenance": "cites-harvest",
    "abstract": "As Moore's law ends, the conventional von Neumann computer architecture with binary-coded data representation has reached its bottleneck because of having separate computing and memory modules. In this architecture, continuous power is required due to sequential processing, making it challenging to improve efficiency further. The human brain can be regarded as the most energy-efficient computer architecture. In the brain, data is represented as small voltage pulses as spikes. That is why the neural units are called spiking neural networks (SNN). In SNNs, energy is required only when there is a spike, making it more energy efficient than the von-Neumann computer architecture. Therefore, in recent decades, researchers in this field have been interested in mimicking the data processing of the human brain in electronic circuits. In biological SNNs, data is propagated from one neuron to another via a synapse. When there is an incoming spike, the chemical weight changes in the synapse, and the next neuron receives the signal. In the electronic neural network, a memristor, a two-terminal nonvolatile memory element, can emulate the function of a synapse by changing its conductance while receiving a pulse. The most common learning rule in the spiking neural network is Spike-Timing-Dependent Plasticity (STDP), which refers to the change of synaptic weight with respect to the time difference between pre- and post-synaptic neural spikes. Although electronic SNNs comprised of memristors with the STDP learning rule have shown promising performance in various event-driven tasks, circuit complexity limitations and a lack of third-order parametric inclusion exist. A solution can be using a simple circuit element to modulate the memristor response.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://scholarworks.boisestate.edu/cgi/viewcontent.cgi?article=3440&context=td",
    "openalex_id": "https://openalex.org/W4414119351",
    "pdf_knowm": "uses-device",
    "relevance": "core",
    "knowm_role": "uses-knowm-model",
    "human_verdict": "uses-knowm-model",
    "human_reason": "YES (PDF): Boise State thesis simulates spiking nets on Knowm SDC devices via the MSS/metastable-switch model (27 'Knowm', 10 'MSS' hits)"
  },
  {
    "cluster_id": "U7SH7XajUjkJ",
    "title": "The Memristor and its Implementation in Deep Neural Network Designing: A Review",
    "authors": [
      "MN Getachew",
      "R Priyadarshini",
      "RM Mehra"
    ],
    "first_author_last": "Getachew",
    "year": 2022,
    "venue": "Artificial Intelligence",
    "link": "https://www.taylorfrancis.com/chapters/edit/10.1201/9781003217237-10/memristor-implementation-deep-neural-network-designing-melaku-nigus-getachew-rashmi-priyadarshini-mehra",
    "doi": "10.1201/9781003217237-10/memristor-implementation-deep-neural-network-designing-melaku-nigus-getachew-rashmi-priyadarshini-mehra",
    "cited_by": 0,
    "snippet": "This chapter provides a general review of memristor device application in designing hardware deep neural networks such as spiking neural network (SNNs), multilevel neural …",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "Campbell-SDC-2016"
    ],
    "provenance": "cites-harvest",
    "abstract": null,
    "abstract_source": "scholar-snippet",
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  },
  {
    "cluster_id": "10955310523963571029",
    "title": "Study of resistive switching in GeSx/Ag system for neuromorphic computing applications",
    "authors": [
      "N Lyapunov"
    ],
    "first_author_last": "Lyapunov",
    "year": 2022,
    "venue": "",
    "link": "https://theses.lib.polyu.edu.hk/handle/200/11944",
    "doi": null,
    "cited_by": 0,
    "snippet": "As a promising building block of the emerging neuromorphic computing hardware, memory devices with multi-functionalities realized in a single memory device are highly demanded …",
    "pdf_url": "https://theses.lib.polyu.edu.hk/bitstream/200/11944/3/6392.pdf",
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "Campbell-SDC-2016"
    ],
    "provenance": "cites-harvest",
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": null,
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    "relevance": "cites",
    "knowm_role": "cites",
    "human_verdict": "cites-only",
    "human_reason": "CITE (PDF): own GeSx/Ag device thesis; cites Campbell (SnSe/SDC) as prior chalcogenide work, no Knowm device/model use",
    "cites_reviewed": true
  },
  {
    "cluster_id": "4114933006457224936",
    "title": "CMOS leaky integrate-and-fire neuron circuit with memristorbased synapses reveals biologically plausible information transmission",
    "authors": [
      "L Benatti",
      "T Zanotti",
      "D Gandolfi",
      "J Mapelli"
    ],
    "first_author_last": "Benatti",
    "year": 2023,
    "venue": "Workshop on Brain …",
    "link": "https://iris.unimore.it/bitstream/11380/1389712/1/9782832512340.PDF",
    "doi": null,
    "cited_by": 0,
    "snippet": "The abstracts in this collection have not been subject to any Frontiers peer review or checks, and are not endorsed by Frontiers. They are made available through the Frontiers …",
    "pdf_url": "https://iris.unimore.it/bitstream/11380/1389712/1/9782832512340.PDF",
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "Campbell-SDC-2016"
    ],
    "provenance": "cites-harvest",
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": null,
    "pdf_knowm": "uses-device",
    "relevance": "core",
    "knowm_role": "uses-knowm-model",
    "human_verdict": "uses-knowm-model",
    "human_reason": "YES (PDF): CMOS LIF neuron models the Knowm SDC device (MSS)"
  },
  {
    "cluster_id": "608225054850384762",
    "title": "Features of the Formation of Conductive Channels in Memristors Based on Solid Electrolytes",
    "authors": [
      "AN Aleshin",
      "NV Zenchenko",
      "OA Ruban"
    ],
    "first_author_last": "Aleshin",
    "year": 2022,
    "venue": "Nanobiotechnology Reports",
    "link": "https://link.springer.com/article/10.1134/S2635167622070023",
    "doi": "10.1134/S2635167622070023",
    "cited_by": 1,
    "snippet": "Experimental data on measurement of the resistance and electrical conductivity in the low-resistance mode of operation of a germanium-selenide-based memristor with a self-forming …",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "Campbell-SDC-2016"
    ],
    "provenance": "cites-harvest",
    "abstract": "Abstract Experimental data on measurement of the resistance and electrical conductivity in the low-resistance mode of operation of a germanium-selenide-based memristor with a self-forming conductive channel in the form of a silver filament are obtained in the range of operating frequencies and temperatures. In the frequency experiment, the influence of the switching frequency is tested at room temperature in the range of 1–10 000 Hz. The main result of the experiment is the identification of a linear relationship between the electrical conductivity and the memristor operating cycle time in semilogarithmic coordinates, which made it possible to introduce a temperature-dependent kinetic constant. This experimental fact made it possible to establish the main parameter affecting the shape of the current–voltage characteristics, namely the thickness of the conductive channel.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4323021652",
    "pdf_knowm": null,
    "relevance": "core",
    "knowm_role": "named-in-abstract"
  },
  {
    "cluster_id": "B2jW0jltTC8J",
    "title": "High Speed Readout Techniques for High Density Non-Volatile Memristor Crossbar Memory with Suppressed Sneak-Path Current",
    "authors": [
      "MR Khan",
      "KA Faruque",
      "ABM Rashid"
    ],
    "first_author_last": "Khan",
    "year": 2023,
    "venue": "SSRN Electronic Journal",
    "link": "https://papers.ssrn.com/sol3/papers.cfm?abstract_id=4473721",
    "doi": "10.2139/ssrn.4473721",
    "cited_by": 0,
    "snippet": "The realization of memristor appears as a smart solution for memory based research. Gateless memristor crossbar architecture is very promising technology for future memory …",
    "pdf_url": "https://papers.ssrn.com/sol3/Delivery.cfm?abstractid=4473721",
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "Campbell-SDC-2016"
    ],
    "provenance": "cites-harvest",
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": "http://dx.doi.org/10.2139/ssrn.4473721",
    "openalex_id": "https://openalex.org/W4391492185",
    "pdf_knowm": "uses-device",
    "relevance": "cites",
    "knowm_role": "cites",
    "cites_reviewed": true
  },
  {
    "cluster_id": "13645235617489950009",
    "title": "Modeling Memristor–Based Circuit Networks on Crossbar Architectures",
    "authors": [
      "I Vourkas",
      "GC Sirakoulis"
    ],
    "first_author_last": "Vourkas",
    "year": 2019,
    "venue": "Handbook of Memristor Networks",
    "link": "https://link.springer.com/chapter/10.1007/978-3-319-76375-0_34",
    "doi": "10.1007/978-3-319-76375-0_34",
    "cited_by": 3,
    "snippet": "Almost 50 years have been completed ever since Leon Chua proposed the existence of a new class of passive circuit elements, which he called memristors and memristive devices …",
    "pdf_url": null,
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "Campbell-SDC-2016"
    ],
    "provenance": "cites-harvest",
    "abstract": null,
    "abstract_source": "scholar-snippet",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W4248397634",
    "pdf_knowm": null,
    "relevance": "cites",
    "knowm_role": "cites",
    "human_verdict": "cites-only",
    "human_reason": "CITE (abstract): tunneling-model crossbar circuits; cites Campbell only",
    "cites_reviewed": true
  },
  {
    "cluster_id": "Ek5gC4v7yl8J",
    "title": "Novel Memristor Based True Random Number Generator",
    "authors": [
      "S Stoller"
    ],
    "first_author_last": "Stoller",
    "year": 2020,
    "venue": "",
    "link": "https://scholarworks.boisestate.edu/td/1770/",
    "doi": "10.18122/td/1770/boisestate",
    "cited_by": 0,
    "snippet": "Random numbers are an important, but often overlooked part of the modern computing environment. They are used everywhere around us for a variety of purposes, from simple …",
    "pdf_url": "https://scholarworks.boisestate.edu/cgi/viewcontent.cgi?article=2888&context=td",
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "Campbell-SDC-2016"
    ],
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    "abstract": "Random numbers are an important, but often overlooked part of the modern computing environment. They are used everywhere around us for a variety of purposes, from simple decision making in video games such as a coin toss, to securing financial transactions and encrypting confidential communications. They are even useful for gambling and the lottery. Random numbers are generated in many ways. Pseudo random number generators (PRNGs) generate numbers based on a formula. True random number generators (TRNGs) capture entropy from the environment to generate randomness. As our society and our devices become more connected in the digital world, it is important to develop new ways to generate truly random numbers in order to secure communications and connected devices. In this work a novel memristor-based True Random Number Generator is designed and a physical implementation is fabricated and tested using a W-based self-directed channel (SDC) memristor. The circuit was initially designed and prototyped on a breadboard. A custom Printed Circuit Board (PCB) was fabricated for the final circuit design and testing of the novel memristor-based TRNG. The National Institute of Standards and Technology (NIST) Statistical Test Suite (STS) was used to check the output of the TRNG for randomness. The TRNG was demonstrated to pass 13 statistical tests out of the 15 in the STS.",
    "abstract_source": "openalex",
    "oa_pdf_url": "https://scholarworks.boisestate.edu/cgi/viewcontent.cgi?article=2888&context=td",
    "openalex_id": "https://openalex.org/W3153719837",
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  },
  {
    "cluster_id": "1773786272125571662",
    "title": "Memristor Engineering: Modeling, Fabrication, and Characterization",
    "authors": [
      "AY Yamamoto"
    ],
    "first_author_last": "Yamamoto",
    "year": 2019,
    "venue": "",
    "link": "https://search.proquest.com/openview/e72f92e031b0070c53f91f66c3797d49/1?pq-origsite=gscholar&cbl=18750&diss=y",
    "doi": null,
    "cited_by": 0,
    "snippet": "Memristors are the predicted fourth fundamental passive element of circuits, connecting a previously missing relationship between charge q and flux-linkage φ. It was first fabricated …",
    "pdf_url": "https://oaktrust.library.tamu.edu/bitstreams/b6d5a48b-4344-4016-8c04-e5d6b708b627/download",
    "is_knowm": false,
    "is_sdc": false,
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      "Campbell-SDC-2016"
    ],
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    "abstract": null,
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    "human_verdict": "uses-knowm-device",
    "human_reason": "YES (user): thesis characterizes the Carbon and Tungsten Knowm devices (i-v / Ω-q curves)"
  },
  {
    "cluster_id": "15458139124340785753",
    "title": "Memristors in Nonlinear Network: Application to Information (Signal and Image) Processing",
    "authors": [
      "A Isah"
    ],
    "first_author_last": "Isah",
    "year": 2021,
    "venue": "",
    "link": "https://theses.hal.science/tel-03470169/",
    "doi": "10.70675/d071f6d0zda25z433az8436z64ac8b3979c6",
    "cited_by": 0,
    "snippet": "Memristor is a two-terminal nonlinear dynamic electronic device. Typically, it is a passive nano-device whose conductivity is controlled by the flux, time-integral of the voltage across …",
    "pdf_url": "https://theses.hal.science/tel-03470169/file/96517_ISAH_2021_archivage.pdf",
    "is_knowm": false,
    "is_sdc": false,
    "is_mss": false,
    "devices": [],
    "cites_seed": [
      "Campbell-SDC-2016"
    ],
    "provenance": "cites-harvest",
    "abstract": "Application des memristors au traitement du signal et des images Le memristor est un dipôle électronique dynamique non linéaire. Typiquement, il s’agit d’un dispositif de nanotechnologie passif dont la conductivité est contrôlée par le flux, l’intégrale de la tension à ses bornes, ou par la charge, l’intégrale du courant qui le traverse, présentant des caractéristiques intéressantes pour des applications polyvalentes. Cette thèse est consacrée à l’utilisation de memristor comme élément de couplage d’un réseau cellulaire non linéaire, en vue du traitement de l’information (image et signal) ou comme prothèse électronique d’un système neuronal. Nous développons un modèle de réseaux cellulaires non linéaires 2D basés sur le memristor, en incorporant le memristor dans le couplage de cellules voisines. Cette approche offre de nombreux avantages par rapport à ce qui est utilisé actuellement. Parmi ces avantages, on peut citer une densité de pixels plus élevée en raison de la nano-nature du memristor, une consommation d’énergie plus faible, une flexibilité de connexion à haute densité, la compatibilité avec la technologie CMOS, etc… Tout d’abord, nous présentons l’état de l’art sur le memristor, ainsi qu’un modèle analogique de memristor à des fins pratiques et de démonstration. Ensuite, nous présentons le comportement quantitatif et qualitatif d’un memristor contrôlé par la charge en considérant les réseaux RC avec le memristor en mode couplage, en se concentrant spécifiquement sur le système de deux cellules RC initialement chargées. Nous étudions en détail l’interaction de deux cellules Fitzhugh-Nagumo via un memristor en observant la réponse transitoire de chaque cellule, ce qui nous permet d’avoir une bonne compréhension de la fonctionnalité memristor et de l’effet de diffusion dans un treillis électrique cellulaire non linéaire 1D. En outre, nous présentons le modèle généralisé des CNNs 2D basés sur le memristor pour le traitement de n’importe quel nombre de cellules.",
    "abstract_source": "openalex",
    "oa_pdf_url": null,
    "openalex_id": "https://openalex.org/W7151104551",
    "pdf_knowm": "uses-device",
    "relevance": "cites",
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    "cites_reviewed": true
  },
  {
    "cluster_id": "kAdKXlPi-q0J",
    "title": "Memristor: funcionamiento y aplicaciones",
    "authors": [
      "J Grande de Miguel"
    ],
    "first_author_last": "Miguel",
    "year": 2021,
    "venue": "",
    "link": "",
    "doi": null,
    "cited_by": 0,
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  }
]