A Decade of Knowm SDC Memristor Literature, Part 2

In Part 1 I built a corpus of every paper I could find that uses or cites our Self-Directed Channel (SDC) memristor or the MSS model, and sized it up: how much there is, where in the world it comes from, and which of our three exports — the device, the model, the architecture — spread. This article is about what people did once they had the part in hand.

First, what we put in their hands. Over the decade we sold four kinds of the Self-Directed Channel device — tungsten, tin, chromium, and carbon — and built and sold the open-source Memristor Discovery board to drive them on a bench. Around all of it we released four open-source projects — memristor-models-4-all (the SPICE / Verilog-A models), jSpice (our circuit simulator), AHaH (the machine-learning code), and the Memristor Discovery software itself — plus a stack of tutorials, so a researcher could go from a cold start to real data in an afternoon.

I closed Part 1 with a promise: neuromorphic synapses, in-memory logic, chaos circuits, hardware security, and a few strange applications. Everything below comes from the same papers.json corpus — download it and sort it yourself.

One caveat governs every number that follows. I sorted the papers that actually put the device or the model to work into application domains. A single paper often lands in two or three at once — a SPICE-modeling paper that builds a synapse, a logic paper that also characterizes variability — so I assigned each one a primary bucket by intent. The counts overlap and do not add up to the corpus total. Read them as proportions, not as a partition. There are also near-duplicate records in here (a preprint and its journal version, an English paper and its Polish or Chinese twin), so treat the raw counts as roughly 10–15% high in the busier domains.

Where the work went#

Each block is a group of papers, sized by how many, and clicking one zooms into what that group built.

A few things I read off the map:

1. The single biggest bucket is not an application at all. It is people learning to model and measure the device. That is a direct consequence of the one fact that makes Knowm unusual: it is the only memristor you can buy, so a large slice of the literature is “how do I trust this thing in a simulation.”
2. The biggest real application is neuromorphic — synapses and spiking networks — and it is the fastest-growing one, pulling away from 2022 onward.
3. The three big blocks are nearly tied. Modeling-and-measuring the part, computing with it (neuromorphic plus ML accelerators), and logic each land around 60 papers. Logic only looks smaller when you split its two lineages — stateful/IMPLY and ternary — which come from different groups.
4. The long tail is the most surprising part. Chaos circuits, hardware security, reservoir computing, RF filters, an artificial pain receptor — small buckets, but they are the clearest evidence that the device went places we never designed it to go.

Biggest bucket first.

People learning to trust the model (~45 papers)#

The largest and most foundational cluster is device modeling and characterization. This is the unglamorous work of turning a physical part into a set of numbers you can put in a SPICE deck, and it is the base the rest of the corpus stands on.

One split runs under the whole corpus: how many papers put a real device on a bench versus simulated it with the model.

It leans toward hardware — 164 measured a real device, 96 used the MSS model, 37 did both. The device is not a simulation-only object; more groups have it on a bench than in a netlist. The counts are lower bounds, too: 117 more papers name or cite Knowm without leaving a decisive device-or-model signal, mostly because we have no PDF to check.

Our own Generalized Metastable Switch model (Molter 2016, 74 cites) is the canonical starting point — stochastic switching plus a diode current, which is what most of these papers lean on or measure against. From there the field kept refining. Ostrovskii’s structural and parametric identification (2021, 55 cites) is the most-cited of the pure characterization works — a method that pulls out low-current effects, cycle-to-cycle variability, and snapback. A sustained program out of AGH Kraków (Garda, then Bednarz) fit Strukov, Biolek, VTEAM, Yakopcic, and MMS models against W-, C-, Sn-, and Cr-doped SDC devices under sinusoidal and triangular drive across frequency, and Bednarz’s 2024 extensive study does a head-to-head across four chemistries with no single winner. Vourkas’ beginner’s guide to behavioral models (2025) is a step-by-step SPICE netlist recipe that reproduces the device’s resistance saturation and fading-memory faults.

I like that this whole domain takes the device’s non-idealities seriously instead of idealizing them away. Radakovits’ BELIEVER model (2021) and Gulafshan’s 2025 behavioral model exist specifically to reproduce the leakage, drift, and device-to-device variability that the clean models miss. If you are about to model an SDC part, this is the bucket to read first — and the MSS model in memristor-models-4-all is the baseline they are all measuring against.

Neuromorphic synapses and spiking networks (~38 papers)#

This is the biggest actual application, and the one growing fastest — the count roughly doubles from the late 2010s into the mid 2020s. The device gets used as a synapse: an analog weight you can nudge up or down and read. Here is that loop on real hardware — our Memristor Discovery board driving Knowm memristors:

Berdan’s short-term synaptic dynamics paper (2016, 139 cites) is the heavily-cited anchor for using memristive devices as biology-faithful synapses. From there it spreads in two directions. One is faithful plasticity: Ma’s homeostatic inhibitory plasticity circuit (2023) builds a Knowm synapse validated in PSpice, and several groups map STDP and spike-rate-dependent plasticity directly on the part. The other is practical accelerators: Florini’s hybrid CMOS-memristor SNN (2022, 23 cites) supports multiple coexisting learning rules on one substrate, and Zhou’s MEMprop work (2022, 32 cites) runs backprop-through-time directly on SPICE models of memristive neurons and synapses.

The most recent papers push toward edge AI. Souto’s MemTorch CNN simulation (2024) runs MNIST and CIFAR through a memristive convolutional net at about 1% precision loss, and Go’s 2026 hybrid CMOS–SDC convolutional spiking net targets edge intelligence on a 1T1R crossbar. Biswas (2024) characterizes silver-based SDC devices specifically as artificial synapses, mapping the conductance states you would build a network out of.

Almost everyone here wires it the same way: one memristor is one synapse — one device, one weight — often sitting in a 1T1R cell next to an access transistor. Our own differential pair — two memristors sharing one output node, the weight the normalized difference between them — barely shows up in the collection of papers that cite us. (Some analog accelerators do put two devices on a weight, but for a narrower reason: a G⁺/G⁻ pair read through a subtractor, just to represent a negative number — Krestinskaya’s GAN below is the clearest case. That is not the same as the balanced shared-node pair, which adds common-mode rejection and symmetric writes on top of the sign.) The exceptions are the AHaH adopters (Abbood 2021, and the Si/Xu group behind Xie 2026) and Przyczyna’s four-memristor bridge synapse for seizure detection, which I get to below.

In-memory logic (~25 + ~22 papers)#

Two separate logic lineages show up, from different groups, both built on the same idea — do the computation inside the memory instead of shuttling operands out to an ALU.

The first is stateful / IMPLY logic, and it is largely one group: Nima TaheriNejad’s at TU Wien. The headline is SIXOR (2021, 42 cites) — a single-cycle in-memristor XOR, twice as fast as the prior stateful approach — sitting on top of a semi-serial IMPLY full adder (2019, 27 cites) that trades area against latency. The lineage tackles device variability: Laube (2021), Seiler (2025), and Qiu’s approximate IMPLY adders (2024) are all about staying correct when the devices don’t behave identically. Ballbe’s 2017 IMPLY gate is a rare one built with actual Knowm hardware rather than a model, and Wang’s 2024 cellular automata derives elementary CA rules from three-memristor stateful logic.

The second is ternary and multi-valued logic — storing more than two states per device to get more data per wire, usually in a hybrid memristor–CMOS family. This one is dominated by a cluster of “Wang” authors (often with Eshraghian). The most-cited is low-variance ternary combinational logic (2022, 32 cites): ternary adders, multipliers, and comparators in SPICE with the Knowm model, plus hardware validation. They synthesized ternary decoders on an FPGA driving a seven-segment display (2022, 14 cites), and the line runs right up to a balanced ternary full adder in 2026. It is a large, sustained push, though heavy with near-duplicate records.

Analog compute in the array (~12 papers)#

This is the domain that gets closest to what we are building toward — the crossbar as a physical matrix-vector multiplier, the math done by Ohm’s and Kirchhoff’s laws in one analog step.

Eshraghian’s analog weights in ReRAM DNN accelerators (2019, 36 cites) uses one memristor per weight, encoding the value in both the device’s conductance and the input frequency to beat one-bit-per-device — which works precisely because the images are unsigned, so there is no negative weight to represent and no need for a second device. Krestinskaya’s analog memristive GAN (2020, 57 cites — the most-cited paper in this accelerator bucket) simulates a full DCGAN with 1.7 million devices at roughly 47 nW per operation. Its weights are the opposite: each signed weight is a two-memristor G⁺/G⁻ pair read through an op-amp subtractor, with a separate “sign crossbar” holding the sign as a R_ON/R_OFF state. Two devices per weight. Across these accelerators the second memristor shows up exactly when the weight has to go negative. Nair (2023) builds a memristive PixelCNN; Radhakrishnan (2023) an NLP text-analytics accelerator.

Two 2026 papers (Tariq, Fiacco) put memristive vector-matrix multiply and FPGA logic toward the trigger electronics of the CERN ATLAS detector — memristive dot-products deciding, in real time, which particle collisions to keep. That is a target I did not expect to see. Tariq’s group tunes a Knowm array to eight distinct conductance states across a 20–250 µS (microsiemens) window, to within a 6–8% programming error, then runs a four-dimensional dot product on a 1×16 array. Setting an analog weight that precisely is still the hard part, and that 6–8% is where it shows. On the open-hardware side, Safa’s OpenMENA (2025) is an 8×8 memristor compute board in the same spirit as our own Memristor Discovery platform.

Chaos, oscillators, and a caveat (~22 papers)#

Researchers love that the Knowm part is a real, nonlinear element you can drop into a classic circuit, and a whole experimentally-grounded domain grew out of that. Volos’ “A dream that has come true” (2020, 44 cites) is the anchor — the first experimental chaos from a nonlinear circuit built with a real memristor, with period-doubling and double-scroll attractors on a scope, not just in simulation. Minati, Faqiang, and Wang extend the physical-memristor chaotic oscillator line; He’s spatiotemporal chaos (2024, 31 cites) works it out in theory. The oscillator sub-thread is a grab bag: a Liénard oscillator (Çakır 2024), a Twin-T sine generator (Zhang 2024), relaxation and Wien-bridge cases (Lopez-Jimenez 2025), a sawtooth generator (Karakulak 2024).

One watch-out. In several of these circuits the device is doing its job precisely because it is not acting like a memristor. Laskaridis’ Shinriki-oscillator work (2022) uses the Knowm part as a static nonlinear resistor — the pinched hysteresis loop collapses at the frequencies they run, and what is left is just a well-behaved nonlinearity. That is not a knock on the work; it is a real operating regime you should know about before you assume “memristor” describes what your circuit sees.

Memory and analog programming (~22 papers)#

If you want to store more than one bit in a device and read it back reliably, this is the bucket. The standout thread is out of UPC-Barcelona. Gomez’s voltage divider for self-limited analog programming (2019, 30 cites) and the companion multi-level tuning study (2019, 34 cites) work out how to set precise intermediate states without the write running away. Cirera’s series (2022–2023) pushes a distinctive current-driven rather than voltage-driven programming line — forming, WRITE/READ, series and anti-series pairs, even stochastic resonance — claiming better switching uniformity and bit-error ratio. Garda’s SDC-for-RRAM study (2024) and Ramirez’s write-verify algorithm against variability (2024) round it out. The rough consensus is that you can get on the order of 6-plus bits out of an SDC cell, but only with a write-verify loop — not open-loop.

Hardware security (~6 papers)#

Small bucket, but I have a soft spot for it because it inverts everything the memory and logic people are fighting. Every other domain treats device-to-device variability as the enemy. The security people treat it as the point: a Physical Unclonable Function needs randomness you can’t clone, and the SDC device’s variability is exactly that. Stoller’s TRNG work (2021, 15 cites) builds three true-random-number generators from off-the-shelf parts including the Knowm device and passes them through the NIST statistical test suite. The Arul/Frank group in Germany uses Knowm 16-cell arrays as PUFs, generating challenge-response pairs straight out of the device variability. If you have been cursing your parts for not matching, these are the folks who found a use for it.

The strange ones#

None of the following was on any roadmap. This is what happens when you put a real, characterizable analog device in people’s hands and open-source the model — the field finds uses you would never have designed for.

• An artificial pain receptor. Wang’s self-reconfigurable nociceptor (2024) builds a memristive pain receptor with threshold, no-adaptation, and sensitization behaviors — and temperature dependence — out of an SDC device.
• Seizure detection from a wristband. Przyczyna’s bridge-synapse reservoir computer (2022) is a single-node echo-state machine — a four-memristor bridge plus a differential amplifier — that flags epileptic seizures from a wrist-worn triaxial accelerometer. They pass on EEG deliberately: it is the clinical gold standard but impractical to wear through a normal day, so they classify motion instead, from 408 instances across three patients. A tiny domain (reservoir computing is only ~3 papers) with a concrete biomedical payoff.
• Adaptive robot perception. Wang’s adaptive neuromorphic perception (2024, 59 cites, Nature Communications) does robot-hand grasping with roughly 1 ms adaptation and autonomous-driving decision-making.
• A field-programmable metamaterial. Hong (2023) uses a Knowm memristor as the stable switching element in a reconfigurable electromagnetic metamaterial.
• Power electronics. Wu’s 20-kHz memristor-based PWM (2025) pushes the device into power-converter control, which is a long way from neuromorphic anything.
• Ultrasound for tissue characterization. The Santos “memosducer” line (2016 onward) uses the device in a reservoir-style ultrasonic transducer for biomedical tissue.
• Quantum entanglement, with slime molds. Miranda and Schmidt (2025) tried to simulate quantum entanglement using Knowm memristors alongside living Physarum polycephalum slime molds as bioelectronic components. It was a negative result — parasitic capacitance, and the molds showed no memristive behavior — but I am including it because someone tried it, and a negative result is still a result.

And one inversion worth its own note: a small cluster (~10 papers) builds other mem-elements — meminductors and memcapacitors — out of a real Knowm memristor plus op-amps (Lei-Jie 2019, Wang 2022 floating memcapacitor). The usual trope is to emulate a memristor with conventional parts; here the real part is the thing you build the missing elements from.

One lab deep#

Sort the domains by who actually works in them, and many are carried by a single group. Stateful logic is largely TU Wien; the ternary-logic push is one cluster of “Wang” authors; the real-memristor chaos line is Volos and Laskaridis in Greece; multi-level analog programming is UPC-Barcelona; the SPICE-characterization backbone leans on AGH Kraków; and the device physics is Boise State, because they are the ones who can change the part. Only the two biggest buckets — general modeling and neuromorphic — are many-handed.

This cuts two ways. If you are entering one of the blue domains, there is a clear body of prior art and often a group to talk to — but also a house style you are stepping into. And it means a lot of these directions are one funding decision or one graduated PhD away from going quiet.

What this adds up to#

One theme runs through most of the real applications: people testing whether you can do the computation in the analog domain, where the weight is the device and the arithmetic happens in place, instead of moving numbers back and forth to an ALU. The synapse work, the in-memory logic, the crossbar accelerators, even the chaos circuits — they are all, in different accents, exploring the same bet.

Two notes to end on. First, the one thing that did not travel is the computing architecture we built on top of the device — kT-RAM and the AHaH nodes. As I showed in Part 1, the device and the model are everywhere; the architecture has almost no outside adopters, with a recent Chinese group (Xu 2025, Xie 2026) the notable exception. Second, a real slice of this corpus is spent arguing about whether the SDC device is even a memristor at all — the Pershin–Di Ventra test (Kim 2020, 38 cites) says it fails the ideal-memristor definition, and others have piled on. That fight — whether the SDC is “really” a memristor — is its own rabbit hole, and one for another day.

This is where the survey ends — two parts over one reproducible corpus, a decade of what the field did with our device and model. The one thing it barely did was build with the differential pair — two memristors read as a single weight. That is a strange gap, because the pair is everywhere in analog AI once you look: IBM’s phase-change pairs, the 2T2R RRAM cell, the memristor-bridge synapse. Almost everyone arrived at “two devices, one weight”.

That is the thread I am pulling next, in a standalone piece: the kT-synapse and the AHaH node, set against every other group that found the pair. New corpus, same open and reproducible approach.

If I filed your paper in the wrong bucket, or missed it entirely, tell me and I’ll fix the corpus.