How 374 Papers Build a Signed Synaptic Weight

I spent the last couple of weeks building a literature corpus to answer a question I’d been curious about for a long time: if you want to use memristors as synapses, how does the field actually do it — how many devices per weight, wired how, and read how? This post is the map the corpus produced — the configurations, the counts, and the trade-offs between them.

The question starts with a fact every analog neural network has to deal with: a memristor’s conductance is a positive number — there is no such thing as negative conductance — and the most useful kind of synaptic weight is a signed one.

Why signed? A neuron decides by summing weighted inputs and comparing the total to a threshold, and that weighted sum draws a boundary through the neuron’s input space: fire on one side, stay quiet on the other. A negative weight is what lets an input push against firing — it’s how a synapse says “evidence against,” the electrical version of biology’s inhibitory synapse. You can clamp every weight positive and still compute — a real fraction of the literature does exactly that, and we’ll count it below. But most of the boundaries a neuron could otherwise learn become unreachable, because you’ve given up half of every weight’s range before training starts. Our 2014 AHaH paper builds on exactly this: learning there means “seek[ing] a hyperplane that separates the input data into two classes resulting in two distinct positive and negative distributions.” The signed weight is how that state is physically held: “the … weight may be positive or negative. We achieve the notion of state in our physical circuits via differential conductances.”

So a positive-only conductance leaves you a choice, not a wall: use one device and live with unsigned weights (or buy the sign somewhere else — more on that road below), or spend more devices and read a difference.

The field’s answers sit on a spectrum of how many devices you spend per weight — one, two, or many — but underneath they all make the same move: the weight is read as a difference. One device gets its sign by subtracting a shared reference. Two devices subtract each other. A bank of many devices subtracts two banks. The device count changes, the subtraction doesn’t.

Here is the whole map up front — every configuration the corpus found, with paper counts. The rest of the post walks through each one, its trade-offs, and who builds it:

Knowm builds on the two-device version. We call it the kT-synapse. Two memristors run from opposite rails, and the weight is the difference between them. Two devices, one weight, sign for free. The kT-synapse is the pair, not one particular wiring of it. Our patents enumerate all three electrode configurations, 1-2, 2-1 and 2-2, and a kT-synapse can be built in any of them. We have published and demonstrated mostly on the 2-1, where the difference forms at a shared node. The pair is the unit the AHaH node is built from, and the whole kT-RAM architecture stands on it. Chapter 3b derives the physics of a single pair, and Chapter 4 builds the neural lane out of it. If the pair is wrong, none of the rest matters.

Here’s how I built the corpus. I harvested 374 candidate papers from Google Scholar, then screened every one for a single thing: does this paper represent one synaptic weight using two or more memristive devices? 233 of them do, once Knowm’s own papers are set aside. Every number below comes out of that corpus, through a pipeline I describe at the bottom of the post.

Two ground rules I set before starting, so the numbers can’t quietly flatter us:

1. Knowm’s own papers are excluded from every count. Our work is the thing being compared against, not evidence for the comparison — counting it would beg the question. (Independent groups that merely bought Knowm parts and built their own thing, like the AGH Kraków bridge-synapse group, do count.)
2. The screen can confirm a pair but never refute one. A paper that names the two-device cell counts. A paper whose abstract is silent on topology goes to a review queue, not to “excluded.” Plenty of papers only reveal the cell in their methods or a figure, so a missing mention is missing data, not a “no.”

One device, two, or many#

Before going further it’s worth being precise about how many devices “the pair” actually means, because the field doesn’t do exactly one thing. There are three regimes.

One device. The natural first thing to try is a single memristor as a synapse: one conductance, one weight. And it is no dead end — it’s the other main road, and arguably the more travelled one. I ran a second, parallel harvest just for it, and screened every hit the same way: does this paper build a synapse from exactly one memristive device? 131 papers do — overwhelmingly RRAM in 1T1R arrays — among them some of the most-cited chips in the field: Hu’s 2016 dot-product engine (905 citations), Long’s 2018 ReRAM processing-in-memory engine, Midya’s 2019 spiking network.

The catch is the one the post opens with — a single conductance is positive, a weight needs a sign, and one device can’t supply it on its own — so these designs get the sign from somewhere else. The most common route is a shared reference column, where the weight is read as G − G_ref: the single-device array doesn’t escape the difference, it just relocates it — from a per-weight partner (the pair) to a per-column reference. Even here, everyone subtracts.

The in-between case: one memristor and one resistor#

Between “one device, no sign” and “two devices, both moving” sits a third design that’s easy to miss because it hides inside the single-device count: one adaptive memristor paired with one fixed resistor — call it 1M1R. The resistor isn’t a selector and isn’t storage. It’s a reference. Wire the memristor against it — a voltage divider, or an excitatory resistor path summed against an inhibitory memristor path at an op-amp — and the output is the difference between an adaptive conductance and a fixed one. That difference can go negative. One memristor, and you have a signed weight.

The clearest instance in this corpus is the Los Alamos oscillator network (Acker/Barrows 2026): each synapse is a fixed resistor on the excitatory path in parallel with one memristor on the inhibitory path, and the net weight crosses zero into negative as the memristor conductance rises — signed, locally learned, one adaptive device.

But 1M1R is not the pair. The reference resistor is fixed, so only one arm of the difference adapts, and that is what costs you the AHaH rule. In a 2-1 pair both devices adapt under the same drive, and the divider decides how far each one moves: the arm carrying the larger share of the voltage moves further. Drive the pair one way and it self-equalizes toward zero, which is the anti-Hebbian direction. Drive it the other way and it diverges toward a rail, which is the Hebbian direction. Chapter 4b has the instruction set that does both. A fixed resistor never moves, so neither dynamic is available — the memristor walks against a reference that stays put.

You lose the common-mode cancellation too. When both halves of a real pair drift with temperature or age, the difference survives. A lone memristor read against a fixed resistor drifts against a reference that doesn’t, so the zero wanders. And the usable swing is one-sided. The pair spends a second device and gets all three back: two-sided range, drift that cancels, and two adaptive arms the drive polarity can equalize or diverge. 1M1R is the middle case, more than a lone unsigned device and less than the pair.

How common is it? Harder to say than it should be. Almost none of the single-device papers state their sign scheme in the abstract at all: the mechanism is a methods-and-figures detail, not a headline. So I pulled the open-access full texts and read the circuits directly. Of the twenty-odd I could get, exactly one was built as a per-synapse 1M1R — the Los Alamos oscillator network above — while the shared reference column was the usual way single-device arrays bought a sign.

More telling: the mis-filing runs in both directions. Several papers filed as single-device turned out to be two-memristor pairs (W = G⁺ − G⁻) the abstract never mentioned — and fourteen papers filed as pairs turned out, on a full read, to be one memristor against a reference. The per-synapse fixed resistor is genuinely rare. A slice of what looks like single-device is a pair wearing a crossbar’s clothes, and vice versa. Abstracts don’t show wiring. Full text does.

(A terminology note: “1M1R” also appears in crossbar papers meaning a resistor placed in series with each memristor to tame sneak paths or limit current — a ballast, not a reference. Different circuit, different job. Here 1M1R means the memristor-against-a-reference synapse that produces a sign.)

The last route is to give up on negative weights entirely and hold the whole network non-negative. Eslami et al. (2024) is a clean example: a two-layer image classifier with one memristor per synapse, every weight clamped to a positive conductance, no reference at all. It’s the one path that genuinely doesn’t subtract — and it pays for that by shrinking the weight space to positives only. What earns it a mention here is the hardware: they built it on Knowm’s own commercial M-SDC memristors, an outside group running a single-device network on our parts.

A quick caveat on the counts: this single-device sweep and the 233-paper pair sweep were harvested by different query families, so the two numbers aren’t a clean market share of one road against the other — each is a floor within its own literature. What the 131 does settle is that the lone device is a large, live approach, not a baseline nobody uses.

Two devices — the pair. Two memristors, one weight, read as the difference of the two conductances, so the weight swings positive and negative around zero. This is the kT-synapse, and it’s the default the field converged on. The drawing below is its 2-1 form — the two devices in series between opposite rails, read at the midpoint:

Many devices — the multi-memristive synapse. You don’t have to stop at two. Gang several memristors onto each side of the shared node and the weight becomes a difference of sums — which averages out the device-to-device variability memristors are notorious for, and widens the dynamic range. The four-memristor bridge synapse is the classic small version of this.

So when the corpus says “two or more devices per weight,” here’s the actual split across the 233 in-scope papers:

The two-device pair is the clear default — 130 of the 233. Three-or-more-device designs (the bridge, or ganged multi-memristive synapses) are the minority route, and a chunk of papers are confirmed multi-device without ever stating the exact count. What none of them do is make one device carry a signed weight on its own — but, as above, that’s not because the door is closed. The single-device road is real and well-travelled — 131 papers whose designs get their sign from a shared reference instead of a partner. This section counts the two-device weights. The single-device road got its own survey a few paragraphs up.

How the two devices are wired#

Two devices per weight still leaves a question the field answers several ways: how are the two actually connected? This is the arrangement you’d draw on a whiteboard — and it’s where the physics does something clean. The dividing line worth caring about: does the difference form at a shared electrode (a series path through a common node, by Kirchhoff), or does a downstream circuit do the subtracting (a subtractor, a sense amp, a dual ADC)? 144 of the 233 papers show their wiring clearly enough to call:

Three arrangements do essentially all the work, and they deserve names. The clearest naming I know is by electrode count, inputs–outputs — the convention we’ve used at Knowm since the early patents — and it covers the whole design space in three labels: 1-2, 2-1, and 2-2. If you’re choosing a synapse circuit, this is the actual decision you’re making, so here’s each one with its trade-off:

• 1-2 — parallel two-column (G⁺/G⁻). One input electrode, two outputs: the pair splits onto a differential output pair, and the two currents are subtracted downstream — an op-amp, a sense amp, or two ADC reads. This is the crossbar mainstream and the most common thing I found, for a practical reason: it drops straight into a standard 1T1R foundry array, and the readout periphery you were building anyway does the subtraction. The cost is that periphery — the subtractor or dual conversion is real per-column hardware, and the sign never exists until the currents reach it.
• 2-1 — series shared-node. Two input electrodes, one output: the devices form one series path through a common node, and the weight is read at that node, as a voltage divider or a Kirchhoff current difference. No subtractor anywhere — the electrode does the math, and the read is passive. That’s why it pairs naturally with local learning and minimal periphery. What differs is the number you get back: the node returns a ratio bounded in [−1, 1], so a lane normalizes by activity on its own instead of handing you a raw accumulated current. This is the configuration Knowm has published on most (teal), and 29 papers build it.
• 2-2 — the bridge. Two inputs, two outputs — fully differential on both sides, which the Wheatstone-style memristor-bridge synapse builds out with four devices and a differential amplifier across the middle. The best common-mode rejection of the three and a clean zero, at the price of doubling the devices and spending an amplifier per synapse.

Between them, these three cover 137 of the 144 papers whose circuit is legible. And the practical way to choose is to ask where you want the subtraction to happen: in periphery you already have (1-2), at the electrode itself (2-1), or across an amplifier (2-2). Everything else in the corpus is a variation on one of the three.

The three are also closer to each other than the labels suggest. Mind the polarity and a 1-2 becomes a 2-1 by tying the two output terminals together. The two branches then share one node, and you can read that node two ways: as the normalized voltage the divider settles to, or as the integration current through the joined terminals. One wiring change, both readouts available.

Note: The 85 “not determinable” are papers whose text names a pair but never shows the wiring clearly enough to classify without redrawing the schematic — the floor on what this kind of survey can read. And four papers build two memristors in series but read the whole stack destructively — the complementary-resistive-switch memory/logic line — the same series structure without the shared-node read.

Who builds the 2-1#

The 2-1 — the shared-node series path — deserves its own roll call, because at abstract level it looked like a rounding error, and on a full read it turns out to include some of the most-cited hardware in the field. If you’re considering the configuration, these are the papers to read.

The lead exhibit is Li 2017 in Nature Electronics — the UMass/HP analog signal-and-image-processing crossbar, ~1,270 citations, one of the more influential memristor-computing papers. The chip drives two neighbouring rows with equal and opposite voltages, and the pair’s net current forms on the shared column wire — by Kirchhoff, at the electrode, before any periphery sees it. That is electrically the 2-1 read. Wang 2018 (Nature Electronics, fully memristive neural network, ~1,100 citations) uses the adjacent-row version of the same wiring.

From there the roster spans every flavor of the structure:

• Research synapses with learning. Merkel builds the 2-1 divider synapse (2014, 2017). Chakma and Rose build the twin-memristor 2-1 mrDANNA cell (two papers, 2017). Adnan builds an opposite-polarity STDP twin (2018), Vo a “two successive memristors” half-bridge (2018), Zheng a summing-node synapse (2018), and Ji a shared-node pair that reads I = (G_A − G_B)·V at the junction (2022). Abbood (2021) runs the AHaH rules themselves on two same-polarity memristors in series, read as a divider at y between V and −V — an outside group reproducing the 2-1 as we build it.
• Production-style CIM macros — the XNOR-RRAM line (Yin 2019, two papers): two 1T1R cells on differential wordlines, difference embedded at the shared bitline; Wang 2021’s 2T2R voltage-division macro (V_CSL read between the two resistors); Chen 2023’s 1T2R1C divider cell; Zhang 2024’s same-source-line 2T2R (“direct subtraction in the current domain”); He 2025’s shared-source-line kernel, which explicitly rejects the downstream-subtraction layout.
• Beyond synapses entirely. Singh 2022 wires a common select line from the top electrode of one RRAM to the bottom electrode of the other for in-memory logic. Yang 2022 builds 2T2R logic and a 512 Kb PUF on the same divider. Park 2025 stacks two full crossbar layers into a 3D array — bottom electrode, memristor, shared middle electrode, memristor, top electrode — and reads the current difference at the middle electrode. That last one is the 2-1 in stacked cross-section, fabricated as 2 × 32 × 32 hardware, used as a security primitive.

Twenty-nine papers, from Nature Electronics flagships to 28 nm production macros to 3D stacks, all reading a difference at a shared electrode. Two caveats: a couple of the CIM macros (Wang 2021, Chen 2023) use the wiring for pre-programmed inference — the structure without the learning — and the 29 is a floor, because wiring shows up in figures and 85 in-scope papers never show theirs. The takeaway for a designer: the shared-node read isn’t a fringe choice. It’s in the field’s best journals, its production test chips, and its security hardware, and the roster above spans every application you might want a worked example for.

Why the pair — the engineering case#

1. Sign for free — nothing bolted on. Two devices between opposite rails, read at the midpoint: the weight is the normalized difference (Ga − Gb)/(Ga + Gb), and it swings both ways with no extra hardware. The single-device road has to buy its sign elsewhere — a shared reference column to subtract against (an extra device per column, plus the wiring to route it), or a hard non-negative constraint that throws away half the weight space. The pair pays for sign once, in the topology itself, and never again.

2. The pair is the learning unit. Most of the field uses it as storage only. Both devices adapt under the drive that reads them, and AHaH plasticity emerges from that. The most useful case is anti-Hebbian learning from a forward read: the node self-calibrates as you read it, adapting around variation in the CMOS and in the memristors themselves.

3. Access transistors are area you don’t have to spend. The mainstream reflex is 2T2R — a select transistor per device — because it buys write-precision and density for a large, pre-programmed inference array. But if the array is small and the point is to learn on it in place, that transistor is overhead. Keep the crossbar small enough that sneak paths stay manageable and you can read and write one device at a time with no selector at every junction — the “unit crossbar” Alex lays out in The Neural Lane. It’s why, in this very survey, the selector-free designs cluster with in-situ learning rather than with the big inference macros. The learning rule itself is indifferent: AHaH runs the same with a selector at every junction or none at all. Dropping the transistor is an area decision, and a small crossbar is what makes it available.

4. Variability averages out when you gang the pair. Memristors are noisy device-to-device — the standard complaint. A complaint that depends on what you are building. The whole field of thermodynamic computing treats noise as a resource rather than a defect: it is where the random samples come from, and a device that fluctuates is a device that can explore. One person’s garbage is another’s treasure. Stack several devices on each side of the shared node and the weight becomes a difference of sums. The per-device scatter averages down and the dynamic range goes up, by the same divider physics, for free. The kT-synapse is the n = 1 case. The pair doesn’t fight variability, it dilutes it.

5. The read is passive. The shared-node divider needs no op-amp per synapse and no per-column ADC to do the subtraction — the node just settles where the more-conductive side pulls it, and by Kirchhoff a whole lane of selected pairs settles to their activity-normalized average, bounded in [−1, 1] no matter how many you switch on. The physics does the math. Most of the field reads the pair with a subtractor or a bridge-plus-amplifier — those work, but that’s circuitry you’re adding back.

Add it up and the pattern holds: the pair gets sign, locality, and variability-averaging out of the same two devices, and asks for less periphery than the alternatives to do it. That’s what kT-RAM is built on.

A short history of the pair#

The idea is older than you’d guess from a keyword search, because it predates the word “memristor” itself:

Everything on that timeline is readable today — every label on it links to its source.

Notice the timeline splits around 2008, when HP’s paper put Chua’s 1971 term “memristor” into common use. The earliest filings sit on the far side of that line and say “connection” and “meta-stable switch” instead — which is why a keyword search of the literature never surfaces them. And the device physics that made real pairs buildable is its own lineage again, running through Kris Campbell’s lab at Boise State.

The useful takeaway: the pair kept being re-derived from different starting problems, which is the strongest kind of evidence that it’s the natural primitive. That’s the next section.

Everyone agrees on the pair. Nobody agrees on how to read it#

Once you accept “two devices per weight,” you still have to decide how to turn that pair into a number. The field has split several ways:

The shared-node read — the one we’ve published on — is in there at thirty papers: the second-most-common stated read, behind the downstream subtractor/sense-amp.

The downstream subtraction is the mainstream, and it dominates precisely where the mainstream builds: large pre-programmed inference arrays with per-column ADCs, where the periphery is already there to do the subtracting. The shared-node read shows up where the periphery is the thing being minimized — the divider macros, the stacked cells, the learning synapses. Whether one is better is a separate question this corpus cannot answer — it counts papers, it doesn’t run benchmarks.

Same story on array topology:

2T2R dominates by a wide margin — and here’s where it gets interesting. Only nine papers go selector-free. But when you actually read them, they aren’t a random scatter. They sort into two camps, and the split tells you why selector-free is uncommon — here are five that show it clearly:

• Self-rectifying device tricks — Siemon 2014 (a complementary-resistive-switch crossbar adder) and Kim 2021 (sodium-doped self-rectifying titania memristors). These drop the transistor by making the device itself suppress sneak paths. It’s a materials-and-cell solution to the same problem the transistor solves.
• Small-array in-situ learners — Nair 2017 (“a differential memristive synapse circuit for on-line learning”), Payvand 2019 (error-triggered local three-factor learning), and Martemucci 2025 (a ferroelectric-memristor cell for both training and inference, in Nature Electronics). These go selector-free for the reason that drew us to explore it: when the array is small and the point is to learn on it in place, the per-device access transistor is area you don’t want to spend.

The field mostly reaches for 2T2R when it’s building a large, pre-programmed inference crossbar, where the transistor buys density and write-precision and the weights never change after training. Selector-free clusters around learning systems instead. One clarification, so the design point isn’t misread as a limitation: selector-free doesn’t mean learning-only. The passive divider read that drives learning is the same read that serves inference, so the same array does both — learn in place and then infer on the spot, or skip the learning and program the weights for inference alone. The asymmetry runs the other way: a 2T2R inference array can’t learn in place without adding the machinery back. So the “rare choice” isn’t a disadvantage so much as a different design point: the mainstream optimized its cell for inference at scale, and a handful of groups — independently, again — kept the cell simple enough to do both.

Where the learning happens#

One axis remains, and for anyone designing a system it’s the one that matters most: are the weights programmed from outside, or does the array update itself?

In most of this literature the pair is storage. A network is trained somewhere else, the weights are decomposed into G⁺ and G⁻, and the devices get programmed to hold them. The pair is an implementation detail for representing a signed number.

On-chip splits again, and the split is about what the hardware hands you. Most on-chip designs put one training algorithm into silicon. Yi et al. (Nature Electronics 2022) run activity-difference training on differential arrays; Oh et al. (Micromachines 2023) run equilibrium propagation on single-device crossbars. Both are network-level schemes — a free pass, a second pass nudged toward the target, a relaxation to equilibrium before any weight moves. The array is a thing being trained by a fixed procedure.

kT-RAM hands you an instruction set instead. Each instruction applied to a node produces an adaptive response. Those are primitives, not a training algorithm. Chapter 6 composes three of them into the delta rule — read the lane, then reward, punish, or relax according to the label — and gets a supervised linear classifier out of it. Other routines from the same instructions give you logic gates, encoders, and samplers. The instructions act on one node at a time, and a global learning system is something you compose from them.

So the question to ask about an on-chip design isn’t whether it learns locally. It’s whether the hardware fixes the learning algorithm or leaves it open — and, once you have a rule in mind, how many passes over the network a single weight update costs you.

The pair is the primitive#

Step back and look at what the corpus shows across its whole span, because it’s remarkable:

That’s not one community’s habit. RRAM groups, phase-change groups, ferroelectric groups, spintronics groups, and generic circuit-theory groups — more than two hundred in all, publishing in Nature and Science and everywhere in between — arrived at the same structural answer: one weight, two devices, read the difference. The physics pushes everyone the same way: conductance can’t go negative, useful weights carry a sign, and the pair is the clean way out.

And it isn’t a thought experiment the field keeps repeating in SPICE — most of these are real chips:

Conclusion#

If you came here wondering how to build a memristive synapse, the 374 papers boil down to this. A lone memristor can hold a weight, but its conductance is positive-only, and the most useful weights carry a sign. A sign takes a difference. So spend two devices per weight, and pick the configuration by where you want the subtraction to happen: in the periphery you already have (1-2), at the shared electrode (2-1), or across an amplifier (2-2). Expect the wiring details to live in figures rather than abstracts.

And know that whichever you pick, you are in good company. More than two hundred groups, starting from different problems in different decades, converged on the same primitive: one weight, two devices, read as a difference. We placed our bet on the 2-1 in 2002, and this corpus reads like the field slowly agreeing — whatever each group calls it.

How the corpus was built#

Six stages, everything after the harvest running offline:

1. Harvest — a Google Scholar sweep through the SerpAPI REST endpoint: 17 query families, as_ylo=2010, every page cached.
2. Gate — dedup by Scholar cluster_id, then a relevance gate that is a conjunction. A paper has to carry both a device term (memristor, rram, pcm, fefet, …) and a two-device-per-weight term (differential pair, 2T2R, signed weight, conductance difference, …). “Differential pair” alone is a 60-year-old amplifier; “2T2R” alone is a memory layout. Only the pair of signals means what we want.
3. Enrich — real abstracts from Crossref, then Unpaywall, then Semantic Scholar; open-access PDFs pulled and their full text scanned.
4. Classify — a relevance tier and seven axes per paper: devices-per-weight, arrangement, read method, selector, technology, learning locus, evidence.
5. Citation check — each paper’s real bibliography from OpenAlex, intersected with a 26-work Knowm seed set.
6. Tally — the per-paper records and the summary statistics every number above is drawn from.

The evidence follows a strict ladder — a human decision beats PDF full text, which beats an LLM abstract read, which beats a title/abstract regex. A weaker signal never overrides a stronger one, and nothing is ever marked “excluded” on the strength of a missing mention. The final wiring numbers come from the top of that ladder: a 121-PDF full-text re-read, with each verdict carrying an evidence quote from the paper itself, and one boundary rule — where does the difference form, at a shared electrode or in a downstream circuit — applied uniformly. The result is that the counts can only be too low, never too high: a paper enters the count only on positive evidence from its own text. That’s why 233 is a floor.

Further resources#

• Chapter 5b: Maximizing Noise Margin — what the pair is for: the AHaH rule, and why growing the weight margin is the same thing as building the read’s noise barrier.
• AHaH Computing—From Metastable Switches to Attractors to Machine Learning (Nugent & Molter, PLoS ONE 2014) — the foundational paper the citation check is anchored on.
• memristor-models-4-all — the device models, if you want to simulate the pair yourself.
• The Memristor Discovery board in the video above — the open-source hardware for driving a real SDC pair on the bench.