Beyond von Neumann: Eight Approaches to AI's Power Problem

What I set out to check#

New chips, physical mechanisms, and startups regularly promise machine learning at a fraction of a GPU’s energy use. These announcements rarely answer two basic questions: how does the approach work, and what has it demonstrated in hardware rather than in simulation or theory?

This article examines eight physical substrates for machine-learning hardware. For each, I describe the operating principle, the central claim, the strongest hardware demonstration I found, and the principal advantages and limitations. The assessment draws on a corpus of about 1,300 papers. I then compare the substrates across inference, learning, and deployment. The final section presents my case for the approach I work on: a combination of three substrates rather than a ninth one.

The scope is the substrate: the physical system that performs the computation. Algorithms are outside it. I include hardware intended to accelerate mainstream machine-learning workloads, such as vision and large language models, and exclude the separate medical and neuroscience literature.

A disclosure, also noted in the memristor taxonomy: I work at Knowm. Knowm’s kT-RAM combines three of the eight substrates, so it does not appear on the ring. I assess it by the same standards. It ranks near the bottom in publication volume, independent replication, and demonstrated scale. The standard throughout is facts, not flattering.

Why leave digital at all?#

A GPU spends much of its energy moving numbers rather than multiplying them. Weights travel from DRAM across a bus to the compute units. This separation of memory and processing defines the von Neumann architecture, and the connecting wires consume much of the power. Moving a bit requires charging a wire. The energy is approximately CV², and capacitance increases with wire length. Every weight fetched for a multiply-accumulate operation incurs this cost; modern models fetch billions of weights.

Memory–processor separation imposes a data-movement cost whether a system is learning or only performing inference. Adaptation creates an additional problem: the system must repeatedly modify its internal state. On a von Neumann machine, each update requires reading a state variable from memory, computing its new value, and writing it back.

In a 2014 PLoS ONE paper, Alex Nugent and I wrote that every adaptation event “must necessarily reduce to memory–processor communication as the state variables are modified.” Alex later called the resulting scaling cost the adaptive power problem. It is not simply the separation of memory and processing. It is the repeated communication required to update many state variables. Faster computation does not remove that cost; the energy required for learning grows with the number of variables being adapted and how often they are updated.

Placing memory and processing together addresses both problems: it reduces data movement during inference and allows state to change where it is stored during learning. Biology provided the model for this design. As we wrote on knowm.org, “Nature does not separate memory and processing.”

Moore’s law could not solve the underlying problem because smaller transistors do not eliminate the memory round trip. Dennard scaling, which reduced power with each generation, ended around 2006 even as transistor density continued to rise. Subsequent gains have depended increasingly on architecture. At the 2017 Energy Consequences of Information conference, researchers from IBM and several universities broadly agreed that memory and computation would need to converge and that substrate physics again mattered. Power is now a central constraint on AI hardware.

The adaptive power problem applies specifically to learning. The broader data-movement problem also applies to inference because every fixed weight must still be fetched for use. Most AI energy use in 2026 comes from inference and from the datacenter training runs that produce the models. Several substrates below address inference but not adaptation, so the later evaluation treats them separately.

The eight substrates are analog in-memory arrays, spiking neuromorphic chips, photonic meshes, superconducting devices, spintronic devices, thermodynamic and probabilistic samplers, quantum processors, and DNA chemistry. Nearly all target the same three problems: energy use, the memory wall, and data movement.

The eight substrates#

The sequence runs from approaches closest to conventional silicon to those based on more unusual physics. The cited examples are the strongest hardware demonstrations in the readable corpus, although they are not always the most famous results; some papers were inaccessible behind paywalls.

The list includes only physical substrates. Reservoir computing is a technique that combines a fixed nonlinear system with a trained linear readout. It has been implemented in light, magnets, memristors, and water; its strongest chips are photonic, so I discuss it under photonics. Physical learning, including equilibrium propagation, is a training method that can operate on several substrates. It returns later in the article. kT-RAM combines three listed substrates and appears in the final sections.

In-memory / ReRAM#

In-memory computing places multiplication beside memory. Conductances programmed into a resistive crossbar perform a matrix-vector multiplication in one analog step through Ohm’s and Kirchhoff’s laws. The weights never cross a bus during inference. Wan et al.’s NeuRRAM (2022) is a fabricated RRAM compute-in-memory chip tested on MNIST and CIFAR. However, several widely cited architectures, including ISAAC, PUMA, and NeuroSim, exist only in simulation. In-memory devices can update conductances in place, but the strongest fabricated benchmark chips generally load weights trained elsewhere and perform inference only.

Pros

• One analog step performs an entire matrix-vector multiplication without moving weights.
• More chips have been fabricated than for any other analog substrate, and commercial parts exist.
• Dense arrays can be added to the back-end metal layers of conventional CMOS.

Cons

• Device variability, drift, and limited precision reduce accuracy. ADCs and DACs consume much of the saved energy.
• Most benchmarked chips use weights trained on a GPU and then written to the array.

We have a solution designed to overcome these issues, and we are disclosing it over the course of our blog series, beginning with Chapter 1, “Assimilation”.

Neuromorphic / spiking#

Neuromorphic hardware uses event-driven neurons that communicate through spikes and keeps synaptic state near the computation. It is the closest silicon analog of a brain’s wiring. IBM’s TrueNorth (2014) placed one million neurons on a 28 nm die. Intel’s Loihi (2018) added programmable on-chip learning, and IBM’s NorthPole (2023) integrated memory with compute and improved inference efficiency. Yet “neuromorphic” covers a broad range of work, much of it limited to single-device synapse demonstrations. Commercial activity has also contracted: Rain AI, a prominent memristor-neuromorphic startup, wound down in 2026 after OpenAI declined to buy the company and acquired only its patents.

Pros

• Computation occurs only when a spike arrives, so idle circuits consume little power.
• Many chips have been fabricated, and parts from BrainChip, Syntiant, and SynSense ship in edge devices.
• Some chips learn on-chip (Loihi).
• The field has relatively mature terminology and tools.

Cons

• Spiking networks trail dense transformers on mainstream tasks, and each chip requires a separate toolchain.
• Most implementations remain digital CMOS and do not change the underlying device physics.
• Learning usually remains off-chip; commercial parts are inference engines.
• No neuromorphic chip competes with GPUs in datacenters.

Photonic#

Photonic systems encode numbers as optical amplitudes and pass them through interferometer meshes or phase-change arrays. The resulting matrix multiplication occurs at propagation speed with little switching energy. Feldmann et al.’s fabricated integrated photonic tensor core (2021) ran convolutions and MNIST inference. Its weights were trained elsewhere and then set in the optical hardware, making it an inference engine rather than a learning system.

Photonics also provides the strongest reservoir-computing hardware. Nakajima et al. demonstrated a photonic reservoir (2021) on MNIST and chaotic time series. In September 2026, a chip-scale optical parametric oscillator reservoir on thin-film lithium niobate operated near 10 GHz and exceeded 93% on three benchmarks. The reservoir is fixed; only its linear readout is trained conventionally.

Pros

• Multiplication occurs at light-propagation speed with little switching energy.
• Enormous bandwidth: many wavelengths through one waveguide.
• Fabricated tensor cores exist, and photonic computing is the best-funded substrate.

Cons

• Weights are trained elsewhere and set electronically, limiting the hardware to inference.
• Lasers, modulators, detectors, and ADCs dominate system energy and offset much of the optical advantage.
• Optics cannot shrink below the wavelength of light, so density is poor.
• Several leading companies have shifted from computation to interconnects.

Superconducting#

Josephson junctions and single-flux-quantum logic switch in picoseconds with femtojoules of energy, but require temperatures near four kelvin. Schneider et al. built magnetic Josephson-junction artificial synapses (2018) and measured updates at a few attojoules per pulse. This exceptional device-level efficiency excludes the energy required for cryogenic cooling.

Pros

• Josephson junctions switch in picoseconds at femtojoule-to-attojoule energies.
• Naturally spiking, with synaptic updates measured at a few attojoules.
• The substrate uses fundamentally different physics from CMOS.

Cons

• Operation near four kelvin requires a refrigerator whose power consumption exceeds that of the chip.
• Low integration density and no dense memory technology to pair with it.
• Demonstrations remain small; no substantial machine-learning system exists.

Spintronic#

Spintronic hardware uses electron spin rather than charge through devices such as magnetic tunnel junctions, nano-oscillators, domain walls, and skyrmions. Torrejon et al.’s nanoscale spintronic oscillator (2017) performed spoken-digit recognition with a single magnetic tunnel junction. This experiment established the principle, but scaling beyond one device and a small task remains unresolved.

Pros

• Devices are nonvolatile, fast, have very high endurance, and are already manufactured at scale as MRAM.
• Built-in stochasticity is a resource for oscillators and probabilistic bits.
• Recognition has been demonstrated experimentally in a single device.

Cons

• Demonstrations are limited to single devices or small networks.
• Small on-off ratios mean weak signals and expensive readout.
• Vendors sell spintronic memory, not AI accelerators.

Thermodynamic / probabilistic#

Thermodynamic and probabilistic systems use noise as a computational resource. Probabilistic bits, or p-bits, fluctuate between 0 and 1. Networks of them sample probability distributions or relax toward the ground state of an energy function. Thermodynamic computing applies the same principle through hardware implementations of Langevin-like dynamics for sampling and energy-based models.

Borders et al. demonstrated integer factorization with stochastic magnetic tunnel junctions (2019). Their eight physical MTJ p-bits factored integers up to 945. In 2026, a CEA-Leti team built a room-temperature hybrid memristor-crossbar and stochastic-MTJ Ising machine that anneals itself. Mohseni et al.’s review of Ising machines (2022) surveys the broader hardware family. Most such systems solve combinatorial-optimization problems rather than learn models.

The thermodynamic framing is recent and prominent. Coles et al. present the case in “Thermodynamic AI and the fluctuation frontier” (2023), and startups including Extropic and Normal Computing are well funded. The literature, however, consists mainly of theory, proposed algorithms, and simulation. The only fabricated demonstration published under the thermodynamic-computing label is Normal Computing’s stochastic processing unit (Melanson et al., 2025), an eight-cell RLC prototype tested on probabilistic-AI primitives.

Announcements have since moved ahead of published measurements. In September 2026, Extropic announced that its Z1 chip—269,000 p-bits operating below one watt—had taped out, with early access planned for 2027. Normal Computing also described a taped-out digital thermodynamic chip. Neither announcement included hardware measurements. Excluding photonic papers captured by broad searches, the experimental record consists of Normal’s prototype and the p-bit systems above. This substrate has the largest gap between its stated potential and demonstrated hardware. Knowm’s Thermodynamic RAM uses the same term; I explain the relationship later.

Pros

• Hardware samples distributions and relaxes toward low-energy states natively, with potentially low energy use for sampling and linear-algebra primitives.
• Room-temperature systems have been fabricated: eight MTJ p-bits in 2019, an eight-cell RLC sampler in 2025, and a hybrid memristor-MTJ annealer in 2026.
• The approach is well suited to optimization and energy-based models. It is well funded, and early access to a taped-out chip is planned for 2027.

Cons

• Most systems address optimization and sampling. Their application to mainstream machine learning remains narrow, and no complete model has been measured.
• Connectivity and scale are hard; big problems must be cut into pieces.
• Experimental evidence remains limited and trails public announcements.

Our new CHILL ZEN work applies kT-RAM to Fashion-MNIST image generation and benchmarks it against Extropic’s Denoising Thermodynamic Model (DTM) on image quality, stochastic operation count, and projected hardware energy.

Quantum#

Quantum machine learning uses superposition, entanglement, and variational circuits. Most work runs in simulation or on shared cloud quantum processors. Benedetti et al. trained a generative model on an ion-trap system (2019). In 2026, a Cleveland Clinic and IBM team trained a 46-qubit quantum convolutional network on an IBM Quantum System One and reported a modest accuracy advantage over a parameter-matched classical CNN. Real-hardware results therefore exist, but remain rare and small. The field also reports fidelity and circuit depth rather than energy per operation, which complicates comparison.

Pros

• An exponential state space for compatible problems.
• Real-hardware quantum machine learning exists, including a 46-qubit trained network in 2026.
• Funding is substantial, and real machines are available through cloud services.

Cons

• Decoherence and error-correction requirements limit useful qubit counts.
• No energy advantage has been shown, and the field does not measure itself in joules.
• Systems are cryogenic, depend on classical optimizers, and have shown no speed advantage on a mainstream learning task.

Molecular / DNA#

Molecular computing uses DNA hybridization and strand-displacement reactions to implement logic gates and neural networks. Liu et al.’s DNA neural network (2025) classified images in a wet lab. The experiment worked, but was slow, effectively single-use, and depended on weights set by the researchers. Its potential to accelerate mainstream machine learning remains uncertain.

Pros

• The chemistry supports massive parallelism, and a wet-lab neural network has classified images.
• Energy per operation is potentially very low.
• Unmatched storage density.

Cons

• Computation takes hours, is effectively single-use, and uses externally set weights.
• Does not integrate with electronics.
• Commercial efforts focus on storage rather than machine learning.

Why have they not beaten the GPU?#

DARPA funded IBM’s TrueNorth more than a decade ago, and some of these physical principles are much older. Yet none has displaced the GPU.

Several substrates have been commercialized, but mainly as low-power inference chips at the edge. This market assessment draws on a companion company census rather than the paper corpus. Syntiant has shipped tens of millions of parts and filed to go public. BrainChip is publicly listed. Always-on voice and sensor chips from Witmem and Femtosense appear in products, including hearing aids. No alternative has entered the datacenter at sufficient scale to compete with GPUs.

To do so, a substrate must meet four market requirements:

1. A tenfold advantage in a metric buyers value. Datacenter operators prioritize throughput per dollar and training time, not energy alone. Energy efficiency matters most at the edge, where the commercial successes have occurred.
2. A software ecosystem. The GPU’s advantage includes CUDA, cuDNN, PyTorch, and a large community trained to use them. Developers will not port models without a substantial performance gain, but that gain is difficult to establish without software support. TrueNorth required users to convert networks to a spiking representation and adopt a separate toolchain; few did.
3. Manufacturability. Digital CMOS is reproducible at scale. Emerging substrates face both technical and infrastructure barriers. Some memristors, photonic devices, and spintronic devices still struggle with variability, drift, and yield. Knowm’s SDC memristors are viable, but production at scale requires a dedicated back-end-of-line (BEOL) facility. The cost of building or accessing that infrastructure creates a high barrier to entry for a small company. Most emerging-device memristor startups in the company census remain pre-product, have gone quiet, have shifted to software, or are for sale. Recent investment in “in-memory” computing has favored near-memory digital designs on 3D DRAM. Several funding rounds exceeded $100 million in August and September 2026, while analog ReRAM arrays attracted less capital.
4. Timing. A chip takes three to five years to develop. During that period, GPUs advance by several generations and dominant workloads can change. Neuromorphic chips designed for spiking convolutional networks arrived as the field shifted toward transformers, which rely on dense matrix multiplication—a strength of GPUs and a weakness of spiking hardware.

The photonic sector illustrates these constraints. Its companies raised more capital than those in any other listed field, but many survivors shifted from computation to interconnects. Rather than replace GPUs, they now connect them. The substrates with the largest theoretical advantages often face the greatest software, manufacturing, and timing barriers. Commercial products have succeeded by targeting narrow edge-inference applications with digital or nearly digital hardware.

What the comparison actually shows#

Taken together, the eight approaches expose a stack of costs rather than a single contest: moving stored state, computing with it, changing it, and drawing from it when the answer should be stochastic rather than fixed. Their categories overlap because those operations sit at different layers of a machine.

Moving the multiply is only the first layer#

In-memory arrays, photonic meshes, and neuromorphic chips can all reduce the data movement of inference. That matters even when the weights never change. But a weight used locally and a weight changed locally are different achievements. If training still reads the state into another processor, calculates an update, and writes it back, the adaptive power problem remains.

The update must reach the state without a round trip#

“In-memory,” “neuromorphic,” and “thermodynamic” do not tell us where learning occurs. Some resistive arrays update conductances in place; Loihi provides a programmable local learning engine; many other systems in the same categories load weights trained elsewhere. The useful question is physical: does the update act on the stored state where it lives, using signals already available there, or does a conventional computer remain in the loop?

Useful noise must act on the learned state#

Thermodynamic hardware contributes a third operation: sampling. A separate random-number generator can make any digital model stochastic, but then the randomness, the learned state, and the computation occupy different machinery. The more interesting target is a learned physical state that can be read quietly for a decision or read at a controlled temperature for a sample.

The comparison therefore points to a more demanding object than an efficient accelerator: one room-temperature, addressable physical primitive that stores a signed state, computes with it, changes it locally, and exposes controllable stochasticity. Most systems distribute those functions across memory, arithmetic, update logic, and random-number generation. kT-RAM was designed to make them operating modes of the same circuit.

The next layer: kT-RAM is three of the eight at once#

kT-RAM is not three accelerators bolted together. It is one physical stack viewed from three directions. The same conductances serve as memory, operands, learning state, and the bias of a random sample.

The kT-bit stores a weight and its history#

Knowm invented and patented the differential-pair memristor synapse architecture at the base of kT-RAM. The kT-bit stores one signed weight in two conductances:

$$w = \frac{G_a-G_b}{G_a+G_b}, \qquad m = G_a+G_b.$$

The balance $w$ is the value. The total conductance $m$ is the evidence behind it: it sets the weight’s inertia, its effective learning rate, and how much its physical read fluctuates. A conventional scalar stores the value and discards that second degree of freedom. Here confidence, annealing, and state are properties of the same pair. The kT-bit, kT-RAM architecture, and full technology stack are covered by Knowm’s intellectual property portfolio.

The neural lane makes memory access the computation#

A neural lane couples many addressable kT-bits to one shared readout. An Activation Address Tuple (AAT) selects one pair from each address space, and the physical node returns

$$y = \frac{\sum_i (G_{a,i}-G_{b,i})}{\sum_i (G_{a,i}+G_{b,i})} = \frac{\sum_i m_i w_i}{\sum_i m_i}.$$

Ohm’s and Kirchhoff’s laws perform the accumulation, normalization, and evidence weighting where the conductances are stored. No weight is fetched into a separate arithmetic unit. The tuple is also the physical selection pattern, so there is no translation table between the data representation and the synapses. Chapter 7’s AAT codecs extend that interface from sparse symbols to vectors and images while keeping computation in address space.

The instruction set makes the same state learn and sample#

A read instruction floats the shared node and observes $y$. A feedback instruction clamps that node and drives the selected conductances. Different sequences of read and feedback instructions produce different learning rules. Chapter 5b shows one that concentrates updates on uncertain decisions and reduces them as the margin grows. The update is delivered by voltage to the devices that hold the weight; it does not make a round trip through a separate optimizer and weight store.

The readout supplies the thermodynamic mode. Low-noise reads use the lane for inference or repair. Deliberately noisy reads turn the same learned scores into samples. A single pair carries device noise directly; across a large pool that noise averages down, so CHILL ZEN uses adjustable comparator noise as the temperature control. The learned conductances still set the distribution; the comparator controls how sharply it is sampled. The result is a lane that can learn locally, answer deterministically, or generate stochastically without moving its weights between three machines.

That is the three-way overlap: in-memory, because conductance is both storage and operand; neuromorphic, because local physical feedback changes the selected synapses; and thermodynamic, because a controlled noisy read samples the state those synapses learned. Chapters 5 and 6 run the same lane as logic, a classifier, and a sampler. CHILL ZEN composes the lane and AAT codec into an image generator. The workload changes; the substrate does not.

The full system has not yet been demonstrated at scale. Its literature is much smaller than the neuromorphic or photonic literature, independent replication is uncommon, and the published machine-learning results used an emulator rather than a physical crossbar. About 40% of the Knowm papers in the corpus report built hardware, and kT-RAM has the largest number of on-substrate-learning papers in the corpus, but there is no end-to-end machine-learning benchmark on a large physical array.

The hardware record is nevertheless more substantial than that publication count suggests. The self-directed-channel memristor was fabricated by Kris Campbell at Boise State University. Knowm developed and patented the differential-pair kT-bit, the kT-RAM instruction set, and the system architecture. Physical devices, kT-bits, nodes, and crossbar arrays have been fabricated and measured. The following videos show a kT-neuron, a physical kT-RAM node, and the underlying kT-bit:

Knowm has also built crossbar arrays. The kT-RAM Server wirebonds crossbar dies into Raspberry Pi-controlled modules containing thousands of memristors. A two-part 2020 build log documents the hardware and resistance programming across 8×8 and 16×16 arrays, including a cell-by-cell rendering of the Knowm logo: Part 1 and Part 2.

Assessed by the same standards:

Pros

• The kT-RAM instruction set drives learning directly in the devices that hold the weights.
• Knowm’s patented differential pair stores a signed weight and its evidence in two physical conductances.
• Small arrays require no selector transistor. The Neural Lane design averages device variability rather than requiring identical devices.
• The device has been sold since 2016, and programmable nodes, bits, and crossbar arrays have been built.

Cons

• The kT-RAM literature is small, and independent replication is limited.
• Published machine-learning results were validated on an emulator (rather than integrated arrays).
• Knowm sells discrete devices and small arrays, not the large integrated circuits required for a system.

That leaves a concrete bet rather than a category label: the same physical state can store, infer, adapt, repair, and sample. kT-RAM still has to prove that stack at useful scale. If it does, it addresses both sides of AI’s power problem—the cost of moving weights to compute and the cost of moving them again to learn. That is why I consider it the strongest candidate, and why the next work is to build it. If you are interested in the technology, our IP page describes the portfolio and how to contact us.

Further resources#

• How 374 Papers Build a Signed Synaptic Weight, the survey behind the differential-pair claims above.
• A Taxonomy of Memristor Technologies, where the SDC memristor is scored as one family among twenty.
• AHaH Computing: From Metastable Switches to Attractors to Machine Learning, Nugent and Molter, PLoS ONE 2014.
• The Adaptive Power Problem, Alex Nugent, 2015.
• Cortical Computing with Thermodynamic RAM, Alex Nugent, 2014, where the name comes from.
• Memristor Crossbars as Easy as Raspberry Pi, Part 1 and Part 2, the kT-RAM Server build log.
• ktram-neural-core, the public kT-RAM emulator.
• The corpus behind this post: every in-scope paper with its deep-read fields, plus every company claim with its coding.